intel drivers: repair missing flush operations

after review of all intel drivers, found several instances where
drivers had the incorrect pattern of:
memory mapped write();
delay();

which should always be:
memory mapped write();
write flush(); /* aka memory mapped read */
delay();

explanation:
The reason for including the flush is that writes can be held
(posted) in PCI/PCIe bridges, but the read always has to complete
synchronously and therefore has to flush all pending writes to a
device.  If a write is held and followed by a delay, the delay
means nothing because the write may not have reached hardware
(maybe even not until the next read)

Signed-off-by: Jesse Brandeburg <jesse.brandeburg@intel.com>
Tested-by:  Aaron Brown <aaron.f.brown@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>

1 files changed, 3 insertions, 0 deletions

diff --git a/drivers/net/ixgbe/ixgbe_phy.c b/drivers/net/ixgbe/ixgbe_phy.c
index 735f686c3b36..f7ca3511b9fe 100644
--- a/drivers/net/ixgbe/ixgbe_phy.c
+++ b/drivers/net/ixgbe/ixgbe_phy.c
@@ -1585,6 +1585,7 @@ static s32 ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
         *i2cctl |= IXGBE_I2C_CLK_OUT;
 
         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
+        IXGBE_WRITE_FLUSH(hw);
 
         /* SCL rise time (1000ns) */
         udelay(IXGBE_I2C_T_RISE);
@@ -1605,6 +1606,7 @@ static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
         *i2cctl &= ~IXGBE_I2C_CLK_OUT;
 
         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
+        IXGBE_WRITE_FLUSH(hw);
 
         /* SCL fall time (300ns) */
         udelay(IXGBE_I2C_T_FALL);
@@ -1628,6 +1630,7 @@ static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
                 *i2cctl &= ~IXGBE_I2C_DATA_OUT;
 
         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
+        IXGBE_WRITE_FLUSH(hw);
 
         /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
         udelay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);