diff options
author | Alexander Duyck <alexander.h.duyck@intel.com> | 2009-11-19 07:42:01 -0500 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2009-11-20 13:00:11 -0500 |
commit | bb2ac47bcfd47ed9431ff1676ec8d79250c941c9 (patch) | |
tree | 2c717135feb469a84382f9532ed6dd70b1ef024c /drivers/net/igb/e1000_defines.h | |
parent | 2909c3f79d933b55bf2485addb1dca762210b6af (diff) |
igb: add support for 82580 MAC
This patch adds support for the 82580 MAC.
Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/igb/e1000_defines.h')
-rw-r--r-- | drivers/net/igb/e1000_defines.h | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/drivers/net/igb/e1000_defines.h b/drivers/net/igb/e1000_defines.h index 48fcab03b752..c58c4fdfee0c 100644 --- a/drivers/net/igb/e1000_defines.h +++ b/drivers/net/igb/e1000_defines.h | |||
@@ -49,6 +49,7 @@ | |||
49 | #define E1000_CTRL_EXT_PFRSTD 0x00004000 | 49 | #define E1000_CTRL_EXT_PFRSTD 0x00004000 |
50 | #define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000 | 50 | #define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000 |
51 | #define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00C00000 | 51 | #define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00C00000 |
52 | #define E1000_CTRL_EXT_LINK_MODE_1000BASE_KX 0x00400000 | ||
52 | #define E1000_CTRL_EXT_LINK_MODE_SGMII 0x00800000 | 53 | #define E1000_CTRL_EXT_LINK_MODE_SGMII 0x00800000 |
53 | #define E1000_CTRL_EXT_EIAME 0x01000000 | 54 | #define E1000_CTRL_EXT_EIAME 0x01000000 |
54 | #define E1000_CTRL_EXT_IRCA 0x00000001 | 55 | #define E1000_CTRL_EXT_IRCA 0x00000001 |
@@ -557,8 +558,12 @@ | |||
557 | #define NVM_ALT_MAC_ADDR_PTR 0x0037 | 558 | #define NVM_ALT_MAC_ADDR_PTR 0x0037 |
558 | #define NVM_CHECKSUM_REG 0x003F | 559 | #define NVM_CHECKSUM_REG 0x003F |
559 | 560 | ||
560 | #define E1000_NVM_CFG_DONE_PORT_0 0x40000 /* MNG config cycle done */ | 561 | #define E1000_NVM_CFG_DONE_PORT_0 0x040000 /* MNG config cycle done */ |
561 | #define E1000_NVM_CFG_DONE_PORT_1 0x80000 /* ...for second port */ | 562 | #define E1000_NVM_CFG_DONE_PORT_1 0x080000 /* ...for second port */ |
563 | #define E1000_NVM_CFG_DONE_PORT_2 0x100000 /* ...for third port */ | ||
564 | #define E1000_NVM_CFG_DONE_PORT_3 0x200000 /* ...for fourth port */ | ||
565 | |||
566 | #define NVM_82580_LAN_FUNC_OFFSET(a) (a ? (0x40 + (0x40 * a)) : 0) | ||
562 | 567 | ||
563 | /* Mask bits for fields in Word 0x0f of the NVM */ | 568 | /* Mask bits for fields in Word 0x0f of the NVM */ |
564 | #define NVM_WORD0F_PAUSE_MASK 0x3000 | 569 | #define NVM_WORD0F_PAUSE_MASK 0x3000 |
@@ -625,6 +630,7 @@ | |||
625 | */ | 630 | */ |
626 | #define M88E1111_I_PHY_ID 0x01410CC0 | 631 | #define M88E1111_I_PHY_ID 0x01410CC0 |
627 | #define IGP03E1000_E_PHY_ID 0x02A80390 | 632 | #define IGP03E1000_E_PHY_ID 0x02A80390 |
633 | #define I82580_I_PHY_ID 0x015403A0 | ||
628 | #define M88_VENDOR 0x0141 | 634 | #define M88_VENDOR 0x0141 |
629 | 635 | ||
630 | /* M88E1000 Specific Registers */ | 636 | /* M88E1000 Specific Registers */ |