diff options
author | Linus Torvalds <torvalds@ppc970.osdl.org> | 2005-04-16 18:20:36 -0400 |
---|---|---|
committer | Linus Torvalds <torvalds@ppc970.osdl.org> | 2005-04-16 18:20:36 -0400 |
commit | 1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch) | |
tree | 0bba044c4ce775e45a88a51686b5d9f90697ea9d /drivers/net/gt96100eth.c |
Linux-2.6.12-rc2
Initial git repository build. I'm not bothering with the full history,
even though we have it. We can create a separate "historical" git
archive of that later if we want to, and in the meantime it's about
3.2GB when imported into git - space that would just make the early
git days unnecessarily complicated, when we don't have a lot of good
infrastructure for it.
Let it rip!
Diffstat (limited to 'drivers/net/gt96100eth.c')
-rw-r--r-- | drivers/net/gt96100eth.c | 1569 |
1 files changed, 1569 insertions, 0 deletions
diff --git a/drivers/net/gt96100eth.c b/drivers/net/gt96100eth.c new file mode 100644 index 000000000000..666cfbbcf6d9 --- /dev/null +++ b/drivers/net/gt96100eth.c | |||
@@ -0,0 +1,1569 @@ | |||
1 | /* | ||
2 | * Copyright 2000, 2001 MontaVista Software Inc. | ||
3 | * Author: MontaVista Software, Inc. | ||
4 | * stevel@mvista.com or source@mvista.com | ||
5 | * | ||
6 | * This program is free software; you can distribute it and/or modify it | ||
7 | * under the terms of the GNU General Public License (Version 2) as | ||
8 | * published by the Free Software Foundation. | ||
9 | * | ||
10 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | ||
13 | * for more details. | ||
14 | * | ||
15 | * You should have received a copy of the GNU General Public License along | ||
16 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
17 | * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. | ||
18 | * | ||
19 | * Ethernet driver for the MIPS GT96100 Advanced Communication Controller. | ||
20 | * | ||
21 | * Revision history | ||
22 | * | ||
23 | * 11.11.2001 Moved to 2.4.14, ppopov@mvista.com. Modified driver to add | ||
24 | * proper gt96100A support. | ||
25 | * 12.05.2001 Moved eth port 0 to irq 3 (mapped to GT_SERINT0 on EV96100A) | ||
26 | * in order for both ports to work. Also cleaned up boot | ||
27 | * option support (mac address string parsing), fleshed out | ||
28 | * gt96100_cleanup_module(), and other general code cleanups | ||
29 | * <stevel@mvista.com>. | ||
30 | */ | ||
31 | #include <linux/module.h> | ||
32 | #include <linux/kernel.h> | ||
33 | #include <linux/string.h> | ||
34 | #include <linux/timer.h> | ||
35 | #include <linux/errno.h> | ||
36 | #include <linux/in.h> | ||
37 | #include <linux/ioport.h> | ||
38 | #include <linux/slab.h> | ||
39 | #include <linux/interrupt.h> | ||
40 | #include <linux/pci.h> | ||
41 | #include <linux/init.h> | ||
42 | #include <linux/netdevice.h> | ||
43 | #include <linux/etherdevice.h> | ||
44 | #include <linux/skbuff.h> | ||
45 | #include <linux/delay.h> | ||
46 | #include <linux/ctype.h> | ||
47 | #include <linux/bitops.h> | ||
48 | |||
49 | #include <asm/irq.h> | ||
50 | #include <asm/io.h> | ||
51 | |||
52 | #define DESC_BE 1 | ||
53 | #define DESC_DATA_BE 1 | ||
54 | |||
55 | #define GT96100_DEBUG 2 | ||
56 | |||
57 | #include "gt96100eth.h" | ||
58 | |||
59 | // prototypes | ||
60 | static void* dmaalloc(size_t size, dma_addr_t *dma_handle); | ||
61 | static void dmafree(size_t size, void *vaddr); | ||
62 | static void gt96100_delay(int msec); | ||
63 | static int gt96100_add_hash_entry(struct net_device *dev, | ||
64 | unsigned char* addr); | ||
65 | static void read_mib_counters(struct gt96100_private *gp); | ||
66 | static int read_MII(int phy_addr, u32 reg); | ||
67 | static int write_MII(int phy_addr, u32 reg, u16 data); | ||
68 | static int gt96100_init_module(void); | ||
69 | static void gt96100_cleanup_module(void); | ||
70 | static void dump_MII(int dbg_lvl, struct net_device *dev); | ||
71 | static void dump_tx_desc(int dbg_lvl, struct net_device *dev, int i); | ||
72 | static void dump_rx_desc(int dbg_lvl, struct net_device *dev, int i); | ||
73 | static void dump_skb(int dbg_lvl, struct net_device *dev, | ||
74 | struct sk_buff *skb); | ||
75 | static void dump_hw_addr(int dbg_lvl, struct net_device *dev, | ||
76 | const char* pfx, unsigned char* addr_str); | ||
77 | static void update_stats(struct gt96100_private *gp); | ||
78 | static void abort(struct net_device *dev, u32 abort_bits); | ||
79 | static void hard_stop(struct net_device *dev); | ||
80 | static void enable_ether_irq(struct net_device *dev); | ||
81 | static void disable_ether_irq(struct net_device *dev); | ||
82 | static int gt96100_probe1(struct pci_dev *pci, int port_num); | ||
83 | static void reset_tx(struct net_device *dev); | ||
84 | static void reset_rx(struct net_device *dev); | ||
85 | static int gt96100_check_tx_consistent(struct gt96100_private *gp); | ||
86 | static int gt96100_init(struct net_device *dev); | ||
87 | static int gt96100_open(struct net_device *dev); | ||
88 | static int gt96100_close(struct net_device *dev); | ||
89 | static int gt96100_tx(struct sk_buff *skb, struct net_device *dev); | ||
90 | static int gt96100_rx(struct net_device *dev, u32 status); | ||
91 | static irqreturn_t gt96100_interrupt(int irq, void *dev_id, struct pt_regs *regs); | ||
92 | static void gt96100_tx_timeout(struct net_device *dev); | ||
93 | static void gt96100_set_rx_mode(struct net_device *dev); | ||
94 | static struct net_device_stats* gt96100_get_stats(struct net_device *dev); | ||
95 | |||
96 | extern char * __init prom_getcmdline(void); | ||
97 | |||
98 | static int max_interrupt_work = 32; | ||
99 | |||
100 | #define nibswap(x) ((((x) >> 4) & 0x0f) | (((x) << 4) & 0xf0)) | ||
101 | |||
102 | #define RUN_AT(x) (jiffies + (x)) | ||
103 | |||
104 | // For reading/writing 32-bit words and half-words from/to DMA memory | ||
105 | #ifdef DESC_BE | ||
106 | #define cpu_to_dma32 cpu_to_be32 | ||
107 | #define dma32_to_cpu be32_to_cpu | ||
108 | #define cpu_to_dma16 cpu_to_be16 | ||
109 | #define dma16_to_cpu be16_to_cpu | ||
110 | #else | ||
111 | #define cpu_to_dma32 cpu_to_le32 | ||
112 | #define dma32_to_cpu le32_to_cpu | ||
113 | #define cpu_to_dma16 cpu_to_le16 | ||
114 | #define dma16_to_cpu le16_to_cpu | ||
115 | #endif | ||
116 | |||
117 | static char mac0[18] = "00.02.03.04.05.06"; | ||
118 | static char mac1[18] = "00.01.02.03.04.05"; | ||
119 | MODULE_PARM(mac0, "c18"); | ||
120 | MODULE_PARM(mac1, "c18"); | ||
121 | MODULE_PARM_DESC(mac0, "MAC address for GT96100 ethernet port 0"); | ||
122 | MODULE_PARM_DESC(mac1, "MAC address for GT96100 ethernet port 1"); | ||
123 | |||
124 | /* | ||
125 | * Info for the GT96100 ethernet controller's ports. | ||
126 | */ | ||
127 | static struct gt96100_if_t { | ||
128 | struct net_device *dev; | ||
129 | unsigned int iobase; // IO Base address of this port | ||
130 | int irq; // IRQ number of this port | ||
131 | char *mac_str; | ||
132 | } gt96100_iflist[NUM_INTERFACES] = { | ||
133 | { | ||
134 | NULL, | ||
135 | GT96100_ETH0_BASE, GT96100_ETHER0_IRQ, | ||
136 | mac0 | ||
137 | }, | ||
138 | { | ||
139 | NULL, | ||
140 | GT96100_ETH1_BASE, GT96100_ETHER1_IRQ, | ||
141 | mac1 | ||
142 | } | ||
143 | }; | ||
144 | |||
145 | static inline const char* | ||
146 | chip_name(int chip_rev) | ||
147 | { | ||
148 | switch (chip_rev) { | ||
149 | case REV_GT96100: | ||
150 | return "GT96100"; | ||
151 | case REV_GT96100A_1: | ||
152 | case REV_GT96100A: | ||
153 | return "GT96100A"; | ||
154 | default: | ||
155 | return "Unknown GT96100"; | ||
156 | } | ||
157 | } | ||
158 | |||
159 | /* | ||
160 | DMA memory allocation, derived from pci_alloc_consistent. | ||
161 | */ | ||
162 | static void * dmaalloc(size_t size, dma_addr_t *dma_handle) | ||
163 | { | ||
164 | void *ret; | ||
165 | |||
166 | ret = (void *)__get_free_pages(GFP_ATOMIC | GFP_DMA, get_order(size)); | ||
167 | |||
168 | if (ret != NULL) { | ||
169 | dma_cache_inv((unsigned long)ret, size); | ||
170 | if (dma_handle != NULL) | ||
171 | *dma_handle = virt_to_phys(ret); | ||
172 | |||
173 | /* bump virtual address up to non-cached area */ | ||
174 | ret = (void*)KSEG1ADDR(ret); | ||
175 | } | ||
176 | |||
177 | return ret; | ||
178 | } | ||
179 | |||
180 | static void dmafree(size_t size, void *vaddr) | ||
181 | { | ||
182 | vaddr = (void*)KSEG0ADDR(vaddr); | ||
183 | free_pages((unsigned long)vaddr, get_order(size)); | ||
184 | } | ||
185 | |||
186 | static void gt96100_delay(int ms) | ||
187 | { | ||
188 | if (in_interrupt()) | ||
189 | return; | ||
190 | else | ||
191 | msleep_interruptible(ms); | ||
192 | } | ||
193 | |||
194 | static int | ||
195 | parse_mac_addr(struct net_device *dev, char* macstr) | ||
196 | { | ||
197 | int i, j; | ||
198 | unsigned char result, value; | ||
199 | |||
200 | for (i=0; i<6; i++) { | ||
201 | result = 0; | ||
202 | if (i != 5 && *(macstr+2) != '.') { | ||
203 | err(__FILE__ "invalid mac address format: %d %c\n", | ||
204 | i, *(macstr+2)); | ||
205 | return -EINVAL; | ||
206 | } | ||
207 | |||
208 | for (j=0; j<2; j++) { | ||
209 | if (isxdigit(*macstr) && | ||
210 | (value = isdigit(*macstr) ? *macstr-'0' : | ||
211 | toupper(*macstr)-'A'+10) < 16) { | ||
212 | result = result*16 + value; | ||
213 | macstr++; | ||
214 | } else { | ||
215 | err(__FILE__ "invalid mac address " | ||
216 | "character: %c\n", *macstr); | ||
217 | return -EINVAL; | ||
218 | } | ||
219 | } | ||
220 | |||
221 | macstr++; // step over '.' | ||
222 | dev->dev_addr[i] = result; | ||
223 | } | ||
224 | |||
225 | return 0; | ||
226 | } | ||
227 | |||
228 | |||
229 | static int | ||
230 | read_MII(int phy_addr, u32 reg) | ||
231 | { | ||
232 | int timedout = 20; | ||
233 | u32 smir = smirOpCode | (phy_addr << smirPhyAdBit) | | ||
234 | (reg << smirRegAdBit); | ||
235 | |||
236 | // wait for last operation to complete | ||
237 | while (GT96100_READ(GT96100_ETH_SMI_REG) & smirBusy) { | ||
238 | // snooze for 1 msec and check again | ||
239 | gt96100_delay(1); | ||
240 | |||
241 | if (--timedout == 0) { | ||
242 | printk(KERN_ERR "%s: busy timeout!!\n", __FUNCTION__); | ||
243 | return -ENODEV; | ||
244 | } | ||
245 | } | ||
246 | |||
247 | GT96100_WRITE(GT96100_ETH_SMI_REG, smir); | ||
248 | |||
249 | timedout = 20; | ||
250 | // wait for read to complete | ||
251 | while (!((smir = GT96100_READ(GT96100_ETH_SMI_REG)) & smirReadValid)) { | ||
252 | // snooze for 1 msec and check again | ||
253 | gt96100_delay(1); | ||
254 | |||
255 | if (--timedout == 0) { | ||
256 | printk(KERN_ERR "%s: timeout!!\n", __FUNCTION__); | ||
257 | return -ENODEV; | ||
258 | } | ||
259 | } | ||
260 | |||
261 | return (int)(smir & smirDataMask); | ||
262 | } | ||
263 | |||
264 | static void | ||
265 | dump_tx_desc(int dbg_lvl, struct net_device *dev, int i) | ||
266 | { | ||
267 | struct gt96100_private *gp = netdev_priv(dev); | ||
268 | gt96100_td_t *td = &gp->tx_ring[i]; | ||
269 | |||
270 | dbg(dbg_lvl, "Tx descriptor at 0x%08lx:\n", virt_to_phys(td)); | ||
271 | dbg(dbg_lvl, | ||
272 | " cmdstat=%04x, byte_cnt=%04x, buff_ptr=%04x, next=%04x\n", | ||
273 | dma32_to_cpu(td->cmdstat), | ||
274 | dma16_to_cpu(td->byte_cnt), | ||
275 | dma32_to_cpu(td->buff_ptr), | ||
276 | dma32_to_cpu(td->next)); | ||
277 | } | ||
278 | |||
279 | static void | ||
280 | dump_rx_desc(int dbg_lvl, struct net_device *dev, int i) | ||
281 | { | ||
282 | struct gt96100_private *gp = netdev_priv(dev); | ||
283 | gt96100_rd_t *rd = &gp->rx_ring[i]; | ||
284 | |||
285 | dbg(dbg_lvl, "Rx descriptor at 0x%08lx:\n", virt_to_phys(rd)); | ||
286 | dbg(dbg_lvl, " cmdstat=%04x, buff_sz=%04x, byte_cnt=%04x, " | ||
287 | "buff_ptr=%04x, next=%04x\n", | ||
288 | dma32_to_cpu(rd->cmdstat), | ||
289 | dma16_to_cpu(rd->buff_sz), | ||
290 | dma16_to_cpu(rd->byte_cnt), | ||
291 | dma32_to_cpu(rd->buff_ptr), | ||
292 | dma32_to_cpu(rd->next)); | ||
293 | } | ||
294 | |||
295 | static int | ||
296 | write_MII(int phy_addr, u32 reg, u16 data) | ||
297 | { | ||
298 | int timedout = 20; | ||
299 | u32 smir = (phy_addr << smirPhyAdBit) | | ||
300 | (reg << smirRegAdBit) | data; | ||
301 | |||
302 | // wait for last operation to complete | ||
303 | while (GT96100_READ(GT96100_ETH_SMI_REG) & smirBusy) { | ||
304 | // snooze for 1 msec and check again | ||
305 | gt96100_delay(1); | ||
306 | |||
307 | if (--timedout == 0) { | ||
308 | printk(KERN_ERR "%s: busy timeout!!\n", __FUNCTION__); | ||
309 | return -1; | ||
310 | } | ||
311 | } | ||
312 | |||
313 | GT96100_WRITE(GT96100_ETH_SMI_REG, smir); | ||
314 | return 0; | ||
315 | } | ||
316 | |||
317 | static void | ||
318 | dump_MII(int dbg_lvl, struct net_device *dev) | ||
319 | { | ||
320 | int i, val; | ||
321 | struct gt96100_private *gp = netdev_priv(dev); | ||
322 | |||
323 | if (dbg_lvl <= GT96100_DEBUG) { | ||
324 | for (i=0; i<7; i++) { | ||
325 | if ((val = read_MII(gp->phy_addr, i)) >= 0) | ||
326 | printk("MII Reg %d=%x\n", i, val); | ||
327 | } | ||
328 | for (i=16; i<21; i++) { | ||
329 | if ((val = read_MII(gp->phy_addr, i)) >= 0) | ||
330 | printk("MII Reg %d=%x\n", i, val); | ||
331 | } | ||
332 | } | ||
333 | } | ||
334 | |||
335 | static void | ||
336 | dump_hw_addr(int dbg_lvl, struct net_device *dev, const char* pfx, | ||
337 | unsigned char* addr_str) | ||
338 | { | ||
339 | int i; | ||
340 | char buf[100], octet[5]; | ||
341 | |||
342 | if (dbg_lvl <= GT96100_DEBUG) { | ||
343 | strcpy(buf, pfx); | ||
344 | for (i = 0; i < 6; i++) { | ||
345 | sprintf(octet, "%2.2x%s", | ||
346 | addr_str[i], i<5 ? ":" : "\n"); | ||
347 | strcat(buf, octet); | ||
348 | } | ||
349 | info("%s", buf); | ||
350 | } | ||
351 | } | ||
352 | |||
353 | |||
354 | static void | ||
355 | dump_skb(int dbg_lvl, struct net_device *dev, struct sk_buff *skb) | ||
356 | { | ||
357 | int i; | ||
358 | unsigned char* skbdata; | ||
359 | |||
360 | if (dbg_lvl <= GT96100_DEBUG) { | ||
361 | dbg(dbg_lvl, "%s: skb=%p, skb->data=%p, skb->len=%d\n", | ||
362 | __FUNCTION__, skb, skb->data, skb->len); | ||
363 | |||
364 | skbdata = (unsigned char*)KSEG1ADDR(skb->data); | ||
365 | |||
366 | for (i=0; i<skb->len; i++) { | ||
367 | if (!(i % 16)) | ||
368 | printk(KERN_DEBUG "\n %3.3x: %2.2x,", | ||
369 | i, skbdata[i]); | ||
370 | else | ||
371 | printk(KERN_DEBUG "%2.2x,", skbdata[i]); | ||
372 | } | ||
373 | printk(KERN_DEBUG "\n"); | ||
374 | } | ||
375 | } | ||
376 | |||
377 | |||
378 | static int | ||
379 | gt96100_add_hash_entry(struct net_device *dev, unsigned char* addr) | ||
380 | { | ||
381 | struct gt96100_private *gp = netdev_priv(dev); | ||
382 | //u16 hashResult, stmp; | ||
383 | //unsigned char ctmp, hash_ea[6]; | ||
384 | u32 tblEntry1, tblEntry0, *tblEntryAddr; | ||
385 | int i; | ||
386 | |||
387 | tblEntry1 = hteValid | hteRD; | ||
388 | tblEntry1 |= (u32)addr[5] << 3; | ||
389 | tblEntry1 |= (u32)addr[4] << 11; | ||
390 | tblEntry1 |= (u32)addr[3] << 19; | ||
391 | tblEntry1 |= ((u32)addr[2] & 0x1f) << 27; | ||
392 | dbg(3, "%s: tblEntry1=%x\n", __FUNCTION__, tblEntry1); | ||
393 | tblEntry0 = ((u32)addr[2] >> 5) & 0x07; | ||
394 | tblEntry0 |= (u32)addr[1] << 3; | ||
395 | tblEntry0 |= (u32)addr[0] << 11; | ||
396 | dbg(3, "%s: tblEntry0=%x\n", __FUNCTION__, tblEntry0); | ||
397 | |||
398 | #if 0 | ||
399 | |||
400 | for (i=0; i<6; i++) { | ||
401 | // nibble swap | ||
402 | ctmp = nibswap(addr[i]); | ||
403 | // invert every nibble | ||
404 | hash_ea[i] = ((ctmp&1)<<3) | ((ctmp&8)>>3) | | ||
405 | ((ctmp&2)<<1) | ((ctmp&4)>>1); | ||
406 | hash_ea[i] |= ((ctmp&0x10)<<3) | ((ctmp&0x80)>>3) | | ||
407 | ((ctmp&0x20)<<1) | ((ctmp&0x40)>>1); | ||
408 | } | ||
409 | |||
410 | dump_hw_addr(3, dev, "%s: nib swap/invt addr=", __FUNCTION__, hash_ea); | ||
411 | |||
412 | if (gp->hash_mode == 0) { | ||
413 | hashResult = ((u16)hash_ea[0] & 0xfc) << 7; | ||
414 | stmp = ((u16)hash_ea[0] & 0x03) | | ||
415 | (((u16)hash_ea[1] & 0x7f) << 2); | ||
416 | stmp ^= (((u16)hash_ea[1] >> 7) & 0x01) | | ||
417 | ((u16)hash_ea[2] << 1); | ||
418 | stmp ^= (u16)hash_ea[3] | (((u16)hash_ea[4] & 1) << 8); | ||
419 | hashResult |= stmp; | ||
420 | } else { | ||
421 | return -1; // don't support hash mode 1 | ||
422 | } | ||
423 | |||
424 | dbg(3, "%s: hashResult=%x\n", __FUNCTION__, hashResult); | ||
425 | |||
426 | tblEntryAddr = | ||
427 | (u32 *)(&gp->hash_table[((u32)hashResult & 0x7ff) << 3]); | ||
428 | |||
429 | dbg(3, "%s: tblEntryAddr=%p\n", tblEntryAddr, __FUNCTION__); | ||
430 | |||
431 | for (i=0; i<HASH_HOP_NUMBER; i++) { | ||
432 | if ((*tblEntryAddr & hteValid) && | ||
433 | !(*tblEntryAddr & hteSkip)) { | ||
434 | // This entry is already occupied, go to next entry | ||
435 | tblEntryAddr += 2; | ||
436 | dbg(3, "%s: skipping to %p\n", __FUNCTION__, | ||
437 | tblEntryAddr); | ||
438 | } else { | ||
439 | memset(tblEntryAddr, 0, 8); | ||
440 | tblEntryAddr[1] = cpu_to_dma32(tblEntry1); | ||
441 | tblEntryAddr[0] = cpu_to_dma32(tblEntry0); | ||
442 | break; | ||
443 | } | ||
444 | } | ||
445 | |||
446 | if (i >= HASH_HOP_NUMBER) { | ||
447 | err("%s: expired!\n", __FUNCTION__); | ||
448 | return -1; // Couldn't find an unused entry | ||
449 | } | ||
450 | |||
451 | #else | ||
452 | |||
453 | tblEntryAddr = (u32 *)gp->hash_table; | ||
454 | for (i=0; i<RX_HASH_TABLE_SIZE/4; i+=2) { | ||
455 | tblEntryAddr[i+1] = cpu_to_dma32(tblEntry1); | ||
456 | tblEntryAddr[i] = cpu_to_dma32(tblEntry0); | ||
457 | } | ||
458 | |||
459 | #endif | ||
460 | |||
461 | return 0; | ||
462 | } | ||
463 | |||
464 | |||
465 | static void | ||
466 | read_mib_counters(struct gt96100_private *gp) | ||
467 | { | ||
468 | u32* mib_regs = (u32*)&gp->mib; | ||
469 | int i; | ||
470 | |||
471 | for (i=0; i<sizeof(mib_counters_t)/sizeof(u32); i++) | ||
472 | mib_regs[i] = GT96100ETH_READ(gp, GT96100_ETH_MIB_COUNT_BASE + | ||
473 | i*sizeof(u32)); | ||
474 | } | ||
475 | |||
476 | |||
477 | static void | ||
478 | update_stats(struct gt96100_private *gp) | ||
479 | { | ||
480 | mib_counters_t *mib = &gp->mib; | ||
481 | struct net_device_stats *stats = &gp->stats; | ||
482 | |||
483 | read_mib_counters(gp); | ||
484 | |||
485 | stats->rx_packets = mib->totalFramesReceived; | ||
486 | stats->tx_packets = mib->framesSent; | ||
487 | stats->rx_bytes = mib->totalByteReceived; | ||
488 | stats->tx_bytes = mib->byteSent; | ||
489 | stats->rx_errors = mib->totalFramesReceived - mib->framesReceived; | ||
490 | //the tx error counters are incremented by the ISR | ||
491 | //rx_dropped incremented by gt96100_rx | ||
492 | //tx_dropped incremented by gt96100_tx | ||
493 | stats->multicast = mib->multicastFramesReceived; | ||
494 | // collisions incremented by gt96100_tx_complete | ||
495 | stats->rx_length_errors = mib->oversizeFrames + mib->fragments; | ||
496 | // The RxError condition means the Rx DMA encountered a | ||
497 | // CPU owned descriptor, which, if things are working as | ||
498 | // they should, means the Rx ring has overflowed. | ||
499 | stats->rx_over_errors = mib->macRxError; | ||
500 | stats->rx_crc_errors = mib->cRCError; | ||
501 | } | ||
502 | |||
503 | static void | ||
504 | abort(struct net_device *dev, u32 abort_bits) | ||
505 | { | ||
506 | struct gt96100_private *gp = netdev_priv(dev); | ||
507 | int timedout = 100; // wait up to 100 msec for hard stop to complete | ||
508 | |||
509 | dbg(3, "%s\n", __FUNCTION__); | ||
510 | |||
511 | // Return if neither Rx or Tx abort bits are set | ||
512 | if (!(abort_bits & (sdcmrAR | sdcmrAT))) | ||
513 | return; | ||
514 | |||
515 | // make sure only the Rx/Tx abort bits are set | ||
516 | abort_bits &= (sdcmrAR | sdcmrAT); | ||
517 | |||
518 | spin_lock(&gp->lock); | ||
519 | |||
520 | // abort any Rx/Tx DMA immediately | ||
521 | GT96100ETH_WRITE(gp, GT96100_ETH_SDMA_COMM, abort_bits); | ||
522 | |||
523 | dbg(3, "%s: SDMA comm = %x\n", __FUNCTION__, | ||
524 | GT96100ETH_READ(gp, GT96100_ETH_SDMA_COMM)); | ||
525 | |||
526 | // wait for abort to complete | ||
527 | while (GT96100ETH_READ(gp, GT96100_ETH_SDMA_COMM) & abort_bits) { | ||
528 | // snooze for 1 msec and check again | ||
529 | gt96100_delay(1); | ||
530 | |||
531 | if (--timedout == 0) { | ||
532 | err("%s: timeout!!\n", __FUNCTION__); | ||
533 | break; | ||
534 | } | ||
535 | } | ||
536 | |||
537 | spin_unlock(&gp->lock); | ||
538 | } | ||
539 | |||
540 | |||
541 | static void | ||
542 | hard_stop(struct net_device *dev) | ||
543 | { | ||
544 | struct gt96100_private *gp = netdev_priv(dev); | ||
545 | |||
546 | dbg(3, "%s\n", __FUNCTION__); | ||
547 | |||
548 | disable_ether_irq(dev); | ||
549 | |||
550 | abort(dev, sdcmrAR | sdcmrAT); | ||
551 | |||
552 | // disable port | ||
553 | GT96100ETH_WRITE(gp, GT96100_ETH_PORT_CONFIG, 0); | ||
554 | } | ||
555 | |||
556 | |||
557 | static void | ||
558 | enable_ether_irq(struct net_device *dev) | ||
559 | { | ||
560 | struct gt96100_private *gp = netdev_priv(dev); | ||
561 | u32 intMask; | ||
562 | /* | ||
563 | * route ethernet interrupt to GT_SERINT0 for port 0, | ||
564 | * GT_INT0 for port 1. | ||
565 | */ | ||
566 | int intr_mask_reg = (gp->port_num == 0) ? | ||
567 | GT96100_SERINT0_MASK : GT96100_INT0_HIGH_MASK; | ||
568 | |||
569 | if (gp->chip_rev >= REV_GT96100A_1) { | ||
570 | intMask = icrTxBufferLow | icrTxEndLow | | ||
571 | icrTxErrorLow | icrRxOVR | icrTxUdr | | ||
572 | icrRxBufferQ0 | icrRxErrorQ0 | | ||
573 | icrMIIPhySTC | icrEtherIntSum; | ||
574 | } | ||
575 | else { | ||
576 | intMask = icrTxBufferLow | icrTxEndLow | | ||
577 | icrTxErrorLow | icrRxOVR | icrTxUdr | | ||
578 | icrRxBuffer | icrRxError | | ||
579 | icrMIIPhySTC | icrEtherIntSum; | ||
580 | } | ||
581 | |||
582 | // unmask interrupts | ||
583 | GT96100ETH_WRITE(gp, GT96100_ETH_INT_MASK, intMask); | ||
584 | |||
585 | intMask = GT96100_READ(intr_mask_reg); | ||
586 | intMask |= 1<<gp->port_num; | ||
587 | GT96100_WRITE(intr_mask_reg, intMask); | ||
588 | } | ||
589 | |||
590 | static void | ||
591 | disable_ether_irq(struct net_device *dev) | ||
592 | { | ||
593 | struct gt96100_private *gp = netdev_priv(dev); | ||
594 | u32 intMask; | ||
595 | int intr_mask_reg = (gp->port_num == 0) ? | ||
596 | GT96100_SERINT0_MASK : GT96100_INT0_HIGH_MASK; | ||
597 | |||
598 | intMask = GT96100_READ(intr_mask_reg); | ||
599 | intMask &= ~(1<<gp->port_num); | ||
600 | GT96100_WRITE(intr_mask_reg, intMask); | ||
601 | |||
602 | GT96100ETH_WRITE(gp, GT96100_ETH_INT_MASK, 0); | ||
603 | } | ||
604 | |||
605 | |||
606 | /* | ||
607 | * Init GT96100 ethernet controller driver | ||
608 | */ | ||
609 | static int gt96100_init_module(void) | ||
610 | { | ||
611 | struct pci_dev *pci; | ||
612 | int i, retval=0; | ||
613 | u32 cpuConfig; | ||
614 | |||
615 | /* | ||
616 | * Stupid probe because this really isn't a PCI device | ||
617 | */ | ||
618 | if (!(pci = pci_find_device(PCI_VENDOR_ID_MARVELL, | ||
619 | PCI_DEVICE_ID_MARVELL_GT96100, NULL)) && | ||
620 | !(pci = pci_find_device(PCI_VENDOR_ID_MARVELL, | ||
621 | PCI_DEVICE_ID_MARVELL_GT96100A, NULL))) { | ||
622 | printk(KERN_ERR __FILE__ ": GT96100 not found!\n"); | ||
623 | return -ENODEV; | ||
624 | } | ||
625 | |||
626 | cpuConfig = GT96100_READ(GT96100_CPU_INTERF_CONFIG); | ||
627 | if (cpuConfig & (1<<12)) { | ||
628 | printk(KERN_ERR __FILE__ | ||
629 | ": must be in Big Endian mode!\n"); | ||
630 | return -ENODEV; | ||
631 | } | ||
632 | |||
633 | for (i=0; i < NUM_INTERFACES; i++) | ||
634 | retval |= gt96100_probe1(pci, i); | ||
635 | |||
636 | return retval; | ||
637 | } | ||
638 | |||
639 | static int __init gt96100_probe1(struct pci_dev *pci, int port_num) | ||
640 | { | ||
641 | struct gt96100_private *gp = NULL; | ||
642 | struct gt96100_if_t *gtif = >96100_iflist[port_num]; | ||
643 | int phy_addr, phy_id1, phy_id2; | ||
644 | u32 phyAD; | ||
645 | int retval; | ||
646 | unsigned char chip_rev; | ||
647 | struct net_device *dev = NULL; | ||
648 | |||
649 | if (gtif->irq < 0) { | ||
650 | printk(KERN_ERR "%s: irq unknown - probing not supported\n", | ||
651 | __FUNCTION__); | ||
652 | return -ENODEV; | ||
653 | } | ||
654 | |||
655 | pci_read_config_byte(pci, PCI_REVISION_ID, &chip_rev); | ||
656 | |||
657 | if (chip_rev >= REV_GT96100A_1) { | ||
658 | phyAD = GT96100_READ(GT96100_ETH_PHY_ADDR_REG); | ||
659 | phy_addr = (phyAD >> (5*port_num)) & 0x1f; | ||
660 | } else { | ||
661 | /* | ||
662 | * not sure what's this about -- probably a gt bug | ||
663 | */ | ||
664 | phy_addr = port_num; | ||
665 | phyAD = GT96100_READ(GT96100_ETH_PHY_ADDR_REG); | ||
666 | phyAD &= ~(0x1f << (port_num*5)); | ||
667 | phyAD |= phy_addr << (port_num*5); | ||
668 | GT96100_WRITE(GT96100_ETH_PHY_ADDR_REG, phyAD); | ||
669 | } | ||
670 | |||
671 | // probe for the external PHY | ||
672 | if ((phy_id1 = read_MII(phy_addr, 2)) <= 0 || | ||
673 | (phy_id2 = read_MII(phy_addr, 3)) <= 0) { | ||
674 | printk(KERN_ERR "%s: no PHY found on MII%d\n", __FUNCTION__, port_num); | ||
675 | return -ENODEV; | ||
676 | } | ||
677 | |||
678 | if (!request_region(gtif->iobase, GT96100_ETH_IO_SIZE, "GT96100ETH")) { | ||
679 | printk(KERN_ERR "%s: request_region failed\n", __FUNCTION__); | ||
680 | return -EBUSY; | ||
681 | } | ||
682 | |||
683 | dev = alloc_etherdev(sizeof(struct gt96100_private)); | ||
684 | if (!dev) | ||
685 | goto out; | ||
686 | gtif->dev = dev; | ||
687 | |||
688 | /* private struct aligned and zeroed by alloc_etherdev */ | ||
689 | /* Fill in the 'dev' fields. */ | ||
690 | dev->base_addr = gtif->iobase; | ||
691 | dev->irq = gtif->irq; | ||
692 | |||
693 | if ((retval = parse_mac_addr(dev, gtif->mac_str))) { | ||
694 | err("%s: MAC address parse failed\n", __FUNCTION__); | ||
695 | retval = -EINVAL; | ||
696 | goto out1; | ||
697 | } | ||
698 | |||
699 | gp = netdev_priv(dev); | ||
700 | |||
701 | memset(gp, 0, sizeof(*gp)); // clear it | ||
702 | |||
703 | gp->port_num = port_num; | ||
704 | gp->io_size = GT96100_ETH_IO_SIZE; | ||
705 | gp->port_offset = port_num * GT96100_ETH_IO_SIZE; | ||
706 | gp->phy_addr = phy_addr; | ||
707 | gp->chip_rev = chip_rev; | ||
708 | |||
709 | info("%s found at 0x%x, irq %d\n", | ||
710 | chip_name(gp->chip_rev), gtif->iobase, gtif->irq); | ||
711 | dump_hw_addr(0, dev, "HW Address ", dev->dev_addr); | ||
712 | info("%s chip revision=%d\n", chip_name(gp->chip_rev), gp->chip_rev); | ||
713 | info("%s ethernet port %d\n", chip_name(gp->chip_rev), gp->port_num); | ||
714 | info("external PHY ID1=0x%04x, ID2=0x%04x\n", phy_id1, phy_id2); | ||
715 | |||
716 | // Allocate Rx and Tx descriptor rings | ||
717 | if (gp->rx_ring == NULL) { | ||
718 | // All descriptors in ring must be 16-byte aligned | ||
719 | gp->rx_ring = dmaalloc(sizeof(gt96100_rd_t) * RX_RING_SIZE | ||
720 | + sizeof(gt96100_td_t) * TX_RING_SIZE, | ||
721 | &gp->rx_ring_dma); | ||
722 | if (gp->rx_ring == NULL) { | ||
723 | retval = -ENOMEM; | ||
724 | goto out1; | ||
725 | } | ||
726 | |||
727 | gp->tx_ring = (gt96100_td_t *)(gp->rx_ring + RX_RING_SIZE); | ||
728 | gp->tx_ring_dma = | ||
729 | gp->rx_ring_dma + sizeof(gt96100_rd_t) * RX_RING_SIZE; | ||
730 | } | ||
731 | |||
732 | // Allocate the Rx Data Buffers | ||
733 | if (gp->rx_buff == NULL) { | ||
734 | gp->rx_buff = dmaalloc(PKT_BUF_SZ*RX_RING_SIZE, | ||
735 | &gp->rx_buff_dma); | ||
736 | if (gp->rx_buff == NULL) { | ||
737 | retval = -ENOMEM; | ||
738 | goto out2; | ||
739 | } | ||
740 | } | ||
741 | |||
742 | dbg(3, "%s: rx_ring=%p, tx_ring=%p\n", __FUNCTION__, | ||
743 | gp->rx_ring, gp->tx_ring); | ||
744 | |||
745 | // Allocate Rx Hash Table | ||
746 | if (gp->hash_table == NULL) { | ||
747 | gp->hash_table = (char*)dmaalloc(RX_HASH_TABLE_SIZE, | ||
748 | &gp->hash_table_dma); | ||
749 | if (gp->hash_table == NULL) { | ||
750 | retval = -ENOMEM; | ||
751 | goto out3; | ||
752 | } | ||
753 | } | ||
754 | |||
755 | dbg(3, "%s: hash=%p\n", __FUNCTION__, gp->hash_table); | ||
756 | |||
757 | spin_lock_init(&gp->lock); | ||
758 | |||
759 | dev->open = gt96100_open; | ||
760 | dev->hard_start_xmit = gt96100_tx; | ||
761 | dev->stop = gt96100_close; | ||
762 | dev->get_stats = gt96100_get_stats; | ||
763 | //dev->do_ioctl = gt96100_ioctl; | ||
764 | dev->set_multicast_list = gt96100_set_rx_mode; | ||
765 | dev->tx_timeout = gt96100_tx_timeout; | ||
766 | dev->watchdog_timeo = GT96100ETH_TX_TIMEOUT; | ||
767 | |||
768 | retval = register_netdev(dev); | ||
769 | if (retval) | ||
770 | goto out4; | ||
771 | return 0; | ||
772 | |||
773 | out4: | ||
774 | dmafree(RX_HASH_TABLE_SIZE, gp->hash_table_dma); | ||
775 | out3: | ||
776 | dmafree(PKT_BUF_SZ*RX_RING_SIZE, gp->rx_buff); | ||
777 | out2: | ||
778 | dmafree(sizeof(gt96100_rd_t) * RX_RING_SIZE | ||
779 | + sizeof(gt96100_td_t) * TX_RING_SIZE, | ||
780 | gp->rx_ring); | ||
781 | out1: | ||
782 | free_netdev (dev); | ||
783 | out: | ||
784 | release_region(gtif->iobase, GT96100_ETH_IO_SIZE); | ||
785 | |||
786 | err("%s failed. Returns %d\n", __FUNCTION__, retval); | ||
787 | return retval; | ||
788 | } | ||
789 | |||
790 | |||
791 | static void | ||
792 | reset_tx(struct net_device *dev) | ||
793 | { | ||
794 | struct gt96100_private *gp = netdev_priv(dev); | ||
795 | int i; | ||
796 | |||
797 | abort(dev, sdcmrAT); | ||
798 | |||
799 | for (i=0; i<TX_RING_SIZE; i++) { | ||
800 | if (gp->tx_skbuff[i]) { | ||
801 | if (in_interrupt()) | ||
802 | dev_kfree_skb_irq(gp->tx_skbuff[i]); | ||
803 | else | ||
804 | dev_kfree_skb(gp->tx_skbuff[i]); | ||
805 | gp->tx_skbuff[i] = NULL; | ||
806 | } | ||
807 | |||
808 | gp->tx_ring[i].cmdstat = 0; // CPU owns | ||
809 | gp->tx_ring[i].byte_cnt = 0; | ||
810 | gp->tx_ring[i].buff_ptr = 0; | ||
811 | gp->tx_ring[i].next = | ||
812 | cpu_to_dma32(gp->tx_ring_dma + | ||
813 | sizeof(gt96100_td_t) * (i+1)); | ||
814 | dump_tx_desc(4, dev, i); | ||
815 | } | ||
816 | /* Wrap the ring. */ | ||
817 | gp->tx_ring[i-1].next = cpu_to_dma32(gp->tx_ring_dma); | ||
818 | |||
819 | // setup only the lowest priority TxCDP reg | ||
820 | GT96100ETH_WRITE(gp, GT96100_ETH_CURR_TX_DESC_PTR0, gp->tx_ring_dma); | ||
821 | GT96100ETH_WRITE(gp, GT96100_ETH_CURR_TX_DESC_PTR1, 0); | ||
822 | |||
823 | // init Tx indeces and pkt counter | ||
824 | gp->tx_next_in = gp->tx_next_out = 0; | ||
825 | gp->tx_count = 0; | ||
826 | |||
827 | } | ||
828 | |||
829 | static void | ||
830 | reset_rx(struct net_device *dev) | ||
831 | { | ||
832 | struct gt96100_private *gp = netdev_priv(dev); | ||
833 | int i; | ||
834 | |||
835 | abort(dev, sdcmrAR); | ||
836 | |||
837 | for (i=0; i<RX_RING_SIZE; i++) { | ||
838 | gp->rx_ring[i].next = | ||
839 | cpu_to_dma32(gp->rx_ring_dma + | ||
840 | sizeof(gt96100_rd_t) * (i+1)); | ||
841 | gp->rx_ring[i].buff_ptr = | ||
842 | cpu_to_dma32(gp->rx_buff_dma + i*PKT_BUF_SZ); | ||
843 | gp->rx_ring[i].buff_sz = cpu_to_dma16(PKT_BUF_SZ); | ||
844 | // Give ownership to device, set first and last, enable intr | ||
845 | gp->rx_ring[i].cmdstat = | ||
846 | cpu_to_dma32((u32)(rxFirst | rxLast | rxOwn | rxEI)); | ||
847 | dump_rx_desc(4, dev, i); | ||
848 | } | ||
849 | /* Wrap the ring. */ | ||
850 | gp->rx_ring[i-1].next = cpu_to_dma32(gp->rx_ring_dma); | ||
851 | |||
852 | // Setup only the lowest priority RxFDP and RxCDP regs | ||
853 | for (i=0; i<4; i++) { | ||
854 | if (i == 0) { | ||
855 | GT96100ETH_WRITE(gp, GT96100_ETH_1ST_RX_DESC_PTR0, | ||
856 | gp->rx_ring_dma); | ||
857 | GT96100ETH_WRITE(gp, GT96100_ETH_CURR_RX_DESC_PTR0, | ||
858 | gp->rx_ring_dma); | ||
859 | } else { | ||
860 | GT96100ETH_WRITE(gp, | ||
861 | GT96100_ETH_1ST_RX_DESC_PTR0 + i*4, | ||
862 | 0); | ||
863 | GT96100ETH_WRITE(gp, | ||
864 | GT96100_ETH_CURR_RX_DESC_PTR0 + i*4, | ||
865 | 0); | ||
866 | } | ||
867 | } | ||
868 | |||
869 | // init Rx NextOut index | ||
870 | gp->rx_next_out = 0; | ||
871 | } | ||
872 | |||
873 | |||
874 | // Returns 1 if the Tx counter and indeces don't gel | ||
875 | static int | ||
876 | gt96100_check_tx_consistent(struct gt96100_private *gp) | ||
877 | { | ||
878 | int diff = gp->tx_next_in - gp->tx_next_out; | ||
879 | |||
880 | diff = diff<0 ? TX_RING_SIZE + diff : diff; | ||
881 | diff = gp->tx_count == TX_RING_SIZE ? diff + TX_RING_SIZE : diff; | ||
882 | |||
883 | return (diff != gp->tx_count); | ||
884 | } | ||
885 | |||
886 | static int | ||
887 | gt96100_init(struct net_device *dev) | ||
888 | { | ||
889 | struct gt96100_private *gp = netdev_priv(dev); | ||
890 | u32 tmp; | ||
891 | u16 mii_reg; | ||
892 | |||
893 | dbg(3, "%s: dev=%p\n", __FUNCTION__, dev); | ||
894 | dbg(3, "%s: scs10_lo=%4x, scs10_hi=%4x\n", __FUNCTION__, | ||
895 | GT96100_READ(0x8), GT96100_READ(0x10)); | ||
896 | dbg(3, "%s: scs32_lo=%4x, scs32_hi=%4x\n", __FUNCTION__, | ||
897 | GT96100_READ(0x18), GT96100_READ(0x20)); | ||
898 | |||
899 | // Stop and disable Port | ||
900 | hard_stop(dev); | ||
901 | |||
902 | // Setup CIU Arbiter | ||
903 | tmp = GT96100_READ(GT96100_CIU_ARBITER_CONFIG); | ||
904 | tmp |= (0x0c << (gp->port_num*2)); // set Ether DMA req priority to hi | ||
905 | #ifndef DESC_BE | ||
906 | tmp &= ~(1<<31); // set desc endianess to little | ||
907 | #else | ||
908 | tmp |= (1<<31); | ||
909 | #endif | ||
910 | GT96100_WRITE(GT96100_CIU_ARBITER_CONFIG, tmp); | ||
911 | dbg(3, "%s: CIU Config=%x/%x\n", __FUNCTION__, | ||
912 | tmp, GT96100_READ(GT96100_CIU_ARBITER_CONFIG)); | ||
913 | |||
914 | // Set routing. | ||
915 | tmp = GT96100_READ(GT96100_ROUTE_MAIN) & (0x3f << 18); | ||
916 | tmp |= (0x07 << (18 + gp->port_num*3)); | ||
917 | GT96100_WRITE(GT96100_ROUTE_MAIN, tmp); | ||
918 | |||
919 | /* set MII as peripheral func */ | ||
920 | tmp = GT96100_READ(GT96100_GPP_CONFIG2); | ||
921 | tmp |= 0x7fff << (gp->port_num*16); | ||
922 | GT96100_WRITE(GT96100_GPP_CONFIG2, tmp); | ||
923 | |||
924 | /* Set up MII port pin directions */ | ||
925 | tmp = GT96100_READ(GT96100_GPP_IO2); | ||
926 | tmp |= 0x003d << (gp->port_num*16); | ||
927 | GT96100_WRITE(GT96100_GPP_IO2, tmp); | ||
928 | |||
929 | // Set-up hash table | ||
930 | memset(gp->hash_table, 0, RX_HASH_TABLE_SIZE); // clear it | ||
931 | gp->hash_mode = 0; | ||
932 | // Add a single entry to hash table - our ethernet address | ||
933 | gt96100_add_hash_entry(dev, dev->dev_addr); | ||
934 | // Set-up DMA ptr to hash table | ||
935 | GT96100ETH_WRITE(gp, GT96100_ETH_HASH_TBL_PTR, gp->hash_table_dma); | ||
936 | dbg(3, "%s: Hash Tbl Ptr=%x\n", __FUNCTION__, | ||
937 | GT96100ETH_READ(gp, GT96100_ETH_HASH_TBL_PTR)); | ||
938 | |||
939 | // Setup Tx | ||
940 | reset_tx(dev); | ||
941 | |||
942 | dbg(3, "%s: Curr Tx Desc Ptr0=%x\n", __FUNCTION__, | ||
943 | GT96100ETH_READ(gp, GT96100_ETH_CURR_TX_DESC_PTR0)); | ||
944 | |||
945 | // Setup Rx | ||
946 | reset_rx(dev); | ||
947 | |||
948 | dbg(3, "%s: 1st/Curr Rx Desc Ptr0=%x/%x\n", __FUNCTION__, | ||
949 | GT96100ETH_READ(gp, GT96100_ETH_1ST_RX_DESC_PTR0), | ||
950 | GT96100ETH_READ(gp, GT96100_ETH_CURR_RX_DESC_PTR0)); | ||
951 | |||
952 | // eth port config register | ||
953 | GT96100ETH_WRITE(gp, GT96100_ETH_PORT_CONFIG_EXT, | ||
954 | pcxrFCTL | pcxrFCTLen | pcxrFLP | pcxrDPLXen); | ||
955 | |||
956 | mii_reg = read_MII(gp->phy_addr, 0x11); /* int enable register */ | ||
957 | mii_reg |= 2; /* enable mii interrupt */ | ||
958 | write_MII(gp->phy_addr, 0x11, mii_reg); | ||
959 | |||
960 | dbg(3, "%s: PhyAD=%x\n", __FUNCTION__, | ||
961 | GT96100_READ(GT96100_ETH_PHY_ADDR_REG)); | ||
962 | |||
963 | // setup DMA | ||
964 | |||
965 | // We want the Rx/Tx DMA to write/read data to/from memory in | ||
966 | // Big Endian mode. Also set DMA Burst Size to 8 64Bit words. | ||
967 | #ifdef DESC_DATA_BE | ||
968 | GT96100ETH_WRITE(gp, GT96100_ETH_SDMA_CONFIG, | ||
969 | (0xf<<sdcrRCBit) | sdcrRIFB | (3<<sdcrBSZBit)); | ||
970 | #else | ||
971 | GT96100ETH_WRITE(gp, GT96100_ETH_SDMA_CONFIG, | ||
972 | sdcrBLMR | sdcrBLMT | | ||
973 | (0xf<<sdcrRCBit) | sdcrRIFB | (3<<sdcrBSZBit)); | ||
974 | #endif | ||
975 | dbg(3, "%s: SDMA Config=%x\n", __FUNCTION__, | ||
976 | GT96100ETH_READ(gp, GT96100_ETH_SDMA_CONFIG)); | ||
977 | |||
978 | // start Rx DMA | ||
979 | GT96100ETH_WRITE(gp, GT96100_ETH_SDMA_COMM, sdcmrERD); | ||
980 | dbg(3, "%s: SDMA Comm=%x\n", __FUNCTION__, | ||
981 | GT96100ETH_READ(gp, GT96100_ETH_SDMA_COMM)); | ||
982 | |||
983 | // enable this port (set hash size to 1/2K) | ||
984 | GT96100ETH_WRITE(gp, GT96100_ETH_PORT_CONFIG, pcrEN | pcrHS); | ||
985 | dbg(3, "%s: Port Config=%x\n", __FUNCTION__, | ||
986 | GT96100ETH_READ(gp, GT96100_ETH_PORT_CONFIG)); | ||
987 | |||
988 | /* | ||
989 | * Disable all Type-of-Service queueing. All Rx packets will be | ||
990 | * treated normally and will be sent to the lowest priority | ||
991 | * queue. | ||
992 | * | ||
993 | * Disable flow-control for now. FIXME: support flow control? | ||
994 | */ | ||
995 | |||
996 | // clear all the MIB ctr regs | ||
997 | GT96100ETH_WRITE(gp, GT96100_ETH_PORT_CONFIG_EXT, | ||
998 | pcxrFCTL | pcxrFCTLen | pcxrFLP | | ||
999 | pcxrPRIOrxOverride); | ||
1000 | read_mib_counters(gp); | ||
1001 | GT96100ETH_WRITE(gp, GT96100_ETH_PORT_CONFIG_EXT, | ||
1002 | pcxrFCTL | pcxrFCTLen | pcxrFLP | | ||
1003 | pcxrPRIOrxOverride | pcxrMIBclrMode); | ||
1004 | |||
1005 | dbg(3, "%s: Port Config Ext=%x\n", __FUNCTION__, | ||
1006 | GT96100ETH_READ(gp, GT96100_ETH_PORT_CONFIG_EXT)); | ||
1007 | |||
1008 | netif_start_queue(dev); | ||
1009 | |||
1010 | dump_MII(4, dev); | ||
1011 | |||
1012 | // enable interrupts | ||
1013 | enable_ether_irq(dev); | ||
1014 | |||
1015 | // we should now be receiving frames | ||
1016 | return 0; | ||
1017 | } | ||
1018 | |||
1019 | |||
1020 | static int | ||
1021 | gt96100_open(struct net_device *dev) | ||
1022 | { | ||
1023 | int retval; | ||
1024 | |||
1025 | dbg(2, "%s: dev=%p\n", __FUNCTION__, dev); | ||
1026 | |||
1027 | // Initialize and startup the GT-96100 ethernet port | ||
1028 | if ((retval = gt96100_init(dev))) { | ||
1029 | err("error in gt96100_init\n"); | ||
1030 | free_irq(dev->irq, dev); | ||
1031 | return retval; | ||
1032 | } | ||
1033 | |||
1034 | if ((retval = request_irq(dev->irq, >96100_interrupt, | ||
1035 | SA_SHIRQ, dev->name, dev))) { | ||
1036 | err("unable to get IRQ %d\n", dev->irq); | ||
1037 | return retval; | ||
1038 | } | ||
1039 | |||
1040 | dbg(2, "%s: Initialization done.\n", __FUNCTION__); | ||
1041 | |||
1042 | return 0; | ||
1043 | } | ||
1044 | |||
1045 | static int | ||
1046 | gt96100_close(struct net_device *dev) | ||
1047 | { | ||
1048 | dbg(3, "%s: dev=%p\n", __FUNCTION__, dev); | ||
1049 | |||
1050 | // stop the device | ||
1051 | if (netif_device_present(dev)) { | ||
1052 | netif_stop_queue(dev); | ||
1053 | hard_stop(dev); | ||
1054 | } | ||
1055 | |||
1056 | free_irq(dev->irq, dev); | ||
1057 | |||
1058 | return 0; | ||
1059 | } | ||
1060 | |||
1061 | |||
1062 | static int | ||
1063 | gt96100_tx(struct sk_buff *skb, struct net_device *dev) | ||
1064 | { | ||
1065 | struct gt96100_private *gp = netdev_priv(dev); | ||
1066 | unsigned long flags; | ||
1067 | int nextIn; | ||
1068 | |||
1069 | spin_lock_irqsave(&gp->lock, flags); | ||
1070 | |||
1071 | nextIn = gp->tx_next_in; | ||
1072 | |||
1073 | dbg(3, "%s: nextIn=%d\n", __FUNCTION__, nextIn); | ||
1074 | |||
1075 | if (gp->tx_count >= TX_RING_SIZE) { | ||
1076 | warn("Tx Ring full, pkt dropped.\n"); | ||
1077 | gp->stats.tx_dropped++; | ||
1078 | spin_unlock_irqrestore(&gp->lock, flags); | ||
1079 | return 1; | ||
1080 | } | ||
1081 | |||
1082 | if (!(gp->last_psr & psrLink)) { | ||
1083 | err("%s: Link down, pkt dropped.\n", __FUNCTION__); | ||
1084 | gp->stats.tx_dropped++; | ||
1085 | spin_unlock_irqrestore(&gp->lock, flags); | ||
1086 | return 1; | ||
1087 | } | ||
1088 | |||
1089 | if (dma32_to_cpu(gp->tx_ring[nextIn].cmdstat) & txOwn) { | ||
1090 | err("%s: device owns descriptor, pkt dropped.\n", __FUNCTION__); | ||
1091 | gp->stats.tx_dropped++; | ||
1092 | // stop the queue, so Tx timeout can fix it | ||
1093 | netif_stop_queue(dev); | ||
1094 | spin_unlock_irqrestore(&gp->lock, flags); | ||
1095 | return 1; | ||
1096 | } | ||
1097 | |||
1098 | // Prepare the Descriptor at tx_next_in | ||
1099 | gp->tx_skbuff[nextIn] = skb; | ||
1100 | gp->tx_ring[nextIn].byte_cnt = cpu_to_dma16(skb->len); | ||
1101 | gp->tx_ring[nextIn].buff_ptr = cpu_to_dma32(virt_to_phys(skb->data)); | ||
1102 | // make sure packet gets written back to memory | ||
1103 | dma_cache_wback_inv((unsigned long)(skb->data), skb->len); | ||
1104 | // Give ownership to device, set first and last desc, enable interrupt | ||
1105 | // Setting of ownership bit must be *last*! | ||
1106 | gp->tx_ring[nextIn].cmdstat = | ||
1107 | cpu_to_dma32((u32)(txOwn | txGenCRC | txEI | | ||
1108 | txPad | txFirst | txLast)); | ||
1109 | |||
1110 | dump_tx_desc(4, dev, nextIn); | ||
1111 | dump_skb(4, dev, skb); | ||
1112 | |||
1113 | // increment tx_next_in with wrap | ||
1114 | gp->tx_next_in = (nextIn + 1) % TX_RING_SIZE; | ||
1115 | // If DMA is stopped, restart | ||
1116 | if (!(GT96100ETH_READ(gp, GT96100_ETH_PORT_STATUS) & psrTxLow)) | ||
1117 | GT96100ETH_WRITE(gp, GT96100_ETH_SDMA_COMM, | ||
1118 | sdcmrERD | sdcmrTXDL); | ||
1119 | |||
1120 | // increment count and stop queue if full | ||
1121 | if (++gp->tx_count == TX_RING_SIZE) { | ||
1122 | gp->tx_full = 1; | ||
1123 | netif_stop_queue(dev); | ||
1124 | dbg(2, "Tx Ring now full, queue stopped.\n"); | ||
1125 | } | ||
1126 | |||
1127 | dev->trans_start = jiffies; | ||
1128 | spin_unlock_irqrestore(&gp->lock, flags); | ||
1129 | |||
1130 | return 0; | ||
1131 | } | ||
1132 | |||
1133 | |||
1134 | static int | ||
1135 | gt96100_rx(struct net_device *dev, u32 status) | ||
1136 | { | ||
1137 | struct gt96100_private *gp = netdev_priv(dev); | ||
1138 | struct sk_buff *skb; | ||
1139 | int pkt_len, nextOut, cdp; | ||
1140 | gt96100_rd_t *rd; | ||
1141 | u32 cmdstat; | ||
1142 | |||
1143 | dbg(3, "%s: dev=%p, status=%x\n", __FUNCTION__, dev, status); | ||
1144 | |||
1145 | cdp = (GT96100ETH_READ(gp, GT96100_ETH_1ST_RX_DESC_PTR0) | ||
1146 | - gp->rx_ring_dma) / sizeof(gt96100_rd_t); | ||
1147 | |||
1148 | // Continue until we reach 1st descriptor pointer | ||
1149 | for (nextOut = gp->rx_next_out; nextOut != cdp; | ||
1150 | nextOut = (nextOut + 1) % RX_RING_SIZE) { | ||
1151 | |||
1152 | if (--gp->intr_work_done == 0) | ||
1153 | break; | ||
1154 | |||
1155 | rd = &gp->rx_ring[nextOut]; | ||
1156 | cmdstat = dma32_to_cpu(rd->cmdstat); | ||
1157 | |||
1158 | dbg(4, "%s: Rx desc cmdstat=%x, nextOut=%d\n", __FUNCTION__, | ||
1159 | cmdstat, nextOut); | ||
1160 | |||
1161 | if (cmdstat & (u32)rxOwn) { | ||
1162 | //err("%s: device owns descriptor!\n", __FUNCTION__); | ||
1163 | // DMA is not finished updating descriptor??? | ||
1164 | // Leave and come back later to pick-up where | ||
1165 | // we left off. | ||
1166 | break; | ||
1167 | } | ||
1168 | |||
1169 | // Drop this received pkt if there were any errors | ||
1170 | if (((cmdstat & (u32)(rxErrorSummary)) && | ||
1171 | (cmdstat & (u32)(rxFirst))) || (status & icrRxError)) { | ||
1172 | // update the detailed rx error counters that | ||
1173 | // are not covered by the MIB counters. | ||
1174 | if (cmdstat & (u32)rxOverrun) | ||
1175 | gp->stats.rx_fifo_errors++; | ||
1176 | cmdstat |= (u32)rxOwn; | ||
1177 | rd->cmdstat = cpu_to_dma32(cmdstat); | ||
1178 | continue; | ||
1179 | } | ||
1180 | |||
1181 | /* | ||
1182 | * Must be first and last (ie only) descriptor of packet. We | ||
1183 | * ignore (drop) any packets that do not fit in one descriptor. | ||
1184 | * Every descriptor's receive buffer is large enough to hold | ||
1185 | * the maximum 802.3 frame size, so a multi-descriptor packet | ||
1186 | * indicates an error. Most if not all corrupted packets will | ||
1187 | * have already been dropped by the above check for the | ||
1188 | * rxErrorSummary status bit. | ||
1189 | */ | ||
1190 | if (!(cmdstat & (u32)rxFirst) || !(cmdstat & (u32)rxLast)) { | ||
1191 | if (cmdstat & (u32)rxFirst) { | ||
1192 | /* | ||
1193 | * This is the first descriptor of a | ||
1194 | * multi-descriptor packet. It isn't corrupted | ||
1195 | * because the above check for rxErrorSummary | ||
1196 | * would have dropped it already, so what's | ||
1197 | * the deal with this packet? Good question, | ||
1198 | * let's dump it out. | ||
1199 | */ | ||
1200 | err("%s: desc not first and last!\n", __FUNCTION__); | ||
1201 | dump_rx_desc(0, dev, nextOut); | ||
1202 | } | ||
1203 | cmdstat |= (u32)rxOwn; | ||
1204 | rd->cmdstat = cpu_to_dma32(cmdstat); | ||
1205 | // continue to drop every descriptor of this packet | ||
1206 | continue; | ||
1207 | } | ||
1208 | |||
1209 | pkt_len = dma16_to_cpu(rd->byte_cnt); | ||
1210 | |||
1211 | /* Create new skb. */ | ||
1212 | skb = dev_alloc_skb(pkt_len+2); | ||
1213 | if (skb == NULL) { | ||
1214 | err("%s: Memory squeeze, dropping packet.\n", __FUNCTION__); | ||
1215 | gp->stats.rx_dropped++; | ||
1216 | cmdstat |= (u32)rxOwn; | ||
1217 | rd->cmdstat = cpu_to_dma32(cmdstat); | ||
1218 | continue; | ||
1219 | } | ||
1220 | skb->dev = dev; | ||
1221 | skb_reserve(skb, 2); /* 16 byte IP header align */ | ||
1222 | memcpy(skb_put(skb, pkt_len), | ||
1223 | &gp->rx_buff[nextOut*PKT_BUF_SZ], pkt_len); | ||
1224 | skb->protocol = eth_type_trans(skb, dev); | ||
1225 | dump_skb(4, dev, skb); | ||
1226 | |||
1227 | netif_rx(skb); /* pass the packet to upper layers */ | ||
1228 | dev->last_rx = jiffies; | ||
1229 | |||
1230 | // now we can release ownership of this desc back to device | ||
1231 | cmdstat |= (u32)rxOwn; | ||
1232 | rd->cmdstat = cpu_to_dma32(cmdstat); | ||
1233 | } | ||
1234 | |||
1235 | if (nextOut == gp->rx_next_out) | ||
1236 | dbg(3, "%s: RxCDP did not increment?\n", __FUNCTION__); | ||
1237 | |||
1238 | gp->rx_next_out = nextOut; | ||
1239 | return 0; | ||
1240 | } | ||
1241 | |||
1242 | |||
1243 | static void | ||
1244 | gt96100_tx_complete(struct net_device *dev, u32 status) | ||
1245 | { | ||
1246 | struct gt96100_private *gp = netdev_priv(dev); | ||
1247 | int nextOut, cdp; | ||
1248 | gt96100_td_t *td; | ||
1249 | u32 cmdstat; | ||
1250 | |||
1251 | cdp = (GT96100ETH_READ(gp, GT96100_ETH_CURR_TX_DESC_PTR0) | ||
1252 | - gp->tx_ring_dma) / sizeof(gt96100_td_t); | ||
1253 | |||
1254 | // Continue until we reach the current descriptor pointer | ||
1255 | for (nextOut = gp->tx_next_out; nextOut != cdp; | ||
1256 | nextOut = (nextOut + 1) % TX_RING_SIZE) { | ||
1257 | |||
1258 | if (--gp->intr_work_done == 0) | ||
1259 | break; | ||
1260 | |||
1261 | td = &gp->tx_ring[nextOut]; | ||
1262 | cmdstat = dma32_to_cpu(td->cmdstat); | ||
1263 | |||
1264 | dbg(3, "%s: Tx desc cmdstat=%x, nextOut=%d\n", __FUNCTION__, | ||
1265 | cmdstat, nextOut); | ||
1266 | |||
1267 | if (cmdstat & (u32)txOwn) { | ||
1268 | /* | ||
1269 | * DMA is not finished writing descriptor??? | ||
1270 | * Leave and come back later to pick-up where | ||
1271 | * we left off. | ||
1272 | */ | ||
1273 | break; | ||
1274 | } | ||
1275 | |||
1276 | // increment Tx error stats | ||
1277 | if (cmdstat & (u32)txErrorSummary) { | ||
1278 | dbg(2, "%s: Tx error, cmdstat = %x\n", __FUNCTION__, | ||
1279 | cmdstat); | ||
1280 | gp->stats.tx_errors++; | ||
1281 | if (cmdstat & (u32)txReTxLimit) | ||
1282 | gp->stats.tx_aborted_errors++; | ||
1283 | if (cmdstat & (u32)txUnderrun) | ||
1284 | gp->stats.tx_fifo_errors++; | ||
1285 | if (cmdstat & (u32)txLateCollision) | ||
1286 | gp->stats.tx_window_errors++; | ||
1287 | } | ||
1288 | |||
1289 | if (cmdstat & (u32)txCollision) | ||
1290 | gp->stats.collisions += | ||
1291 | (u32)((cmdstat & txReTxCntMask) >> | ||
1292 | txReTxCntBit); | ||
1293 | |||
1294 | // Wake the queue if the ring was full | ||
1295 | if (gp->tx_full) { | ||
1296 | gp->tx_full = 0; | ||
1297 | if (gp->last_psr & psrLink) { | ||
1298 | netif_wake_queue(dev); | ||
1299 | dbg(2, "%s: Tx Ring was full, queue waked\n", | ||
1300 | __FUNCTION__); | ||
1301 | } | ||
1302 | } | ||
1303 | |||
1304 | // decrement tx ring buffer count | ||
1305 | if (gp->tx_count) gp->tx_count--; | ||
1306 | |||
1307 | // free the skb | ||
1308 | if (gp->tx_skbuff[nextOut]) { | ||
1309 | dbg(3, "%s: good Tx, skb=%p\n", __FUNCTION__, | ||
1310 | gp->tx_skbuff[nextOut]); | ||
1311 | dev_kfree_skb_irq(gp->tx_skbuff[nextOut]); | ||
1312 | gp->tx_skbuff[nextOut] = NULL; | ||
1313 | } else { | ||
1314 | err("%s: no skb!\n", __FUNCTION__); | ||
1315 | } | ||
1316 | } | ||
1317 | |||
1318 | gp->tx_next_out = nextOut; | ||
1319 | |||
1320 | if (gt96100_check_tx_consistent(gp)) { | ||
1321 | err("%s: Tx queue inconsistent!\n", __FUNCTION__); | ||
1322 | } | ||
1323 | |||
1324 | if ((status & icrTxEndLow) && gp->tx_count != 0) { | ||
1325 | // we must restart the DMA | ||
1326 | dbg(3, "%s: Restarting Tx DMA\n", __FUNCTION__); | ||
1327 | GT96100ETH_WRITE(gp, GT96100_ETH_SDMA_COMM, | ||
1328 | sdcmrERD | sdcmrTXDL); | ||
1329 | } | ||
1330 | } | ||
1331 | |||
1332 | |||
1333 | static irqreturn_t | ||
1334 | gt96100_interrupt(int irq, void *dev_id, struct pt_regs *regs) | ||
1335 | { | ||
1336 | struct net_device *dev = (struct net_device *)dev_id; | ||
1337 | struct gt96100_private *gp = netdev_priv(dev); | ||
1338 | u32 status; | ||
1339 | int handled = 0; | ||
1340 | |||
1341 | if (dev == NULL) { | ||
1342 | err("%s: null dev ptr\n", __FUNCTION__); | ||
1343 | return IRQ_NONE; | ||
1344 | } | ||
1345 | |||
1346 | dbg(3, "%s: entry, icr=%x\n", __FUNCTION__, | ||
1347 | GT96100ETH_READ(gp, GT96100_ETH_INT_CAUSE)); | ||
1348 | |||
1349 | spin_lock(&gp->lock); | ||
1350 | |||
1351 | gp->intr_work_done = max_interrupt_work; | ||
1352 | |||
1353 | while (gp->intr_work_done > 0) { | ||
1354 | |||
1355 | status = GT96100ETH_READ(gp, GT96100_ETH_INT_CAUSE); | ||
1356 | // ACK interrupts | ||
1357 | GT96100ETH_WRITE(gp, GT96100_ETH_INT_CAUSE, ~status); | ||
1358 | |||
1359 | if ((status & icrEtherIntSum) == 0 && | ||
1360 | !(status & (icrTxBufferLow|icrTxBufferHigh|icrRxBuffer))) | ||
1361 | break; | ||
1362 | |||
1363 | handled = 1; | ||
1364 | |||
1365 | if (status & icrMIIPhySTC) { | ||
1366 | u32 psr = GT96100ETH_READ(gp, GT96100_ETH_PORT_STATUS); | ||
1367 | if (gp->last_psr != psr) { | ||
1368 | dbg(0, "port status:\n"); | ||
1369 | dbg(0, " %s MBit/s, %s-duplex, " | ||
1370 | "flow-control %s, link is %s,\n", | ||
1371 | psr & psrSpeed ? "100":"10", | ||
1372 | psr & psrDuplex ? "full":"half", | ||
1373 | psr & psrFctl ? "disabled":"enabled", | ||
1374 | psr & psrLink ? "up":"down"); | ||
1375 | dbg(0, " TxLowQ is %s, TxHighQ is %s, " | ||
1376 | "Transmitter is %s\n", | ||
1377 | psr & psrTxLow ? "running":"stopped", | ||
1378 | psr & psrTxHigh ? "running":"stopped", | ||
1379 | psr & psrTxInProg ? "on":"off"); | ||
1380 | |||
1381 | if ((psr & psrLink) && !gp->tx_full && | ||
1382 | netif_queue_stopped(dev)) { | ||
1383 | dbg(0, "%s: Link up, waking queue.\n", | ||
1384 | __FUNCTION__); | ||
1385 | netif_wake_queue(dev); | ||
1386 | } else if (!(psr & psrLink) && | ||
1387 | !netif_queue_stopped(dev)) { | ||
1388 | dbg(0, "%s: Link down, stopping queue.\n", | ||
1389 | __FUNCTION__); | ||
1390 | netif_stop_queue(dev); | ||
1391 | } | ||
1392 | |||
1393 | gp->last_psr = psr; | ||
1394 | } | ||
1395 | |||
1396 | if (--gp->intr_work_done == 0) | ||
1397 | break; | ||
1398 | } | ||
1399 | |||
1400 | if (status & (icrTxBufferLow | icrTxEndLow)) | ||
1401 | gt96100_tx_complete(dev, status); | ||
1402 | |||
1403 | if (status & (icrRxBuffer | icrRxError)) { | ||
1404 | gt96100_rx(dev, status); | ||
1405 | } | ||
1406 | |||
1407 | // Now check TX errors (RX errors were handled in gt96100_rx) | ||
1408 | if (status & icrTxErrorLow) { | ||
1409 | err("%s: Tx resource error\n", __FUNCTION__); | ||
1410 | if (--gp->intr_work_done == 0) | ||
1411 | break; | ||
1412 | } | ||
1413 | |||
1414 | if (status & icrTxUdr) { | ||
1415 | err("%s: Tx underrun error\n", __FUNCTION__); | ||
1416 | if (--gp->intr_work_done == 0) | ||
1417 | break; | ||
1418 | } | ||
1419 | } | ||
1420 | |||
1421 | if (gp->intr_work_done == 0) { | ||
1422 | // ACK any remaining pending interrupts | ||
1423 | GT96100ETH_WRITE(gp, GT96100_ETH_INT_CAUSE, 0); | ||
1424 | dbg(3, "%s: hit max work\n", __FUNCTION__); | ||
1425 | } | ||
1426 | |||
1427 | dbg(3, "%s: exit, icr=%x\n", __FUNCTION__, | ||
1428 | GT96100ETH_READ(gp, GT96100_ETH_INT_CAUSE)); | ||
1429 | |||
1430 | spin_unlock(&gp->lock); | ||
1431 | return IRQ_RETVAL(handled); | ||
1432 | } | ||
1433 | |||
1434 | |||
1435 | static void | ||
1436 | gt96100_tx_timeout(struct net_device *dev) | ||
1437 | { | ||
1438 | struct gt96100_private *gp = netdev_priv(dev); | ||
1439 | unsigned long flags; | ||
1440 | |||
1441 | spin_lock_irqsave(&gp->lock, flags); | ||
1442 | |||
1443 | if (!(gp->last_psr & psrLink)) { | ||
1444 | err("tx_timeout: link down.\n"); | ||
1445 | spin_unlock_irqrestore(&gp->lock, flags); | ||
1446 | } else { | ||
1447 | if (gt96100_check_tx_consistent(gp)) | ||
1448 | err("tx_timeout: Tx ring error.\n"); | ||
1449 | |||
1450 | disable_ether_irq(dev); | ||
1451 | spin_unlock_irqrestore(&gp->lock, flags); | ||
1452 | reset_tx(dev); | ||
1453 | enable_ether_irq(dev); | ||
1454 | |||
1455 | netif_wake_queue(dev); | ||
1456 | } | ||
1457 | } | ||
1458 | |||
1459 | |||
1460 | static void | ||
1461 | gt96100_set_rx_mode(struct net_device *dev) | ||
1462 | { | ||
1463 | struct gt96100_private *gp = netdev_priv(dev); | ||
1464 | unsigned long flags; | ||
1465 | //struct dev_mc_list *mcptr; | ||
1466 | |||
1467 | dbg(3, "%s: dev=%p, flags=%x\n", __FUNCTION__, dev, dev->flags); | ||
1468 | |||
1469 | // stop the Receiver DMA | ||
1470 | abort(dev, sdcmrAR); | ||
1471 | |||
1472 | spin_lock_irqsave(&gp->lock, flags); | ||
1473 | |||
1474 | if (dev->flags & IFF_PROMISC) { | ||
1475 | GT96100ETH_WRITE(gp, GT96100_ETH_PORT_CONFIG, | ||
1476 | pcrEN | pcrHS | pcrPM); | ||
1477 | } | ||
1478 | |||
1479 | #if 0 | ||
1480 | /* | ||
1481 | FIXME: currently multicast doesn't work - need to get hash table | ||
1482 | working first. | ||
1483 | */ | ||
1484 | if (dev->mc_count) { | ||
1485 | // clear hash table | ||
1486 | memset(gp->hash_table, 0, RX_HASH_TABLE_SIZE); | ||
1487 | // Add our ethernet address | ||
1488 | gt96100_add_hash_entry(dev, dev->dev_addr); | ||
1489 | |||
1490 | for (mcptr = dev->mc_list; mcptr; mcptr = mcptr->next) { | ||
1491 | dump_hw_addr(2, dev, __FUNCTION__ ": addr=", | ||
1492 | mcptr->dmi_addr); | ||
1493 | gt96100_add_hash_entry(dev, mcptr->dmi_addr); | ||
1494 | } | ||
1495 | } | ||
1496 | #endif | ||
1497 | |||
1498 | // restart Rx DMA | ||
1499 | GT96100ETH_WRITE(gp, GT96100_ETH_SDMA_COMM, sdcmrERD); | ||
1500 | |||
1501 | spin_unlock_irqrestore(&gp->lock, flags); | ||
1502 | } | ||
1503 | |||
1504 | static struct net_device_stats * | ||
1505 | gt96100_get_stats(struct net_device *dev) | ||
1506 | { | ||
1507 | struct gt96100_private *gp = netdev_priv(dev); | ||
1508 | unsigned long flags; | ||
1509 | |||
1510 | dbg(3, "%s: dev=%p\n", __FUNCTION__, dev); | ||
1511 | |||
1512 | if (netif_device_present(dev)) { | ||
1513 | spin_lock_irqsave (&gp->lock, flags); | ||
1514 | update_stats(gp); | ||
1515 | spin_unlock_irqrestore (&gp->lock, flags); | ||
1516 | } | ||
1517 | |||
1518 | return &gp->stats; | ||
1519 | } | ||
1520 | |||
1521 | static void gt96100_cleanup_module(void) | ||
1522 | { | ||
1523 | int i; | ||
1524 | for (i=0; i<NUM_INTERFACES; i++) { | ||
1525 | struct gt96100_if_t *gtif = >96100_iflist[i]; | ||
1526 | if (gtif->dev != NULL) { | ||
1527 | struct gt96100_private *gp = (struct gt96100_private *) | ||
1528 | netdev_priv(gtif->dev); | ||
1529 | unregister_netdev(gtif->dev); | ||
1530 | dmafree(RX_HASH_TABLE_SIZE, gp->hash_table_dma); | ||
1531 | dmafree(PKT_BUF_SZ*RX_RING_SIZE, gp->rx_buff); | ||
1532 | dmafree(sizeof(gt96100_rd_t) * RX_RING_SIZE | ||
1533 | + sizeof(gt96100_td_t) * TX_RING_SIZE, | ||
1534 | gp->rx_ring); | ||
1535 | free_netdev(gtif->dev); | ||
1536 | release_region(gtif->iobase, gp->io_size); | ||
1537 | } | ||
1538 | } | ||
1539 | } | ||
1540 | |||
1541 | static int __init gt96100_setup(char *options) | ||
1542 | { | ||
1543 | char *this_opt; | ||
1544 | |||
1545 | if (!options || !*options) | ||
1546 | return 0; | ||
1547 | |||
1548 | while ((this_opt = strsep (&options, ",")) != NULL) { | ||
1549 | if (!*this_opt) | ||
1550 | continue; | ||
1551 | if (!strncmp(this_opt, "mac0:", 5)) { | ||
1552 | memcpy(mac0, this_opt+5, 17); | ||
1553 | mac0[17]= '\0'; | ||
1554 | } else if (!strncmp(this_opt, "mac1:", 5)) { | ||
1555 | memcpy(mac1, this_opt+5, 17); | ||
1556 | mac1[17]= '\0'; | ||
1557 | } | ||
1558 | } | ||
1559 | |||
1560 | return 1; | ||
1561 | } | ||
1562 | |||
1563 | __setup("gt96100eth=", gt96100_setup); | ||
1564 | |||
1565 | module_init(gt96100_init_module); | ||
1566 | module_exit(gt96100_cleanup_module); | ||
1567 | |||
1568 | MODULE_AUTHOR("Steve Longerbeam <stevel@mvista.com>"); | ||
1569 | MODULE_DESCRIPTION("GT96100 Ethernet driver"); | ||