ixgbe: update {P}FC thresholds to account for X540 and loopback

Revise high and low threshold marks wrt flow control to account
for the X540 devices and latency introduced by the loopback
switch.

Without this it was in theory possible to drop frames on a
supposedly lossless link with X540 or SR-IOV enabled.

Previously we used a magic number in a define to calculate the
threshold values. This made it difficult to sort out exactly
which latencies were or were not being accounted for. Here
I was overly explicit and tried to used #define names that would
be recognizable after reading the IEEE 802.1Qbb specification.

Signed-off-by: John Fastabend <john.r.fastabend@intel.com>
Tested-by: Ross Brattain <ross.b.brattain@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>

1 files changed, 3 insertions, 5 deletions

diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82599.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82599.c
index d64fb872978e..02f6724bf48e 100644
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82599.c
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82599.c
@@ -210,21 +210,19 @@ s32 ixgbe_dcb_config_tx_data_arbiter_82599(struct ixgbe_hw *hw,
  */
 s32 ixgbe_dcb_config_pfc_82599(struct ixgbe_hw *hw, u8 pfc_en)
 {
-        u32 i, reg, rx_pba_size;
+        u32 i, reg;
 
         /* Configure PFC Tx thresholds per TC */
         for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
                 int enabled = pfc_en & (1 << i);
-                rx_pba_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
-                rx_pba_size >>= IXGBE_RXPBSIZE_SHIFT;
 
-                reg = (rx_pba_size - hw->fc.low_water) << 10;
+                reg = hw->fc.low_water << 10;
 
                 if (enabled)
                         reg |= IXGBE_FCRTL_XONE;
                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), reg);
 
-                reg = (rx_pba_size - hw->fc.high_water) << 10;
+                reg = hw->fc.high_water[i] << 10;
                 if (enabled)
                         reg |= IXGBE_FCRTH_FCEN;
                 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), reg);