diff options
| author | Jiang Liu <jiang.liu@huawei.com> | 2012-08-20 15:51:20 -0400 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2012-08-23 12:11:14 -0400 |
| commit | c772b44e32ea8255e5d0ffaac0a7b76043b14565 (patch) | |
| tree | a4ca888bf061dd2a5a28389914841c1db0382767 /drivers/net/ethernet/chelsio | |
| parent | 9503e255763da2e6b5b0d0d9dfa104e1ca8d035a (diff) | |
cxgb3: Use PCI Express Capability accessors
Use PCI Express Capability access functions to simplify cxgb3 driver.
[bhelgaas: split cxgb3 and cxgb4 into separate patches]
Signed-off-by: Jiang Liu <jiang.liu@huawei.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Diffstat (limited to 'drivers/net/ethernet/chelsio')
| -rw-r--r-- | drivers/net/ethernet/chelsio/cxgb3/t3_hw.c | 22 |
1 files changed, 8 insertions, 14 deletions
diff --git a/drivers/net/ethernet/chelsio/cxgb3/t3_hw.c b/drivers/net/ethernet/chelsio/cxgb3/t3_hw.c index bff8a3cdd3df..aef45d3113ba 100644 --- a/drivers/net/ethernet/chelsio/cxgb3/t3_hw.c +++ b/drivers/net/ethernet/chelsio/cxgb3/t3_hw.c | |||
| @@ -3289,22 +3289,18 @@ static void config_pcie(struct adapter *adap) | |||
| 3289 | unsigned int log2_width, pldsize; | 3289 | unsigned int log2_width, pldsize; |
| 3290 | unsigned int fst_trn_rx, fst_trn_tx, acklat, rpllmt; | 3290 | unsigned int fst_trn_rx, fst_trn_tx, acklat, rpllmt; |
| 3291 | 3291 | ||
| 3292 | pci_read_config_word(adap->pdev, | 3292 | pcie_capability_read_word(adap->pdev, PCI_EXP_DEVCTL, &val); |
| 3293 | adap->pdev->pcie_cap + PCI_EXP_DEVCTL, | ||
| 3294 | &val); | ||
| 3295 | pldsize = (val & PCI_EXP_DEVCTL_PAYLOAD) >> 5; | 3293 | pldsize = (val & PCI_EXP_DEVCTL_PAYLOAD) >> 5; |
| 3296 | 3294 | ||
| 3297 | pci_read_config_word(adap->pdev, 0x2, &devid); | 3295 | pci_read_config_word(adap->pdev, 0x2, &devid); |
| 3298 | if (devid == 0x37) { | 3296 | if (devid == 0x37) { |
| 3299 | pci_write_config_word(adap->pdev, | 3297 | pcie_capability_write_word(adap->pdev, PCI_EXP_DEVCTL, |
| 3300 | adap->pdev->pcie_cap + PCI_EXP_DEVCTL, | 3298 | val & ~PCI_EXP_DEVCTL_READRQ & |
| 3301 | val & ~PCI_EXP_DEVCTL_READRQ & | 3299 | ~PCI_EXP_DEVCTL_PAYLOAD); |
| 3302 | ~PCI_EXP_DEVCTL_PAYLOAD); | ||
| 3303 | pldsize = 0; | 3300 | pldsize = 0; |
| 3304 | } | 3301 | } |
| 3305 | 3302 | ||
| 3306 | pci_read_config_word(adap->pdev, adap->pdev->pcie_cap + PCI_EXP_LNKCTL, | 3303 | pcie_capability_read_word(adap->pdev, PCI_EXP_LNKCTL, &val); |
| 3307 | &val); | ||
| 3308 | 3304 | ||
| 3309 | fst_trn_tx = G_NUMFSTTRNSEQ(t3_read_reg(adap, A_PCIE_PEX_CTRL0)); | 3305 | fst_trn_tx = G_NUMFSTTRNSEQ(t3_read_reg(adap, A_PCIE_PEX_CTRL0)); |
| 3310 | fst_trn_rx = adap->params.rev == 0 ? fst_trn_tx : | 3306 | fst_trn_rx = adap->params.rev == 0 ? fst_trn_tx : |
| @@ -3425,15 +3421,13 @@ out_err: | |||
| 3425 | static void get_pci_mode(struct adapter *adapter, struct pci_params *p) | 3421 | static void get_pci_mode(struct adapter *adapter, struct pci_params *p) |
| 3426 | { | 3422 | { |
| 3427 | static unsigned short speed_map[] = { 33, 66, 100, 133 }; | 3423 | static unsigned short speed_map[] = { 33, 66, 100, 133 }; |
| 3428 | u32 pci_mode, pcie_cap; | 3424 | u32 pci_mode; |
| 3429 | 3425 | ||
| 3430 | pcie_cap = pci_pcie_cap(adapter->pdev); | 3426 | if (pci_is_pcie(adapter->pdev)) { |
| 3431 | if (pcie_cap) { | ||
| 3432 | u16 val; | 3427 | u16 val; |
| 3433 | 3428 | ||
| 3434 | p->variant = PCI_VARIANT_PCIE; | 3429 | p->variant = PCI_VARIANT_PCIE; |
| 3435 | pci_read_config_word(adapter->pdev, pcie_cap + PCI_EXP_LNKSTA, | 3430 | pcie_capability_read_word(adapter->pdev, PCI_EXP_LNKSTA, &val); |
| 3436 | &val); | ||
| 3437 | p->width = (val >> 4) & 0x3f; | 3431 | p->width = (val >> 4) & 0x3f; |
| 3438 | return; | 3432 | return; |
| 3439 | } | 3433 | } |