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authorJeff Kirsher <jeffrey.t.kirsher@intel.com>2011-04-07 09:03:04 -0400
committerJeff Kirsher <jeffrey.t.kirsher@intel.com>2011-08-10 22:54:39 -0400
commitadfc5217e9db68d3f0cec8dd847c1a6d3ab549ee (patch)
tree4082ae79d2d4d40b39c9b5144b8171464b5f7eb2 /drivers/net/ethernet/broadcom/bnx2x/bnx2x_reg.h
parent644570b830266ff33ff5f3542b9c838f93a55ea6 (diff)
broadcom: Move the Broadcom drivers
Moves the drivers for Broadcom devices into drivers/net/ethernet/broadcom/ and the necessary Kconfig and Makefile changes. CC: Eilon Greenstein <eilong@broadcom.com> CC: Michael Chan <mchan@broadcom.com> CC: Matt Carlson <mcarlson@broadcom.com> CC: Gary Zambrano <zambrano@broadcom.com> CC: "Maciej W. Rozycki" <macro@linux-mips.org> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Diffstat (limited to 'drivers/net/ethernet/broadcom/bnx2x/bnx2x_reg.h')
-rw-r--r--drivers/net/ethernet/broadcom/bnx2x/bnx2x_reg.h7146
1 files changed, 7146 insertions, 0 deletions
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_reg.h b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_reg.h
new file mode 100644
index 000000000000..27b5ecb11830
--- /dev/null
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_reg.h
@@ -0,0 +1,7146 @@
1/* bnx2x_reg.h: Broadcom Everest network driver.
2 *
3 * Copyright (c) 2007-2011 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * The registers description starts with the register Access type followed
10 * by size in bits. For example [RW 32]. The access types are:
11 * R - Read only
12 * RC - Clear on read
13 * RW - Read/Write
14 * ST - Statistics register (clear on read)
15 * W - Write only
16 * WB - Wide bus register - the size is over 32 bits and it should be
17 * read/write in consecutive 32 bits accesses
18 * WR - Write Clear (write 1 to clear the bit)
19 *
20 */
21#ifndef BNX2X_REG_H
22#define BNX2X_REG_H
23
24#define ATC_ATC_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
25#define ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS (0x1<<2)
26#define ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU (0x1<<5)
27#define ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT (0x1<<3)
28#define ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR (0x1<<4)
29#define ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND (0x1<<1)
30/* [RW 1] Initiate the ATC array - reset all the valid bits */
31#define ATC_REG_ATC_INIT_ARRAY 0x1100b8
32/* [R 1] ATC initalization done */
33#define ATC_REG_ATC_INIT_DONE 0x1100bc
34/* [RC 6] Interrupt register #0 read clear */
35#define ATC_REG_ATC_INT_STS_CLR 0x1101c0
36/* [RW 5] Parity mask register #0 read/write */
37#define ATC_REG_ATC_PRTY_MASK 0x1101d8
38/* [RC 5] Parity register #0 read clear */
39#define ATC_REG_ATC_PRTY_STS_CLR 0x1101d0
40/* [RW 19] Interrupt mask register #0 read/write */
41#define BRB1_REG_BRB1_INT_MASK 0x60128
42/* [R 19] Interrupt register #0 read */
43#define BRB1_REG_BRB1_INT_STS 0x6011c
44/* [RW 4] Parity mask register #0 read/write */
45#define BRB1_REG_BRB1_PRTY_MASK 0x60138
46/* [R 4] Parity register #0 read */
47#define BRB1_REG_BRB1_PRTY_STS 0x6012c
48/* [RC 4] Parity register #0 read clear */
49#define BRB1_REG_BRB1_PRTY_STS_CLR 0x60130
50/* [RW 10] At address BRB1_IND_FREE_LIST_PRS_CRDT initialize free head. At
51 * address BRB1_IND_FREE_LIST_PRS_CRDT+1 initialize free tail. At address
52 * BRB1_IND_FREE_LIST_PRS_CRDT+2 initialize parser initial credit. Warning -
53 * following reset the first rbc access to this reg must be write; there can
54 * be no more rbc writes after the first one; there can be any number of rbc
55 * read following the first write; rbc access not following these rules will
56 * result in hang condition. */
57#define BRB1_REG_FREE_LIST_PRS_CRDT 0x60200
58/* [RW 10] The number of free blocks below which the full signal to class 0
59 * is asserted */
60#define BRB1_REG_FULL_0_XOFF_THRESHOLD_0 0x601d0
61#define BRB1_REG_FULL_0_XOFF_THRESHOLD_1 0x60230
62/* [RW 11] The number of free blocks above which the full signal to class 0
63 * is de-asserted */
64#define BRB1_REG_FULL_0_XON_THRESHOLD_0 0x601d4
65#define BRB1_REG_FULL_0_XON_THRESHOLD_1 0x60234
66/* [RW 11] The number of free blocks below which the full signal to class 1
67 * is asserted */
68#define BRB1_REG_FULL_1_XOFF_THRESHOLD_0 0x601d8
69#define BRB1_REG_FULL_1_XOFF_THRESHOLD_1 0x60238
70/* [RW 11] The number of free blocks above which the full signal to class 1
71 * is de-asserted */
72#define BRB1_REG_FULL_1_XON_THRESHOLD_0 0x601dc
73#define BRB1_REG_FULL_1_XON_THRESHOLD_1 0x6023c
74/* [RW 11] The number of free blocks below which the full signal to the LB
75 * port is asserted */
76#define BRB1_REG_FULL_LB_XOFF_THRESHOLD 0x601e0
77/* [RW 10] The number of free blocks above which the full signal to the LB
78 * port is de-asserted */
79#define BRB1_REG_FULL_LB_XON_THRESHOLD 0x601e4
80/* [RW 10] The number of free blocks above which the High_llfc signal to
81 interface #n is de-asserted. */
82#define BRB1_REG_HIGH_LLFC_HIGH_THRESHOLD_0 0x6014c
83/* [RW 10] The number of free blocks below which the High_llfc signal to
84 interface #n is asserted. */
85#define BRB1_REG_HIGH_LLFC_LOW_THRESHOLD_0 0x6013c
86/* [RW 11] The number of blocks guarantied for the LB port */
87#define BRB1_REG_LB_GUARANTIED 0x601ec
88/* [RW 11] The hysteresis on the guarantied buffer space for the Lb port
89 * before signaling XON. */
90#define BRB1_REG_LB_GUARANTIED_HYST 0x60264
91/* [RW 24] LL RAM data. */
92#define BRB1_REG_LL_RAM 0x61000
93/* [RW 10] The number of free blocks above which the Low_llfc signal to
94 interface #n is de-asserted. */
95#define BRB1_REG_LOW_LLFC_HIGH_THRESHOLD_0 0x6016c
96/* [RW 10] The number of free blocks below which the Low_llfc signal to
97 interface #n is asserted. */
98#define BRB1_REG_LOW_LLFC_LOW_THRESHOLD_0 0x6015c
99/* [RW 11] The number of blocks guarantied for class 0 in MAC 0. The
100 * register is applicable only when per_class_guaranty_mode is set. */
101#define BRB1_REG_MAC_0_CLASS_0_GUARANTIED 0x60244
102/* [RW 11] The hysteresis on the guarantied buffer space for class 0 in MAC
103 * 1 before signaling XON. The register is applicable only when
104 * per_class_guaranty_mode is set. */
105#define BRB1_REG_MAC_0_CLASS_0_GUARANTIED_HYST 0x60254
106/* [RW 11] The number of blocks guarantied for class 1 in MAC 0. The
107 * register is applicable only when per_class_guaranty_mode is set. */
108#define BRB1_REG_MAC_0_CLASS_1_GUARANTIED 0x60248
109/* [RW 11] The hysteresis on the guarantied buffer space for class 1in MAC 0
110 * before signaling XON. The register is applicable only when
111 * per_class_guaranty_mode is set. */
112#define BRB1_REG_MAC_0_CLASS_1_GUARANTIED_HYST 0x60258
113/* [RW 11] The number of blocks guarantied for class 0in MAC1.The register
114 * is applicable only when per_class_guaranty_mode is set. */
115#define BRB1_REG_MAC_1_CLASS_0_GUARANTIED 0x6024c
116/* [RW 11] The hysteresis on the guarantied buffer space for class 0 in MAC
117 * 1 before signaling XON. The register is applicable only when
118 * per_class_guaranty_mode is set. */
119#define BRB1_REG_MAC_1_CLASS_0_GUARANTIED_HYST 0x6025c
120/* [RW 11] The number of blocks guarantied for class 1 in MAC 1. The
121 * register is applicable only when per_class_guaranty_mode is set. */
122#define BRB1_REG_MAC_1_CLASS_1_GUARANTIED 0x60250
123/* [RW 11] The hysteresis on the guarantied buffer space for class 1 in MAC
124 * 1 before signaling XON. The register is applicable only when
125 * per_class_guaranty_mode is set. */
126#define BRB1_REG_MAC_1_CLASS_1_GUARANTIED_HYST 0x60260
127/* [RW 11] The number of blocks guarantied for the MAC port. The register is
128 * applicable only when per_class_guaranty_mode is reset. */
129#define BRB1_REG_MAC_GUARANTIED_0 0x601e8
130#define BRB1_REG_MAC_GUARANTIED_1 0x60240
131/* [R 24] The number of full blocks. */
132#define BRB1_REG_NUM_OF_FULL_BLOCKS 0x60090
133/* [ST 32] The number of cycles that the write_full signal towards MAC #0
134 was asserted. */
135#define BRB1_REG_NUM_OF_FULL_CYCLES_0 0x600c8
136#define BRB1_REG_NUM_OF_FULL_CYCLES_1 0x600cc
137#define BRB1_REG_NUM_OF_FULL_CYCLES_4 0x600d8
138/* [ST 32] The number of cycles that the pause signal towards MAC #0 was
139 asserted. */
140#define BRB1_REG_NUM_OF_PAUSE_CYCLES_0 0x600b8
141#define BRB1_REG_NUM_OF_PAUSE_CYCLES_1 0x600bc
142/* [RW 10] The number of free blocks below which the pause signal to class 0
143 * is asserted */
144#define BRB1_REG_PAUSE_0_XOFF_THRESHOLD_0 0x601c0
145#define BRB1_REG_PAUSE_0_XOFF_THRESHOLD_1 0x60220
146/* [RW 11] The number of free blocks above which the pause signal to class 0
147 * is de-asserted */
148#define BRB1_REG_PAUSE_0_XON_THRESHOLD_0 0x601c4
149#define BRB1_REG_PAUSE_0_XON_THRESHOLD_1 0x60224
150/* [RW 11] The number of free blocks below which the pause signal to class 1
151 * is asserted */
152#define BRB1_REG_PAUSE_1_XOFF_THRESHOLD_0 0x601c8
153#define BRB1_REG_PAUSE_1_XOFF_THRESHOLD_1 0x60228
154/* [RW 11] The number of free blocks above which the pause signal to class 1
155 * is de-asserted */
156#define BRB1_REG_PAUSE_1_XON_THRESHOLD_0 0x601cc
157#define BRB1_REG_PAUSE_1_XON_THRESHOLD_1 0x6022c
158/* [RW 10] Write client 0: De-assert pause threshold. Not Functional */
159#define BRB1_REG_PAUSE_HIGH_THRESHOLD_0 0x60078
160#define BRB1_REG_PAUSE_HIGH_THRESHOLD_1 0x6007c
161/* [RW 10] Write client 0: Assert pause threshold. */
162#define BRB1_REG_PAUSE_LOW_THRESHOLD_0 0x60068
163#define BRB1_REG_PAUSE_LOW_THRESHOLD_1 0x6006c
164/* [R 24] The number of full blocks occupied by port. */
165#define BRB1_REG_PORT_NUM_OCC_BLOCKS_0 0x60094
166/* [RW 1] Reset the design by software. */
167#define BRB1_REG_SOFT_RESET 0x600dc
168/* [R 5] Used to read the value of the XX protection CAM occupancy counter. */
169#define CCM_REG_CAM_OCCUP 0xd0188
170/* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
171 acknowledge output is deasserted; all other signals are treated as usual;
172 if 1 - normal activity. */
173#define CCM_REG_CCM_CFC_IFEN 0xd003c
174/* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
175 disregarded; valid is deasserted; all other signals are treated as usual;
176 if 1 - normal activity. */
177#define CCM_REG_CCM_CQM_IFEN 0xd000c
178/* [RW 1] If set the Q index; received from the QM is inserted to event ID.
179 Otherwise 0 is inserted. */
180#define CCM_REG_CCM_CQM_USE_Q 0xd00c0
181/* [RW 11] Interrupt mask register #0 read/write */
182#define CCM_REG_CCM_INT_MASK 0xd01e4
183/* [R 11] Interrupt register #0 read */
184#define CCM_REG_CCM_INT_STS 0xd01d8
185/* [RW 27] Parity mask register #0 read/write */
186#define CCM_REG_CCM_PRTY_MASK 0xd01f4
187/* [R 27] Parity register #0 read */
188#define CCM_REG_CCM_PRTY_STS 0xd01e8
189/* [RC 27] Parity register #0 read clear */
190#define CCM_REG_CCM_PRTY_STS_CLR 0xd01ec
191/* [RW 3] The size of AG context region 0 in REG-pairs. Designates the MS
192 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
193 Is used to determine the number of the AG context REG-pairs written back;
194 when the input message Reg1WbFlg isn't set. */
195#define CCM_REG_CCM_REG0_SZ 0xd00c4
196/* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
197 disregarded; valid is deasserted; all other signals are treated as usual;
198 if 1 - normal activity. */
199#define CCM_REG_CCM_STORM0_IFEN 0xd0004
200/* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
201 disregarded; valid is deasserted; all other signals are treated as usual;
202 if 1 - normal activity. */
203#define CCM_REG_CCM_STORM1_IFEN 0xd0008
204/* [RW 1] CDU AG read Interface enable. If 0 - the request input is
205 disregarded; valid output is deasserted; all other signals are treated as
206 usual; if 1 - normal activity. */
207#define CCM_REG_CDU_AG_RD_IFEN 0xd0030
208/* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
209 are disregarded; all other signals are treated as usual; if 1 - normal
210 activity. */
211#define CCM_REG_CDU_AG_WR_IFEN 0xd002c
212/* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
213 disregarded; valid output is deasserted; all other signals are treated as
214 usual; if 1 - normal activity. */
215#define CCM_REG_CDU_SM_RD_IFEN 0xd0038
216/* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
217 input is disregarded; all other signals are treated as usual; if 1 -
218 normal activity. */
219#define CCM_REG_CDU_SM_WR_IFEN 0xd0034
220/* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
221 the initial credit value; read returns the current value of the credit
222 counter. Must be initialized to 1 at start-up. */
223#define CCM_REG_CFC_INIT_CRD 0xd0204
224/* [RW 2] Auxiliary counter flag Q number 1. */
225#define CCM_REG_CNT_AUX1_Q 0xd00c8
226/* [RW 2] Auxiliary counter flag Q number 2. */
227#define CCM_REG_CNT_AUX2_Q 0xd00cc
228/* [RW 28] The CM header value for QM request (primary). */
229#define CCM_REG_CQM_CCM_HDR_P 0xd008c
230/* [RW 28] The CM header value for QM request (secondary). */
231#define CCM_REG_CQM_CCM_HDR_S 0xd0090
232/* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
233 acknowledge output is deasserted; all other signals are treated as usual;
234 if 1 - normal activity. */
235#define CCM_REG_CQM_CCM_IFEN 0xd0014
236/* [RW 6] QM output initial credit. Max credit available - 32. Write writes
237 the initial credit value; read returns the current value of the credit
238 counter. Must be initialized to 32 at start-up. */
239#define CCM_REG_CQM_INIT_CRD 0xd020c
240/* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
241 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
242 prioritised); 2 stands for weight 2; tc. */
243#define CCM_REG_CQM_P_WEIGHT 0xd00b8
244/* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0
245 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
246 prioritised); 2 stands for weight 2; tc. */
247#define CCM_REG_CQM_S_WEIGHT 0xd00bc
248/* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
249 acknowledge output is deasserted; all other signals are treated as usual;
250 if 1 - normal activity. */
251#define CCM_REG_CSDM_IFEN 0xd0018
252/* [RC 1] Set when the message length mismatch (relative to last indication)
253 at the SDM interface is detected. */
254#define CCM_REG_CSDM_LENGTH_MIS 0xd0170
255/* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for
256 weight 8 (the most prioritised); 1 stands for weight 1(least
257 prioritised); 2 stands for weight 2; tc. */
258#define CCM_REG_CSDM_WEIGHT 0xd00b4
259/* [RW 28] The CM header for QM formatting in case of an error in the QM
260 inputs. */
261#define CCM_REG_ERR_CCM_HDR 0xd0094
262/* [RW 8] The Event ID in case the input message ErrorFlg is set. */
263#define CCM_REG_ERR_EVNT_ID 0xd0098
264/* [RW 8] FIC0 output initial credit. Max credit available - 255. Write
265 writes the initial credit value; read returns the current value of the
266 credit counter. Must be initialized to 64 at start-up. */
267#define CCM_REG_FIC0_INIT_CRD 0xd0210
268/* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
269 writes the initial credit value; read returns the current value of the
270 credit counter. Must be initialized to 64 at start-up. */
271#define CCM_REG_FIC1_INIT_CRD 0xd0214
272/* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1
273 - strict priority defined by ~ccm_registers_gr_ag_pr.gr_ag_pr;
274 ~ccm_registers_gr_ld0_pr.gr_ld0_pr and
275 ~ccm_registers_gr_ld1_pr.gr_ld1_pr. Groups are according to channels and
276 outputs to STORM: aggregation; load FIC0; load FIC1 and store. */
277#define CCM_REG_GR_ARB_TYPE 0xd015c
278/* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
279 highest priority is 3. It is supposed; that the Store channel priority is
280 the compliment to 4 of the rest priorities - Aggregation channel; Load
281 (FIC0) channel and Load (FIC1). */
282#define CCM_REG_GR_LD0_PR 0xd0164
283/* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
284 highest priority is 3. It is supposed; that the Store channel priority is
285 the compliment to 4 of the rest priorities - Aggregation channel; Load
286 (FIC0) channel and Load (FIC1). */
287#define CCM_REG_GR_LD1_PR 0xd0168
288/* [RW 2] General flags index. */
289#define CCM_REG_INV_DONE_Q 0xd0108
290/* [RW 4] The number of double REG-pairs(128 bits); loaded from the STORM
291 context and sent to STORM; for a specific connection type. The double
292 REG-pairs are used in order to align to STORM context row size of 128
293 bits. The offset of these data in the STORM context is always 0. Index
294 _(0..15) stands for the connection type (one of 16). */
295#define CCM_REG_N_SM_CTX_LD_0 0xd004c
296#define CCM_REG_N_SM_CTX_LD_1 0xd0050
297#define CCM_REG_N_SM_CTX_LD_2 0xd0054
298#define CCM_REG_N_SM_CTX_LD_3 0xd0058
299#define CCM_REG_N_SM_CTX_LD_4 0xd005c
300/* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded;
301 acknowledge output is deasserted; all other signals are treated as usual;
302 if 1 - normal activity. */
303#define CCM_REG_PBF_IFEN 0xd0028
304/* [RC 1] Set when the message length mismatch (relative to last indication)
305 at the pbf interface is detected. */
306#define CCM_REG_PBF_LENGTH_MIS 0xd0180
307/* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for
308 weight 8 (the most prioritised); 1 stands for weight 1(least
309 prioritised); 2 stands for weight 2; tc. */
310#define CCM_REG_PBF_WEIGHT 0xd00ac
311#define CCM_REG_PHYS_QNUM1_0 0xd0134
312#define CCM_REG_PHYS_QNUM1_1 0xd0138
313#define CCM_REG_PHYS_QNUM2_0 0xd013c
314#define CCM_REG_PHYS_QNUM2_1 0xd0140
315#define CCM_REG_PHYS_QNUM3_0 0xd0144
316#define CCM_REG_PHYS_QNUM3_1 0xd0148
317#define CCM_REG_QOS_PHYS_QNUM0_0 0xd0114
318#define CCM_REG_QOS_PHYS_QNUM0_1 0xd0118
319#define CCM_REG_QOS_PHYS_QNUM1_0 0xd011c
320#define CCM_REG_QOS_PHYS_QNUM1_1 0xd0120
321#define CCM_REG_QOS_PHYS_QNUM2_0 0xd0124
322#define CCM_REG_QOS_PHYS_QNUM2_1 0xd0128
323#define CCM_REG_QOS_PHYS_QNUM3_0 0xd012c
324#define CCM_REG_QOS_PHYS_QNUM3_1 0xd0130
325/* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
326 disregarded; acknowledge output is deasserted; all other signals are
327 treated as usual; if 1 - normal activity. */
328#define CCM_REG_STORM_CCM_IFEN 0xd0010
329/* [RC 1] Set when the message length mismatch (relative to last indication)
330 at the STORM interface is detected. */
331#define CCM_REG_STORM_LENGTH_MIS 0xd016c
332/* [RW 3] The weight of the STORM input in the WRR (Weighted Round robin)
333 mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for
334 weight 1(least prioritised); 2 stands for weight 2 (more prioritised);
335 tc. */
336#define CCM_REG_STORM_WEIGHT 0xd009c
337/* [RW 1] Input tsem Interface enable. If 0 - the valid input is
338 disregarded; acknowledge output is deasserted; all other signals are
339 treated as usual; if 1 - normal activity. */
340#define CCM_REG_TSEM_IFEN 0xd001c
341/* [RC 1] Set when the message length mismatch (relative to last indication)
342 at the tsem interface is detected. */
343#define CCM_REG_TSEM_LENGTH_MIS 0xd0174
344/* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for
345 weight 8 (the most prioritised); 1 stands for weight 1(least
346 prioritised); 2 stands for weight 2; tc. */
347#define CCM_REG_TSEM_WEIGHT 0xd00a0
348/* [RW 1] Input usem Interface enable. If 0 - the valid input is
349 disregarded; acknowledge output is deasserted; all other signals are
350 treated as usual; if 1 - normal activity. */
351#define CCM_REG_USEM_IFEN 0xd0024
352/* [RC 1] Set when message length mismatch (relative to last indication) at
353 the usem interface is detected. */
354#define CCM_REG_USEM_LENGTH_MIS 0xd017c
355/* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for
356 weight 8 (the most prioritised); 1 stands for weight 1(least
357 prioritised); 2 stands for weight 2; tc. */
358#define CCM_REG_USEM_WEIGHT 0xd00a8
359/* [RW 1] Input xsem Interface enable. If 0 - the valid input is
360 disregarded; acknowledge output is deasserted; all other signals are
361 treated as usual; if 1 - normal activity. */
362#define CCM_REG_XSEM_IFEN 0xd0020
363/* [RC 1] Set when the message length mismatch (relative to last indication)
364 at the xsem interface is detected. */
365#define CCM_REG_XSEM_LENGTH_MIS 0xd0178
366/* [RW 3] The weight of the input xsem in the WRR mechanism. 0 stands for
367 weight 8 (the most prioritised); 1 stands for weight 1(least
368 prioritised); 2 stands for weight 2; tc. */
369#define CCM_REG_XSEM_WEIGHT 0xd00a4
370/* [RW 19] Indirect access to the descriptor table of the XX protection
371 mechanism. The fields are: [5:0] - message length; [12:6] - message
372 pointer; 18:13] - next pointer. */
373#define CCM_REG_XX_DESCR_TABLE 0xd0300
374#define CCM_REG_XX_DESCR_TABLE_SIZE 24
375/* [R 7] Used to read the value of XX protection Free counter. */
376#define CCM_REG_XX_FREE 0xd0184
377/* [RW 6] Initial value for the credit counter; responsible for fulfilling
378 of the Input Stage XX protection buffer by the XX protection pending
379 messages. Max credit available - 127. Write writes the initial credit
380 value; read returns the current value of the credit counter. Must be
381 initialized to maximum XX protected message size - 2 at start-up. */
382#define CCM_REG_XX_INIT_CRD 0xd0220
383/* [RW 7] The maximum number of pending messages; which may be stored in XX
384 protection. At read the ~ccm_registers_xx_free.xx_free counter is read.
385 At write comprises the start value of the ~ccm_registers_xx_free.xx_free
386 counter. */
387#define CCM_REG_XX_MSG_NUM 0xd0224
388/* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
389#define CCM_REG_XX_OVFL_EVNT_ID 0xd0044
390/* [RW 18] Indirect access to the XX table of the XX protection mechanism.
391 The fields are: [5:0] - tail pointer; 11:6] - Link List size; 17:12] -
392 header pointer. */
393#define CCM_REG_XX_TABLE 0xd0280
394#define CDU_REG_CDU_CHK_MASK0 0x101000
395#define CDU_REG_CDU_CHK_MASK1 0x101004
396#define CDU_REG_CDU_CONTROL0 0x101008
397#define CDU_REG_CDU_DEBUG 0x101010
398#define CDU_REG_CDU_GLOBAL_PARAMS 0x101020
399/* [RW 7] Interrupt mask register #0 read/write */
400#define CDU_REG_CDU_INT_MASK 0x10103c
401/* [R 7] Interrupt register #0 read */
402#define CDU_REG_CDU_INT_STS 0x101030
403/* [RW 5] Parity mask register #0 read/write */
404#define CDU_REG_CDU_PRTY_MASK 0x10104c
405/* [R 5] Parity register #0 read */
406#define CDU_REG_CDU_PRTY_STS 0x101040
407/* [RC 5] Parity register #0 read clear */
408#define CDU_REG_CDU_PRTY_STS_CLR 0x101044
409/* [RC 32] logging of error data in case of a CDU load error:
410 {expected_cid[15:0]; xpected_type[2:0]; xpected_region[2:0]; ctive_error;
411 ype_error; ctual_active; ctual_compressed_context}; */
412#define CDU_REG_ERROR_DATA 0x101014
413/* [WB 216] L1TT ram access. each entry has the following format :
414 {mrege_regions[7:0]; ffset12[5:0]...offset0[5:0];
415 ength12[5:0]...length0[5:0]; d12[3:0]...id0[3:0]} */
416#define CDU_REG_L1TT 0x101800
417/* [WB 24] MATT ram access. each entry has the following
418 format:{RegionLength[11:0]; egionOffset[11:0]} */
419#define CDU_REG_MATT 0x101100
420/* [RW 1] when this bit is set the CDU operates in e1hmf mode */
421#define CDU_REG_MF_MODE 0x101050
422/* [R 1] indication the initializing the activity counter by the hardware
423 was done. */
424#define CFC_REG_AC_INIT_DONE 0x104078
425/* [RW 13] activity counter ram access */
426#define CFC_REG_ACTIVITY_COUNTER 0x104400
427#define CFC_REG_ACTIVITY_COUNTER_SIZE 256
428/* [R 1] indication the initializing the cams by the hardware was done. */
429#define CFC_REG_CAM_INIT_DONE 0x10407c
430/* [RW 2] Interrupt mask register #0 read/write */
431#define CFC_REG_CFC_INT_MASK 0x104108
432/* [R 2] Interrupt register #0 read */
433#define CFC_REG_CFC_INT_STS 0x1040fc
434/* [RC 2] Interrupt register #0 read clear */
435#define CFC_REG_CFC_INT_STS_CLR 0x104100
436/* [RW 4] Parity mask register #0 read/write */
437#define CFC_REG_CFC_PRTY_MASK 0x104118
438/* [R 4] Parity register #0 read */
439#define CFC_REG_CFC_PRTY_STS 0x10410c
440/* [RC 4] Parity register #0 read clear */
441#define CFC_REG_CFC_PRTY_STS_CLR 0x104110
442/* [RW 21] CID cam access (21:1 - Data; alid - 0) */
443#define CFC_REG_CID_CAM 0x104800
444#define CFC_REG_CONTROL0 0x104028
445#define CFC_REG_DEBUG0 0x104050
446/* [RW 14] indicates per error (in #cfc_registers_cfc_error_vector.cfc_error
447 vector) whether the cfc should be disabled upon it */
448#define CFC_REG_DISABLE_ON_ERROR 0x104044
449/* [RC 14] CFC error vector. when the CFC detects an internal error it will
450 set one of these bits. the bit description can be found in CFC
451 specifications */
452#define CFC_REG_ERROR_VECTOR 0x10403c
453/* [WB 93] LCID info ram access */
454#define CFC_REG_INFO_RAM 0x105000
455#define CFC_REG_INFO_RAM_SIZE 1024
456#define CFC_REG_INIT_REG 0x10404c
457#define CFC_REG_INTERFACES 0x104058
458/* [RW 24] {weight_load_client7[2:0] to weight_load_client0[2:0]}. this
459 field allows changing the priorities of the weighted-round-robin arbiter
460 which selects which CFC load client should be served next */
461#define CFC_REG_LCREQ_WEIGHTS 0x104084
462/* [RW 16] Link List ram access; data = {prev_lcid; ext_lcid} */
463#define CFC_REG_LINK_LIST 0x104c00
464#define CFC_REG_LINK_LIST_SIZE 256
465/* [R 1] indication the initializing the link list by the hardware was done. */
466#define CFC_REG_LL_INIT_DONE 0x104074
467/* [R 9] Number of allocated LCIDs which are at empty state */
468#define CFC_REG_NUM_LCIDS_ALLOC 0x104020
469/* [R 9] Number of Arriving LCIDs in Link List Block */
470#define CFC_REG_NUM_LCIDS_ARRIVING 0x104004
471#define CFC_REG_NUM_LCIDS_INSIDE_PF 0x104120
472/* [R 9] Number of Leaving LCIDs in Link List Block */
473#define CFC_REG_NUM_LCIDS_LEAVING 0x104018
474#define CFC_REG_WEAK_ENABLE_PF 0x104124
475/* [RW 8] The event id for aggregated interrupt 0 */
476#define CSDM_REG_AGG_INT_EVENT_0 0xc2038
477#define CSDM_REG_AGG_INT_EVENT_10 0xc2060
478#define CSDM_REG_AGG_INT_EVENT_11 0xc2064
479#define CSDM_REG_AGG_INT_EVENT_12 0xc2068
480#define CSDM_REG_AGG_INT_EVENT_13 0xc206c
481#define CSDM_REG_AGG_INT_EVENT_14 0xc2070
482#define CSDM_REG_AGG_INT_EVENT_15 0xc2074
483#define CSDM_REG_AGG_INT_EVENT_16 0xc2078
484#define CSDM_REG_AGG_INT_EVENT_2 0xc2040
485#define CSDM_REG_AGG_INT_EVENT_3 0xc2044
486#define CSDM_REG_AGG_INT_EVENT_4 0xc2048
487#define CSDM_REG_AGG_INT_EVENT_5 0xc204c
488#define CSDM_REG_AGG_INT_EVENT_6 0xc2050
489#define CSDM_REG_AGG_INT_EVENT_7 0xc2054
490#define CSDM_REG_AGG_INT_EVENT_8 0xc2058
491#define CSDM_REG_AGG_INT_EVENT_9 0xc205c
492/* [RW 1] For each aggregated interrupt index whether the mode is normal (0)
493 or auto-mask-mode (1) */
494#define CSDM_REG_AGG_INT_MODE_10 0xc21e0
495#define CSDM_REG_AGG_INT_MODE_11 0xc21e4
496#define CSDM_REG_AGG_INT_MODE_12 0xc21e8
497#define CSDM_REG_AGG_INT_MODE_13 0xc21ec
498#define CSDM_REG_AGG_INT_MODE_14 0xc21f0
499#define CSDM_REG_AGG_INT_MODE_15 0xc21f4
500#define CSDM_REG_AGG_INT_MODE_16 0xc21f8
501#define CSDM_REG_AGG_INT_MODE_6 0xc21d0
502#define CSDM_REG_AGG_INT_MODE_7 0xc21d4
503#define CSDM_REG_AGG_INT_MODE_8 0xc21d8
504#define CSDM_REG_AGG_INT_MODE_9 0xc21dc
505/* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
506#define CSDM_REG_CFC_RSP_START_ADDR 0xc2008
507/* [RW 16] The maximum value of the completion counter #0 */
508#define CSDM_REG_CMP_COUNTER_MAX0 0xc201c
509/* [RW 16] The maximum value of the completion counter #1 */
510#define CSDM_REG_CMP_COUNTER_MAX1 0xc2020
511/* [RW 16] The maximum value of the completion counter #2 */
512#define CSDM_REG_CMP_COUNTER_MAX2 0xc2024
513/* [RW 16] The maximum value of the completion counter #3 */
514#define CSDM_REG_CMP_COUNTER_MAX3 0xc2028
515/* [RW 13] The start address in the internal RAM for the completion
516 counters. */
517#define CSDM_REG_CMP_COUNTER_START_ADDR 0xc200c
518/* [RW 32] Interrupt mask register #0 read/write */
519#define CSDM_REG_CSDM_INT_MASK_0 0xc229c
520#define CSDM_REG_CSDM_INT_MASK_1 0xc22ac
521/* [R 32] Interrupt register #0 read */
522#define CSDM_REG_CSDM_INT_STS_0 0xc2290
523#define CSDM_REG_CSDM_INT_STS_1 0xc22a0
524/* [RW 11] Parity mask register #0 read/write */
525#define CSDM_REG_CSDM_PRTY_MASK 0xc22bc
526/* [R 11] Parity register #0 read */
527#define CSDM_REG_CSDM_PRTY_STS 0xc22b0
528/* [RC 11] Parity register #0 read clear */
529#define CSDM_REG_CSDM_PRTY_STS_CLR 0xc22b4
530#define CSDM_REG_ENABLE_IN1 0xc2238
531#define CSDM_REG_ENABLE_IN2 0xc223c
532#define CSDM_REG_ENABLE_OUT1 0xc2240
533#define CSDM_REG_ENABLE_OUT2 0xc2244
534/* [RW 4] The initial number of messages that can be sent to the pxp control
535 interface without receiving any ACK. */
536#define CSDM_REG_INIT_CREDIT_PXP_CTRL 0xc24bc
537/* [ST 32] The number of ACK after placement messages received */
538#define CSDM_REG_NUM_OF_ACK_AFTER_PLACE 0xc227c
539/* [ST 32] The number of packet end messages received from the parser */
540#define CSDM_REG_NUM_OF_PKT_END_MSG 0xc2274
541/* [ST 32] The number of requests received from the pxp async if */
542#define CSDM_REG_NUM_OF_PXP_ASYNC_REQ 0xc2278
543/* [ST 32] The number of commands received in queue 0 */
544#define CSDM_REG_NUM_OF_Q0_CMD 0xc2248
545/* [ST 32] The number of commands received in queue 10 */
546#define CSDM_REG_NUM_OF_Q10_CMD 0xc226c
547/* [ST 32] The number of commands received in queue 11 */
548#define CSDM_REG_NUM_OF_Q11_CMD 0xc2270
549/* [ST 32] The number of commands received in queue 1 */
550#define CSDM_REG_NUM_OF_Q1_CMD 0xc224c
551/* [ST 32] The number of commands received in queue 3 */
552#define CSDM_REG_NUM_OF_Q3_CMD 0xc2250
553/* [ST 32] The number of commands received in queue 4 */
554#define CSDM_REG_NUM_OF_Q4_CMD 0xc2254
555/* [ST 32] The number of commands received in queue 5 */
556#define CSDM_REG_NUM_OF_Q5_CMD 0xc2258
557/* [ST 32] The number of commands received in queue 6 */
558#define CSDM_REG_NUM_OF_Q6_CMD 0xc225c
559/* [ST 32] The number of commands received in queue 7 */
560#define CSDM_REG_NUM_OF_Q7_CMD 0xc2260
561/* [ST 32] The number of commands received in queue 8 */
562#define CSDM_REG_NUM_OF_Q8_CMD 0xc2264
563/* [ST 32] The number of commands received in queue 9 */
564#define CSDM_REG_NUM_OF_Q9_CMD 0xc2268
565/* [RW 13] The start address in the internal RAM for queue counters */
566#define CSDM_REG_Q_COUNTER_START_ADDR 0xc2010
567/* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
568#define CSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0xc2548
569/* [R 1] parser fifo empty in sdm_sync block */
570#define CSDM_REG_SYNC_PARSER_EMPTY 0xc2550
571/* [R 1] parser serial fifo empty in sdm_sync block */
572#define CSDM_REG_SYNC_SYNC_EMPTY 0xc2558
573/* [RW 32] Tick for timer counter. Applicable only when
574 ~csdm_registers_timer_tick_enable.timer_tick_enable =1 */
575#define CSDM_REG_TIMER_TICK 0xc2000
576/* [RW 5] The number of time_slots in the arbitration cycle */
577#define CSEM_REG_ARB_CYCLE_SIZE 0x200034
578/* [RW 3] The source that is associated with arbitration element 0. Source
579 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
580 sleeping thread with priority 1; 4- sleeping thread with priority 2 */
581#define CSEM_REG_ARB_ELEMENT0 0x200020
582/* [RW 3] The source that is associated with arbitration element 1. Source
583 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
584 sleeping thread with priority 1; 4- sleeping thread with priority 2.
585 Could not be equal to register ~csem_registers_arb_element0.arb_element0 */
586#define CSEM_REG_ARB_ELEMENT1 0x200024
587/* [RW 3] The source that is associated with arbitration element 2. Source
588 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
589 sleeping thread with priority 1; 4- sleeping thread with priority 2.
590 Could not be equal to register ~csem_registers_arb_element0.arb_element0
591 and ~csem_registers_arb_element1.arb_element1 */
592#define CSEM_REG_ARB_ELEMENT2 0x200028
593/* [RW 3] The source that is associated with arbitration element 3. Source
594 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
595 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could
596 not be equal to register ~csem_registers_arb_element0.arb_element0 and
597 ~csem_registers_arb_element1.arb_element1 and
598 ~csem_registers_arb_element2.arb_element2 */
599#define CSEM_REG_ARB_ELEMENT3 0x20002c
600/* [RW 3] The source that is associated with arbitration element 4. Source
601 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
602 sleeping thread with priority 1; 4- sleeping thread with priority 2.
603 Could not be equal to register ~csem_registers_arb_element0.arb_element0
604 and ~csem_registers_arb_element1.arb_element1 and
605 ~csem_registers_arb_element2.arb_element2 and
606 ~csem_registers_arb_element3.arb_element3 */
607#define CSEM_REG_ARB_ELEMENT4 0x200030
608/* [RW 32] Interrupt mask register #0 read/write */
609#define CSEM_REG_CSEM_INT_MASK_0 0x200110
610#define CSEM_REG_CSEM_INT_MASK_1 0x200120
611/* [R 32] Interrupt register #0 read */
612#define CSEM_REG_CSEM_INT_STS_0 0x200104
613#define CSEM_REG_CSEM_INT_STS_1 0x200114
614/* [RW 32] Parity mask register #0 read/write */
615#define CSEM_REG_CSEM_PRTY_MASK_0 0x200130
616#define CSEM_REG_CSEM_PRTY_MASK_1 0x200140
617/* [R 32] Parity register #0 read */
618#define CSEM_REG_CSEM_PRTY_STS_0 0x200124
619#define CSEM_REG_CSEM_PRTY_STS_1 0x200134
620/* [RC 32] Parity register #0 read clear */
621#define CSEM_REG_CSEM_PRTY_STS_CLR_0 0x200128
622#define CSEM_REG_CSEM_PRTY_STS_CLR_1 0x200138
623#define CSEM_REG_ENABLE_IN 0x2000a4
624#define CSEM_REG_ENABLE_OUT 0x2000a8
625/* [RW 32] This address space contains all registers and memories that are
626 placed in SEM_FAST block. The SEM_FAST registers are described in
627 appendix B. In order to access the sem_fast registers the base address
628 ~fast_memory.fast_memory should be added to eachsem_fast register offset. */
629#define CSEM_REG_FAST_MEMORY 0x220000
630/* [RW 1] Disables input messages from FIC0 May be updated during run_time
631 by the microcode */
632#define CSEM_REG_FIC0_DISABLE 0x200224
633/* [RW 1] Disables input messages from FIC1 May be updated during run_time
634 by the microcode */
635#define CSEM_REG_FIC1_DISABLE 0x200234
636/* [RW 15] Interrupt table Read and write access to it is not possible in
637 the middle of the work */
638#define CSEM_REG_INT_TABLE 0x200400
639/* [ST 24] Statistics register. The number of messages that entered through
640 FIC0 */
641#define CSEM_REG_MSG_NUM_FIC0 0x200000
642/* [ST 24] Statistics register. The number of messages that entered through
643 FIC1 */
644#define CSEM_REG_MSG_NUM_FIC1 0x200004
645/* [ST 24] Statistics register. The number of messages that were sent to
646 FOC0 */
647#define CSEM_REG_MSG_NUM_FOC0 0x200008
648/* [ST 24] Statistics register. The number of messages that were sent to
649 FOC1 */
650#define CSEM_REG_MSG_NUM_FOC1 0x20000c
651/* [ST 24] Statistics register. The number of messages that were sent to
652 FOC2 */
653#define CSEM_REG_MSG_NUM_FOC2 0x200010
654/* [ST 24] Statistics register. The number of messages that were sent to
655 FOC3 */
656#define CSEM_REG_MSG_NUM_FOC3 0x200014
657/* [RW 1] Disables input messages from the passive buffer May be updated
658 during run_time by the microcode */
659#define CSEM_REG_PAS_DISABLE 0x20024c
660/* [WB 128] Debug only. Passive buffer memory */
661#define CSEM_REG_PASSIVE_BUFFER 0x202000
662/* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
663#define CSEM_REG_PRAM 0x240000
664/* [R 16] Valid sleeping threads indication have bit per thread */
665#define CSEM_REG_SLEEP_THREADS_VALID 0x20026c
666/* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
667#define CSEM_REG_SLOW_EXT_STORE_EMPTY 0x2002a0
668/* [RW 16] List of free threads . There is a bit per thread. */
669#define CSEM_REG_THREADS_LIST 0x2002e4
670/* [RW 3] The arbitration scheme of time_slot 0 */
671#define CSEM_REG_TS_0_AS 0x200038
672/* [RW 3] The arbitration scheme of time_slot 10 */
673#define CSEM_REG_TS_10_AS 0x200060
674/* [RW 3] The arbitration scheme of time_slot 11 */
675#define CSEM_REG_TS_11_AS 0x200064
676/* [RW 3] The arbitration scheme of time_slot 12 */
677#define CSEM_REG_TS_12_AS 0x200068
678/* [RW 3] The arbitration scheme of time_slot 13 */
679#define CSEM_REG_TS_13_AS 0x20006c
680/* [RW 3] The arbitration scheme of time_slot 14 */
681#define CSEM_REG_TS_14_AS 0x200070
682/* [RW 3] The arbitration scheme of time_slot 15 */
683#define CSEM_REG_TS_15_AS 0x200074
684/* [RW 3] The arbitration scheme of time_slot 16 */
685#define CSEM_REG_TS_16_AS 0x200078
686/* [RW 3] The arbitration scheme of time_slot 17 */
687#define CSEM_REG_TS_17_AS 0x20007c
688/* [RW 3] The arbitration scheme of time_slot 18 */
689#define CSEM_REG_TS_18_AS 0x200080
690/* [RW 3] The arbitration scheme of time_slot 1 */
691#define CSEM_REG_TS_1_AS 0x20003c
692/* [RW 3] The arbitration scheme of time_slot 2 */
693#define CSEM_REG_TS_2_AS 0x200040
694/* [RW 3] The arbitration scheme of time_slot 3 */
695#define CSEM_REG_TS_3_AS 0x200044
696/* [RW 3] The arbitration scheme of time_slot 4 */
697#define CSEM_REG_TS_4_AS 0x200048
698/* [RW 3] The arbitration scheme of time_slot 5 */
699#define CSEM_REG_TS_5_AS 0x20004c
700/* [RW 3] The arbitration scheme of time_slot 6 */
701#define CSEM_REG_TS_6_AS 0x200050
702/* [RW 3] The arbitration scheme of time_slot 7 */
703#define CSEM_REG_TS_7_AS 0x200054
704/* [RW 3] The arbitration scheme of time_slot 8 */
705#define CSEM_REG_TS_8_AS 0x200058
706/* [RW 3] The arbitration scheme of time_slot 9 */
707#define CSEM_REG_TS_9_AS 0x20005c
708/* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 64
709 * VF; values 64-67 reset error for 4 PF; values 68-127 are not valid. */
710#define CSEM_REG_VFPF_ERR_NUM 0x200380
711/* [RW 1] Parity mask register #0 read/write */
712#define DBG_REG_DBG_PRTY_MASK 0xc0a8
713/* [R 1] Parity register #0 read */
714#define DBG_REG_DBG_PRTY_STS 0xc09c
715/* [RC 1] Parity register #0 read clear */
716#define DBG_REG_DBG_PRTY_STS_CLR 0xc0a0
717/* [RW 1] When set the DMAE will process the commands as in E1.5. 1.The
718 * function that is used is always SRC-PCI; 2.VF_Valid = 0; 3.VFID=0;
719 * 4.Completion function=0; 5.Error handling=0 */
720#define DMAE_REG_BACKWARD_COMP_EN 0x10207c
721/* [RW 32] Commands memory. The address to command X; row Y is to calculated
722 as 14*X+Y. */
723#define DMAE_REG_CMD_MEM 0x102400
724#define DMAE_REG_CMD_MEM_SIZE 224
725/* [RW 1] If 0 - the CRC-16c initial value is all zeroes; if 1 - the CRC-16c
726 initial value is all ones. */
727#define DMAE_REG_CRC16C_INIT 0x10201c
728/* [RW 1] If 0 - the CRC-16 T10 initial value is all zeroes; if 1 - the
729 CRC-16 T10 initial value is all ones. */
730#define DMAE_REG_CRC16T10_INIT 0x102020
731/* [RW 2] Interrupt mask register #0 read/write */
732#define DMAE_REG_DMAE_INT_MASK 0x102054
733/* [RW 4] Parity mask register #0 read/write */
734#define DMAE_REG_DMAE_PRTY_MASK 0x102064
735/* [R 4] Parity register #0 read */
736#define DMAE_REG_DMAE_PRTY_STS 0x102058
737/* [RC 4] Parity register #0 read clear */
738#define DMAE_REG_DMAE_PRTY_STS_CLR 0x10205c
739/* [RW 1] Command 0 go. */
740#define DMAE_REG_GO_C0 0x102080
741/* [RW 1] Command 1 go. */
742#define DMAE_REG_GO_C1 0x102084
743/* [RW 1] Command 10 go. */
744#define DMAE_REG_GO_C10 0x102088
745/* [RW 1] Command 11 go. */
746#define DMAE_REG_GO_C11 0x10208c
747/* [RW 1] Command 12 go. */
748#define DMAE_REG_GO_C12 0x102090
749/* [RW 1] Command 13 go. */
750#define DMAE_REG_GO_C13 0x102094
751/* [RW 1] Command 14 go. */
752#define DMAE_REG_GO_C14 0x102098
753/* [RW 1] Command 15 go. */
754#define DMAE_REG_GO_C15 0x10209c
755/* [RW 1] Command 2 go. */
756#define DMAE_REG_GO_C2 0x1020a0
757/* [RW 1] Command 3 go. */
758#define DMAE_REG_GO_C3 0x1020a4
759/* [RW 1] Command 4 go. */
760#define DMAE_REG_GO_C4 0x1020a8
761/* [RW 1] Command 5 go. */
762#define DMAE_REG_GO_C5 0x1020ac
763/* [RW 1] Command 6 go. */
764#define DMAE_REG_GO_C6 0x1020b0
765/* [RW 1] Command 7 go. */
766#define DMAE_REG_GO_C7 0x1020b4
767/* [RW 1] Command 8 go. */
768#define DMAE_REG_GO_C8 0x1020b8
769/* [RW 1] Command 9 go. */
770#define DMAE_REG_GO_C9 0x1020bc
771/* [RW 1] DMAE GRC Interface (Target; aster) enable. If 0 - the acknowledge
772 input is disregarded; valid is deasserted; all other signals are treated
773 as usual; if 1 - normal activity. */
774#define DMAE_REG_GRC_IFEN 0x102008
775/* [RW 1] DMAE PCI Interface (Request; ead; rite) enable. If 0 - the
776 acknowledge input is disregarded; valid is deasserted; full is asserted;
777 all other signals are treated as usual; if 1 - normal activity. */
778#define DMAE_REG_PCI_IFEN 0x102004
779/* [RW 4] DMAE- PCI Request Interface initial credit. Write writes the
780 initial value to the credit counter; related to the address. Read returns
781 the current value of the counter. */
782#define DMAE_REG_PXP_REQ_INIT_CRD 0x1020c0
783/* [RW 8] Aggregation command. */
784#define DORQ_REG_AGG_CMD0 0x170060
785/* [RW 8] Aggregation command. */
786#define DORQ_REG_AGG_CMD1 0x170064
787/* [RW 8] Aggregation command. */
788#define DORQ_REG_AGG_CMD2 0x170068
789/* [RW 8] Aggregation command. */
790#define DORQ_REG_AGG_CMD3 0x17006c
791/* [RW 28] UCM Header. */
792#define DORQ_REG_CMHEAD_RX 0x170050
793/* [RW 32] Doorbell address for RBC doorbells (function 0). */
794#define DORQ_REG_DB_ADDR0 0x17008c
795/* [RW 5] Interrupt mask register #0 read/write */
796#define DORQ_REG_DORQ_INT_MASK 0x170180
797/* [R 5] Interrupt register #0 read */
798#define DORQ_REG_DORQ_INT_STS 0x170174
799/* [RC 5] Interrupt register #0 read clear */
800#define DORQ_REG_DORQ_INT_STS_CLR 0x170178
801/* [RW 2] Parity mask register #0 read/write */
802#define DORQ_REG_DORQ_PRTY_MASK 0x170190
803/* [R 2] Parity register #0 read */
804#define DORQ_REG_DORQ_PRTY_STS 0x170184
805/* [RC 2] Parity register #0 read clear */
806#define DORQ_REG_DORQ_PRTY_STS_CLR 0x170188
807/* [RW 8] The address to write the DPM CID to STORM. */
808#define DORQ_REG_DPM_CID_ADDR 0x170044
809/* [RW 5] The DPM mode CID extraction offset. */
810#define DORQ_REG_DPM_CID_OFST 0x170030
811/* [RW 12] The threshold of the DQ FIFO to send the almost full interrupt. */
812#define DORQ_REG_DQ_FIFO_AFULL_TH 0x17007c
813/* [RW 12] The threshold of the DQ FIFO to send the full interrupt. */
814#define DORQ_REG_DQ_FIFO_FULL_TH 0x170078
815/* [R 13] Current value of the DQ FIFO fill level according to following
816 pointer. The range is 0 - 256 FIFO rows; where each row stands for the
817 doorbell. */
818#define DORQ_REG_DQ_FILL_LVLF 0x1700a4
819/* [R 1] DQ FIFO full status. Is set; when FIFO filling level is more or
820 equal to full threshold; reset on full clear. */
821#define DORQ_REG_DQ_FULL_ST 0x1700c0
822/* [RW 28] The value sent to CM header in the case of CFC load error. */
823#define DORQ_REG_ERR_CMHEAD 0x170058
824#define DORQ_REG_IF_EN 0x170004
825#define DORQ_REG_MODE_ACT 0x170008
826/* [RW 5] The normal mode CID extraction offset. */
827#define DORQ_REG_NORM_CID_OFST 0x17002c
828/* [RW 28] TCM Header when only TCP context is loaded. */
829#define DORQ_REG_NORM_CMHEAD_TX 0x17004c
830/* [RW 3] The number of simultaneous outstanding requests to Context Fetch
831 Interface. */
832#define DORQ_REG_OUTST_REQ 0x17003c
833#define DORQ_REG_PF_USAGE_CNT 0x1701d0
834#define DORQ_REG_REGN 0x170038
835/* [R 4] Current value of response A counter credit. Initial credit is
836 configured through write to ~dorq_registers_rsp_init_crd.rsp_init_crd
837 register. */
838#define DORQ_REG_RSPA_CRD_CNT 0x1700ac
839/* [R 4] Current value of response B counter credit. Initial credit is
840 configured through write to ~dorq_registers_rsp_init_crd.rsp_init_crd
841 register. */
842#define DORQ_REG_RSPB_CRD_CNT 0x1700b0
843/* [RW 4] The initial credit at the Doorbell Response Interface. The write
844 writes the same initial credit to the rspa_crd_cnt and rspb_crd_cnt. The
845 read reads this written value. */
846#define DORQ_REG_RSP_INIT_CRD 0x170048
847/* [RW 4] Initial activity counter value on the load request; when the
848 shortcut is done. */
849#define DORQ_REG_SHRT_ACT_CNT 0x170070
850/* [RW 28] TCM Header when both ULP and TCP context is loaded. */
851#define DORQ_REG_SHRT_CMHEAD 0x170054
852#define HC_CONFIG_0_REG_ATTN_BIT_EN_0 (0x1<<4)
853#define HC_CONFIG_0_REG_BLOCK_DISABLE_0 (0x1<<0)
854#define HC_CONFIG_0_REG_INT_LINE_EN_0 (0x1<<3)
855#define HC_CONFIG_0_REG_MSI_ATTN_EN_0 (0x1<<7)
856#define HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 (0x1<<2)
857#define HC_CONFIG_0_REG_SINGLE_ISR_EN_0 (0x1<<1)
858#define HC_CONFIG_1_REG_BLOCK_DISABLE_1 (0x1<<0)
859#define HC_REG_AGG_INT_0 0x108050
860#define HC_REG_AGG_INT_1 0x108054
861#define HC_REG_ATTN_BIT 0x108120
862#define HC_REG_ATTN_IDX 0x108100
863#define HC_REG_ATTN_MSG0_ADDR_L 0x108018
864#define HC_REG_ATTN_MSG1_ADDR_L 0x108020
865#define HC_REG_ATTN_NUM_P0 0x108038
866#define HC_REG_ATTN_NUM_P1 0x10803c
867#define HC_REG_COMMAND_REG 0x108180
868#define HC_REG_CONFIG_0 0x108000
869#define HC_REG_CONFIG_1 0x108004
870#define HC_REG_FUNC_NUM_P0 0x1080ac
871#define HC_REG_FUNC_NUM_P1 0x1080b0
872/* [RW 3] Parity mask register #0 read/write */
873#define HC_REG_HC_PRTY_MASK 0x1080a0
874/* [R 3] Parity register #0 read */
875#define HC_REG_HC_PRTY_STS 0x108094
876/* [RC 3] Parity register #0 read clear */
877#define HC_REG_HC_PRTY_STS_CLR 0x108098
878#define HC_REG_INT_MASK 0x108108
879#define HC_REG_LEADING_EDGE_0 0x108040
880#define HC_REG_LEADING_EDGE_1 0x108048
881#define HC_REG_MAIN_MEMORY 0x108800
882#define HC_REG_MAIN_MEMORY_SIZE 152
883#define HC_REG_P0_PROD_CONS 0x108200
884#define HC_REG_P1_PROD_CONS 0x108400
885#define HC_REG_PBA_COMMAND 0x108140
886#define HC_REG_PCI_CONFIG_0 0x108010
887#define HC_REG_PCI_CONFIG_1 0x108014
888#define HC_REG_STATISTIC_COUNTERS 0x109000
889#define HC_REG_TRAILING_EDGE_0 0x108044
890#define HC_REG_TRAILING_EDGE_1 0x10804c
891#define HC_REG_UC_RAM_ADDR_0 0x108028
892#define HC_REG_UC_RAM_ADDR_1 0x108030
893#define HC_REG_USTORM_ADDR_FOR_COALESCE 0x108068
894#define HC_REG_VQID_0 0x108008
895#define HC_REG_VQID_1 0x10800c
896#define IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN (0x1<<1)
897#define IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE (0x1<<0)
898#define IGU_REG_ATTENTION_ACK_BITS 0x130108
899/* [R 4] Debug: attn_fsm */
900#define IGU_REG_ATTN_FSM 0x130054
901#define IGU_REG_ATTN_MSG_ADDR_H 0x13011c
902#define IGU_REG_ATTN_MSG_ADDR_L 0x130120
903/* [R 4] Debug: [3] - attention write done message is pending (0-no pending;
904 * 1-pending). [2:0] = PFID. Pending means attention message was sent; but
905 * write done didn't receive. */
906#define IGU_REG_ATTN_WRITE_DONE_PENDING 0x130030
907#define IGU_REG_BLOCK_CONFIGURATION 0x130000
908#define IGU_REG_COMMAND_REG_32LSB_DATA 0x130124
909#define IGU_REG_COMMAND_REG_CTRL 0x13012c
910/* [WB_R 32] Cleanup bit status per SB. 1 = cleanup is set. 0 = cleanup bit
911 * is clear. The bits in this registers are set and clear via the producer
912 * command. Data valid only in addresses 0-4. all the rest are zero. */
913#define IGU_REG_CSTORM_TYPE_0_SB_CLEANUP 0x130200
914/* [R 5] Debug: ctrl_fsm */
915#define IGU_REG_CTRL_FSM 0x130064
916/* [R 1] data available for error memory. If this bit is clear do not red
917 * from error_handling_memory. */
918#define IGU_REG_ERROR_HANDLING_DATA_VALID 0x130130
919/* [RW 11] Parity mask register #0 read/write */
920#define IGU_REG_IGU_PRTY_MASK 0x1300a8
921/* [R 11] Parity register #0 read */
922#define IGU_REG_IGU_PRTY_STS 0x13009c
923/* [RC 11] Parity register #0 read clear */
924#define IGU_REG_IGU_PRTY_STS_CLR 0x1300a0
925/* [R 4] Debug: int_handle_fsm */
926#define IGU_REG_INT_HANDLE_FSM 0x130050
927#define IGU_REG_LEADING_EDGE_LATCH 0x130134
928/* [RW 14] mapping CAM; relevant for E2 operating mode only. [0] - valid.
929 * [6:1] - vector number; [13:7] - FID (if VF - [13] = 0; [12:7] = VF
930 * number; if PF - [13] = 1; [12:10] = 0; [9:7] = PF number); */
931#define IGU_REG_MAPPING_MEMORY 0x131000
932#define IGU_REG_MAPPING_MEMORY_SIZE 136
933#define IGU_REG_PBA_STATUS_LSB 0x130138
934#define IGU_REG_PBA_STATUS_MSB 0x13013c
935#define IGU_REG_PCI_PF_MSI_EN 0x130140
936#define IGU_REG_PCI_PF_MSIX_EN 0x130144
937#define IGU_REG_PCI_PF_MSIX_FUNC_MASK 0x130148
938/* [WB_R 32] Each bit represent the pending bits status for that SB. 0 = no
939 * pending; 1 = pending. Pendings means interrupt was asserted; and write
940 * done was not received. Data valid only in addresses 0-4. all the rest are
941 * zero. */
942#define IGU_REG_PENDING_BITS_STATUS 0x130300
943#define IGU_REG_PF_CONFIGURATION 0x130154
944/* [RW 20] producers only. E2 mode: address 0-135 match to the mapping
945 * memory; 136 - PF0 default prod; 137 PF1 default prod; 138 - PF2 default
946 * prod; 139 PF3 default prod; 140 - PF0 - ATTN prod; 141 - PF1 - ATTN prod;
947 * 142 - PF2 - ATTN prod; 143 - PF3 - ATTN prod; 144-147 reserved. E1.5 mode
948 * - In backward compatible mode; for non default SB; each even line in the
949 * memory holds the U producer and each odd line hold the C producer. The
950 * first 128 producer are for NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The
951 * last 20 producers are for the DSB for each PF. each PF has five segments
952 * (the order inside each segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
953 * 132-135 C prods; 136-139 X prods; 140-143 T prods; 144-147 ATTN prods; */
954#define IGU_REG_PROD_CONS_MEMORY 0x132000
955/* [R 3] Debug: pxp_arb_fsm */
956#define IGU_REG_PXP_ARB_FSM 0x130068
957/* [RW 6] Write one for each bit will reset the appropriate memory. When the
958 * memory reset finished the appropriate bit will be clear. Bit 0 - mapping
959 * memory; Bit 1 - SB memory; Bit 2 - SB interrupt and mask register; Bit 3
960 * - MSIX memory; Bit 4 - PBA memory; Bit 5 - statistics; */
961#define IGU_REG_RESET_MEMORIES 0x130158
962/* [R 4] Debug: sb_ctrl_fsm */
963#define IGU_REG_SB_CTRL_FSM 0x13004c
964#define IGU_REG_SB_INT_BEFORE_MASK_LSB 0x13015c
965#define IGU_REG_SB_INT_BEFORE_MASK_MSB 0x130160
966#define IGU_REG_SB_MASK_LSB 0x130164
967#define IGU_REG_SB_MASK_MSB 0x130168
968/* [RW 16] Number of command that were dropped without causing an interrupt
969 * due to: read access for WO BAR address; or write access for RO BAR
970 * address or any access for reserved address or PCI function error is set
971 * and address is not MSIX; PBA or cleanup */
972#define IGU_REG_SILENT_DROP 0x13016c
973/* [RW 10] Number of MSI/MSIX/ATTN messages sent for the function: 0-63 -
974 * number of MSIX messages per VF; 64-67 - number of MSI/MSIX messages per
975 * PF; 68-71 number of ATTN messages per PF */
976#define IGU_REG_STATISTIC_NUM_MESSAGE_SENT 0x130800
977/* [RW 32] Number of cycles the timer mask masking the IGU interrupt when a
978 * timer mask command arrives. Value must be bigger than 100. */
979#define IGU_REG_TIMER_MASKING_VALUE 0x13003c
980#define IGU_REG_TRAILING_EDGE_LATCH 0x130104
981#define IGU_REG_VF_CONFIGURATION 0x130170
982/* [WB_R 32] Each bit represent write done pending bits status for that SB
983 * (MSI/MSIX message was sent and write done was not received yet). 0 =
984 * clear; 1 = set. Data valid only in addresses 0-4. all the rest are zero. */
985#define IGU_REG_WRITE_DONE_PENDING 0x130480
986#define MCP_A_REG_MCPR_SCRATCH 0x3a0000
987#define MCP_REG_MCPR_CPU_PROGRAM_COUNTER 0x8501c
988#define MCP_REG_MCPR_GP_INPUTS 0x800c0
989#define MCP_REG_MCPR_GP_OENABLE 0x800c8
990#define MCP_REG_MCPR_GP_OUTPUTS 0x800c4
991#define MCP_REG_MCPR_IMC_COMMAND 0x85900
992#define MCP_REG_MCPR_IMC_DATAREG0 0x85920
993#define MCP_REG_MCPR_IMC_SLAVE_CONTROL 0x85904
994#define MCP_REG_MCPR_CPU_PROGRAM_COUNTER 0x8501c
995#define MCP_REG_MCPR_NVM_ACCESS_ENABLE 0x86424
996#define MCP_REG_MCPR_NVM_ADDR 0x8640c
997#define MCP_REG_MCPR_NVM_CFG4 0x8642c
998#define MCP_REG_MCPR_NVM_COMMAND 0x86400
999#define MCP_REG_MCPR_NVM_READ 0x86410
1000#define MCP_REG_MCPR_NVM_SW_ARB 0x86420
1001#define MCP_REG_MCPR_NVM_WRITE 0x86408
1002#define MCP_REG_MCPR_SCRATCH 0xa0000
1003#define MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK (0x1<<1)
1004#define MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK (0x1<<0)
1005/* [R 32] read first 32 bit after inversion of function 0. mapped as
1006 follows: [0] NIG attention for function0; [1] NIG attention for
1007 function1; [2] GPIO1 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp;
1008 [6] GPIO1 function 1; [7] GPIO2 function 1; [8] GPIO3 function 1; [9]
1009 GPIO4 function 1; [10] PCIE glue/PXP VPD event function0; [11] PCIE
1010 glue/PXP VPD event function1; [12] PCIE glue/PXP Expansion ROM event0;
1011 [13] PCIE glue/PXP Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16]
1012 MSI/X indication for mcp; [17] MSI/X indication for function 1; [18] BRB
1013 Parity error; [19] BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw
1014 interrupt; [22] SRC Parity error; [23] SRC Hw interrupt; [24] TSDM Parity
1015 error; [25] TSDM Hw interrupt; [26] TCM Parity error; [27] TCM Hw
1016 interrupt; [28] TSEMI Parity error; [29] TSEMI Hw interrupt; [30] PBF
1017 Parity error; [31] PBF Hw interrupt; */
1018#define MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 0xa42c
1019#define MISC_REG_AEU_AFTER_INVERT_1_FUNC_1 0xa430
1020/* [R 32] read first 32 bit after inversion of mcp. mapped as follows: [0]
1021 NIG attention for function0; [1] NIG attention for function1; [2] GPIO1
1022 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1;
1023 [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10]
1024 PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event
1025 function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP
1026 Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for
1027 mcp; [17] MSI/X indication for function 1; [18] BRB Parity error; [19]
1028 BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC
1029 Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw
1030 interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI
1031 Parity error; [29] TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw
1032 interrupt; */
1033#define MISC_REG_AEU_AFTER_INVERT_1_MCP 0xa434
1034/* [R 32] read second 32 bit after inversion of function 0. mapped as
1035 follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
1036 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
1037 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
1038 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
1039 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
1040 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
1041 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
1042 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
1043 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
1044 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
1045 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
1046 interrupt; */
1047#define MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 0xa438
1048#define MISC_REG_AEU_AFTER_INVERT_2_FUNC_1 0xa43c
1049/* [R 32] read second 32 bit after inversion of mcp. mapped as follows: [0]
1050 PBClient Parity error; [1] PBClient Hw interrupt; [2] QM Parity error;
1051 [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw interrupt;
1052 [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9]
1053 XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12]
1054 DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity
1055 error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux
1056 PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt;
1057 [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error;
1058 [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt;
1059 [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error;
1060 [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt; */
1061#define MISC_REG_AEU_AFTER_INVERT_2_MCP 0xa440
1062/* [R 32] read third 32 bit after inversion of function 0. mapped as
1063 follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity
1064 error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; [5]
1065 PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
1066 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
1067 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
1068 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
1069 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
1070 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
1071 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
1072 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
1073 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
1074 attn1; */
1075#define MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 0xa444
1076#define MISC_REG_AEU_AFTER_INVERT_3_FUNC_1 0xa448
1077/* [R 32] read third 32 bit after inversion of mcp. mapped as follows: [0]
1078 CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity error; [3] PXP
1079 Hw interrupt; [4] PXPpciClockClient Parity error; [5] PXPpciClockClient
1080 Hw interrupt; [6] CFC Parity error; [7] CFC Hw interrupt; [8] CDU Parity
1081 error; [9] CDU Hw interrupt; [10] DMAE Parity error; [11] DMAE Hw
1082 interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) Hw interrupt; [14]
1083 MISC Parity error; [15] MISC Hw interrupt; [16] pxp_misc_mps_attn; [17]
1084 Flash event; [18] SMB event; [19] MCP attn0; [20] MCP attn1; [21] SW
1085 timers attn_1 func0; [22] SW timers attn_2 func0; [23] SW timers attn_3
1086 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW timers attn_1
1087 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 func1; [29] SW
1088 timers attn_4 func1; [30] General attn0; [31] General attn1; */
1089#define MISC_REG_AEU_AFTER_INVERT_3_MCP 0xa44c
1090/* [R 32] read fourth 32 bit after inversion of function 0. mapped as
1091 follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1092 General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
1093 [7] General attn9; [8] General attn10; [9] General attn11; [10] General
1094 attn12; [11] General attn13; [12] General attn14; [13] General attn15;
1095 [14] General attn16; [15] General attn17; [16] General attn18; [17]
1096 General attn19; [18] General attn20; [19] General attn21; [20] Main power
1097 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
1098 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
1099 Latched timeout attention; [27] GRC Latched reserved access attention;
1100 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
1101 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
1102#define MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 0xa450
1103#define MISC_REG_AEU_AFTER_INVERT_4_FUNC_1 0xa454
1104/* [R 32] read fourth 32 bit after inversion of mcp. mapped as follows: [0]
1105 General attn2; [1] General attn3; [2] General attn4; [3] General attn5;
1106 [4] General attn6; [5] General attn7; [6] General attn8; [7] General
1107 attn9; [8] General attn10; [9] General attn11; [10] General attn12; [11]
1108 General attn13; [12] General attn14; [13] General attn15; [14] General
1109 attn16; [15] General attn17; [16] General attn18; [17] General attn19;
1110 [18] General attn20; [19] General attn21; [20] Main power interrupt; [21]
1111 RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN Latched attn; [24]
1112 RBCU Latched attn; [25] RBCP Latched attn; [26] GRC Latched timeout
1113 attention; [27] GRC Latched reserved access attention; [28] MCP Latched
1114 rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP Latched
1115 ump_tx_parity; [31] MCP Latched scpad_parity; */
1116#define MISC_REG_AEU_AFTER_INVERT_4_MCP 0xa458
1117/* [R 32] Read fifth 32 bit after inversion of function 0. Mapped as
1118 * follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC
1119 * attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6]
1120 * CNIG attention (reserved); [7] CNIG parity (reserved); [31-8] Reserved; */
1121#define MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 0xa700
1122/* [W 14] write to this register results with the clear of the latched
1123 signals; one in d0 clears RBCR latch; one in d1 clears RBCT latch; one in
1124 d2 clears RBCN latch; one in d3 clears RBCU latch; one in d4 clears RBCP
1125 latch; one in d5 clears GRC Latched timeout attention; one in d6 clears
1126 GRC Latched reserved access attention; one in d7 clears Latched
1127 rom_parity; one in d8 clears Latched ump_rx_parity; one in d9 clears
1128 Latched ump_tx_parity; one in d10 clears Latched scpad_parity (both
1129 ports); one in d11 clears pxpv_misc_mps_attn; one in d12 clears
1130 pxp_misc_exp_rom_attn0; one in d13 clears pxp_misc_exp_rom_attn1; read
1131 from this register return zero */
1132#define MISC_REG_AEU_CLR_LATCH_SIGNAL 0xa45c
1133/* [RW 32] first 32b for enabling the output for function 0 output0. mapped
1134 as follows: [0] NIG attention for function0; [1] NIG attention for
1135 function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function
1136 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
1137 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
1138 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
1139 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
1140 SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X
1141 indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
1142 [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
1143 SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
1144 TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
1145 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
1146#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0 0xa06c
1147#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1 0xa07c
1148#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2 0xa08c
1149#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_3 0xa09c
1150#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_5 0xa0bc
1151#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_6 0xa0cc
1152#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_7 0xa0dc
1153/* [RW 32] first 32b for enabling the output for function 1 output0. mapped
1154 as follows: [0] NIG attention for function0; [1] NIG attention for
1155 function1; [2] GPIO1 function 1; [3] GPIO2 function 1; [4] GPIO3 function
1156 1; [5] GPIO4 function 1; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
1157 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
1158 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
1159 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
1160 SPIO4; [15] SPIO5; [16] MSI/X indication for function 1; [17] MSI/X
1161 indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
1162 [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
1163 SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
1164 TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
1165 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
1166#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 0xa10c
1167#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 0xa11c
1168#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 0xa12c
1169#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_3 0xa13c
1170#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_5 0xa15c
1171#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_6 0xa16c
1172#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_7 0xa17c
1173/* [RW 32] first 32b for enabling the output for close the gate nig. mapped
1174 as follows: [0] NIG attention for function0; [1] NIG attention for
1175 function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function
1176 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
1177 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
1178 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
1179 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
1180 SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X
1181 indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
1182 [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
1183 SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
1184 TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
1185 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
1186#define MISC_REG_AEU_ENABLE1_NIG_0 0xa0ec
1187#define MISC_REG_AEU_ENABLE1_NIG_1 0xa18c
1188/* [RW 32] first 32b for enabling the output for close the gate pxp. mapped
1189 as follows: [0] NIG attention for function0; [1] NIG attention for
1190 function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function
1191 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
1192 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
1193 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
1194 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
1195 SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X
1196 indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
1197 [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
1198 SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
1199 TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
1200 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
1201#define MISC_REG_AEU_ENABLE1_PXP_0 0xa0fc
1202#define MISC_REG_AEU_ENABLE1_PXP_1 0xa19c
1203/* [RW 32] second 32b for enabling the output for function 0 output0. mapped
1204 as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
1205 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
1206 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
1207 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
1208 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
1209 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
1210 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
1211 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
1212 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
1213 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
1214 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
1215 interrupt; */
1216#define MISC_REG_AEU_ENABLE2_FUNC_0_OUT_0 0xa070
1217#define MISC_REG_AEU_ENABLE2_FUNC_0_OUT_1 0xa080
1218/* [RW 32] second 32b for enabling the output for function 1 output0. mapped
1219 as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
1220 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
1221 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
1222 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
1223 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
1224 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
1225 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
1226 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
1227 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
1228 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
1229 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
1230 interrupt; */
1231#define MISC_REG_AEU_ENABLE2_FUNC_1_OUT_0 0xa110
1232#define MISC_REG_AEU_ENABLE2_FUNC_1_OUT_1 0xa120
1233/* [RW 32] second 32b for enabling the output for close the gate nig. mapped
1234 as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
1235 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
1236 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
1237 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
1238 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
1239 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
1240 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
1241 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
1242 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
1243 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
1244 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
1245 interrupt; */
1246#define MISC_REG_AEU_ENABLE2_NIG_0 0xa0f0
1247#define MISC_REG_AEU_ENABLE2_NIG_1 0xa190
1248/* [RW 32] second 32b for enabling the output for close the gate pxp. mapped
1249 as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
1250 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
1251 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
1252 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
1253 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
1254 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
1255 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
1256 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
1257 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
1258 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
1259 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
1260 interrupt; */
1261#define MISC_REG_AEU_ENABLE2_PXP_0 0xa100
1262#define MISC_REG_AEU_ENABLE2_PXP_1 0xa1a0
1263/* [RW 32] third 32b for enabling the output for function 0 output0. mapped
1264 as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP
1265 Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;
1266 [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
1267 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
1268 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
1269 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
1270 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
1271 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
1272 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
1273 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
1274 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
1275 attn1; */
1276#define MISC_REG_AEU_ENABLE3_FUNC_0_OUT_0 0xa074
1277#define MISC_REG_AEU_ENABLE3_FUNC_0_OUT_1 0xa084
1278/* [RW 32] third 32b for enabling the output for function 1 output0. mapped
1279 as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP
1280 Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;
1281 [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
1282 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
1283 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
1284 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
1285 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
1286 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
1287 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
1288 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
1289 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
1290 attn1; */
1291#define MISC_REG_AEU_ENABLE3_FUNC_1_OUT_0 0xa114
1292#define MISC_REG_AEU_ENABLE3_FUNC_1_OUT_1 0xa124
1293/* [RW 32] third 32b for enabling the output for close the gate nig. mapped
1294 as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP
1295 Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;
1296 [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
1297 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
1298 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
1299 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
1300 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
1301 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
1302 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
1303 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
1304 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
1305 attn1; */
1306#define MISC_REG_AEU_ENABLE3_NIG_0 0xa0f4
1307#define MISC_REG_AEU_ENABLE3_NIG_1 0xa194
1308/* [RW 32] third 32b for enabling the output for close the gate pxp. mapped
1309 as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP
1310 Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;
1311 [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
1312 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
1313 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
1314 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
1315 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
1316 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
1317 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
1318 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
1319 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
1320 attn1; */
1321#define MISC_REG_AEU_ENABLE3_PXP_0 0xa104
1322#define MISC_REG_AEU_ENABLE3_PXP_1 0xa1a4
1323/* [RW 32] fourth 32b for enabling the output for function 0 output0.mapped
1324 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1325 General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
1326 [7] General attn9; [8] General attn10; [9] General attn11; [10] General
1327 attn12; [11] General attn13; [12] General attn14; [13] General attn15;
1328 [14] General attn16; [15] General attn17; [16] General attn18; [17]
1329 General attn19; [18] General attn20; [19] General attn21; [20] Main power
1330 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
1331 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
1332 Latched timeout attention; [27] GRC Latched reserved access attention;
1333 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
1334 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
1335#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0 0xa078
1336#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_2 0xa098
1337#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_4 0xa0b8
1338#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_5 0xa0c8
1339#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_6 0xa0d8
1340#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_7 0xa0e8
1341/* [RW 32] fourth 32b for enabling the output for function 1 output0.mapped
1342 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1343 General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
1344 [7] General attn9; [8] General attn10; [9] General attn11; [10] General
1345 attn12; [11] General attn13; [12] General attn14; [13] General attn15;
1346 [14] General attn16; [15] General attn17; [16] General attn18; [17]
1347 General attn19; [18] General attn20; [19] General attn21; [20] Main power
1348 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
1349 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
1350 Latched timeout attention; [27] GRC Latched reserved access attention;
1351 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
1352 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
1353#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0 0xa118
1354#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_2 0xa138
1355#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_4 0xa158
1356#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_5 0xa168
1357#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_6 0xa178
1358#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_7 0xa188
1359/* [RW 32] fourth 32b for enabling the output for close the gate nig.mapped
1360 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1361 General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
1362 [7] General attn9; [8] General attn10; [9] General attn11; [10] General
1363 attn12; [11] General attn13; [12] General attn14; [13] General attn15;
1364 [14] General attn16; [15] General attn17; [16] General attn18; [17]
1365 General attn19; [18] General attn20; [19] General attn21; [20] Main power
1366 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
1367 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
1368 Latched timeout attention; [27] GRC Latched reserved access attention;
1369 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
1370 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
1371#define MISC_REG_AEU_ENABLE4_NIG_0 0xa0f8
1372#define MISC_REG_AEU_ENABLE4_NIG_1 0xa198
1373/* [RW 32] fourth 32b for enabling the output for close the gate pxp.mapped
1374 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1375 General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
1376 [7] General attn9; [8] General attn10; [9] General attn11; [10] General
1377 attn12; [11] General attn13; [12] General attn14; [13] General attn15;
1378 [14] General attn16; [15] General attn17; [16] General attn18; [17]
1379 General attn19; [18] General attn20; [19] General attn21; [20] Main power
1380 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
1381 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
1382 Latched timeout attention; [27] GRC Latched reserved access attention;
1383 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
1384 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
1385#define MISC_REG_AEU_ENABLE4_PXP_0 0xa108
1386#define MISC_REG_AEU_ENABLE4_PXP_1 0xa1a8
1387/* [RW 1] set/clr general attention 0; this will set/clr bit 94 in the aeu
1388 128 bit vector */
1389#define MISC_REG_AEU_GENERAL_ATTN_0 0xa000
1390#define MISC_REG_AEU_GENERAL_ATTN_1 0xa004
1391#define MISC_REG_AEU_GENERAL_ATTN_10 0xa028
1392#define MISC_REG_AEU_GENERAL_ATTN_11 0xa02c
1393#define MISC_REG_AEU_GENERAL_ATTN_12 0xa030
1394#define MISC_REG_AEU_GENERAL_ATTN_2 0xa008
1395#define MISC_REG_AEU_GENERAL_ATTN_3 0xa00c
1396#define MISC_REG_AEU_GENERAL_ATTN_4 0xa010
1397#define MISC_REG_AEU_GENERAL_ATTN_5 0xa014
1398#define MISC_REG_AEU_GENERAL_ATTN_6 0xa018
1399#define MISC_REG_AEU_GENERAL_ATTN_7 0xa01c
1400#define MISC_REG_AEU_GENERAL_ATTN_8 0xa020
1401#define MISC_REG_AEU_GENERAL_ATTN_9 0xa024
1402#define MISC_REG_AEU_GENERAL_MASK 0xa61c
1403/* [RW 32] first 32b for inverting the input for function 0; for each bit:
1404 0= do not invert; 1= invert; mapped as follows: [0] NIG attention for
1405 function0; [1] NIG attention for function1; [2] GPIO1 mcp; [3] GPIO2 mcp;
1406 [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1; [7] GPIO2 function 1;
1407 [8] GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
1408 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
1409 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
1410 SPIO4; [15] SPIO5; [16] MSI/X indication for mcp; [17] MSI/X indication
1411 for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; [20] PRS
1412 Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] SRC Hw
1413 interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] TCM
1414 Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] TSEMI
1415 Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
1416#define MISC_REG_AEU_INVERTER_1_FUNC_0 0xa22c
1417#define MISC_REG_AEU_INVERTER_1_FUNC_1 0xa23c
1418/* [RW 32] second 32b for inverting the input for function 0; for each bit:
1419 0= do not invert; 1= invert. mapped as follows: [0] PBClient Parity
1420 error; [1] PBClient Hw interrupt; [2] QM Parity error; [3] QM Hw
1421 interrupt; [4] Timers Parity error; [5] Timers Hw interrupt; [6] XSDM
1422 Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9] XCM Hw
1423 interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12]
1424 DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity
1425 error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux
1426 PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt;
1427 [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error;
1428 [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt;
1429 [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error;
1430 [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt; */
1431#define MISC_REG_AEU_INVERTER_2_FUNC_0 0xa230
1432#define MISC_REG_AEU_INVERTER_2_FUNC_1 0xa240
1433/* [RW 10] [7:0] = mask 8 attention output signals toward IGU function0;
1434 [9:8] = raserved. Zero = mask; one = unmask */
1435#define MISC_REG_AEU_MASK_ATTN_FUNC_0 0xa060
1436#define MISC_REG_AEU_MASK_ATTN_FUNC_1 0xa064
1437/* [RW 1] If set a system kill occurred */
1438#define MISC_REG_AEU_SYS_KILL_OCCURRED 0xa610
1439/* [RW 32] Represent the status of the input vector to the AEU when a system
1440 kill occurred. The register is reset in por reset. Mapped as follows: [0]
1441 NIG attention for function0; [1] NIG attention for function1; [2] GPIO1
1442 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1;
1443 [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10]
1444 PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event
1445 function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP
1446 Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for
1447 mcp; [17] MSI/X indication for function 1; [18] BRB Parity error; [19]
1448 BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC
1449 Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw
1450 interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI
1451 Parity error; [29] TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw
1452 interrupt; */
1453#define MISC_REG_AEU_SYS_KILL_STATUS_0 0xa600
1454#define MISC_REG_AEU_SYS_KILL_STATUS_1 0xa604
1455#define MISC_REG_AEU_SYS_KILL_STATUS_2 0xa608
1456#define MISC_REG_AEU_SYS_KILL_STATUS_3 0xa60c
1457/* [R 4] This field indicates the type of the device. '0' - 2 Ports; '1' - 1
1458 Port. */
1459#define MISC_REG_BOND_ID 0xa400
1460/* [R 8] These bits indicate the metal revision of the chip. This value
1461 starts at 0x00 for each all-layer tape-out and increments by one for each
1462 tape-out. */
1463#define MISC_REG_CHIP_METAL 0xa404
1464/* [R 16] These bits indicate the part number for the chip. */
1465#define MISC_REG_CHIP_NUM 0xa408
1466/* [R 4] These bits indicate the base revision of the chip. This value
1467 starts at 0x0 for the A0 tape-out and increments by one for each
1468 all-layer tape-out. */
1469#define MISC_REG_CHIP_REV 0xa40c
1470/* [RW 32] The following driver registers(1...16) represent 16 drivers and
1471 32 clients. Each client can be controlled by one driver only. One in each
1472 bit represent that this driver control the appropriate client (Ex: bit 5
1473 is set means this driver control client number 5). addr1 = set; addr0 =
1474 clear; read from both addresses will give the same result = status. write
1475 to address 1 will set a request to control all the clients that their
1476 appropriate bit (in the write command) is set. if the client is free (the
1477 appropriate bit in all the other drivers is clear) one will be written to
1478 that driver register; if the client isn't free the bit will remain zero.
1479 if the appropriate bit is set (the driver request to gain control on a
1480 client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW
1481 interrupt will be asserted). write to address 0 will set a request to
1482 free all the clients that their appropriate bit (in the write command) is
1483 set. if the appropriate bit is clear (the driver request to free a client
1484 it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will
1485 be asserted). */
1486#define MISC_REG_DRIVER_CONTROL_1 0xa510
1487#define MISC_REG_DRIVER_CONTROL_7 0xa3c8
1488/* [RW 1] e1hmf for WOL. If clr WOL signal o the PXP will be send on bit 0
1489 only. */
1490#define MISC_REG_E1HMF_MODE 0xa5f8
1491/* [R 1] Status of four port mode path swap input pin. */
1492#define MISC_REG_FOUR_PORT_PATH_SWAP 0xa75c
1493/* [RW 2] 4 port path swap overwrite.[0] - Overwrite control; if it is 0 -
1494 the path_swap output is equal to 4 port mode path swap input pin; if it
1495 is 1 - the path_swap output is equal to bit[1] of this register; [1] -
1496 Overwrite value. If bit[0] of this register is 1 this is the value that
1497 receives the path_swap output. Reset on Hard reset. */
1498#define MISC_REG_FOUR_PORT_PATH_SWAP_OVWR 0xa738
1499/* [R 1] Status of 4 port mode port swap input pin. */
1500#define MISC_REG_FOUR_PORT_PORT_SWAP 0xa754
1501/* [RW 2] 4 port port swap overwrite.[0] - Overwrite control; if it is 0 -
1502 the port_swap output is equal to 4 port mode port swap input pin; if it
1503 is 1 - the port_swap output is equal to bit[1] of this register; [1] -
1504 Overwrite value. If bit[0] of this register is 1 this is the value that
1505 receives the port_swap output. Reset on Hard reset. */
1506#define MISC_REG_FOUR_PORT_PORT_SWAP_OVWR 0xa734
1507/* [RW 32] Debug only: spare RW register reset by core reset */
1508#define MISC_REG_GENERIC_CR_0 0xa460
1509#define MISC_REG_GENERIC_CR_1 0xa464
1510/* [RW 32] Debug only: spare RW register reset by por reset */
1511#define MISC_REG_GENERIC_POR_1 0xa474
1512/* [RW 32] Bit[0]: EPIO MODE SEL: Setting this bit to 1 will allow SW/FW to
1513 use all of the 32 Extended GPIO pins. Without setting this bit; an EPIO
1514 can not be configured as an output. Each output has its output enable in
1515 the MCP register space; but this bit needs to be set to make use of that.
1516 Bit[3:1] spare. Bit[4]: WCVTMON_PWRDN: Powerdown for Warpcore VTMON. When
1517 set to 1 - Powerdown. Bit[5]: WCVTMON_RESETB: Reset for Warpcore VTMON.
1518 When set to 0 - vTMON is in reset. Bit[6]: setting this bit will change
1519 the i/o to an output and will drive the TimeSync output. Bit[31:7]:
1520 spare. Global register. Reset by hard reset. */
1521#define MISC_REG_GEN_PURP_HWG 0xa9a0
1522/* [RW 32] GPIO. [31-28] FLOAT port 0; [27-24] FLOAT port 0; When any of
1523 these bits is written as a '1'; the corresponding SPIO bit will turn off
1524 it's drivers and become an input. This is the reset state of all GPIO
1525 pins. The read value of these bits will be a '1' if that last command
1526 (#SET; #CLR; or #FLOAT) for this bit was a #FLOAT. (reset value 0xff).
1527 [23-20] CLR port 1; 19-16] CLR port 0; When any of these bits is written
1528 as a '1'; the corresponding GPIO bit will drive low. The read value of
1529 these bits will be a '1' if that last command (#SET; #CLR; or #FLOAT) for
1530 this bit was a #CLR. (reset value 0). [15-12] SET port 1; 11-8] port 0;
1531 SET When any of these bits is written as a '1'; the corresponding GPIO
1532 bit will drive high (if it has that capability). The read value of these
1533 bits will be a '1' if that last command (#SET; #CLR; or #FLOAT) for this
1534 bit was a #SET. (reset value 0). [7-4] VALUE port 1; [3-0] VALUE port 0;
1535 RO; These bits indicate the read value of each of the eight GPIO pins.
1536 This is the result value of the pin; not the drive value. Writing these
1537 bits will have not effect. */
1538#define MISC_REG_GPIO 0xa490
1539/* [RW 8] These bits enable the GPIO_INTs to signals event to the
1540 IGU/MCP.according to the following map: [0] p0_gpio_0; [1] p0_gpio_1; [2]
1541 p0_gpio_2; [3] p0_gpio_3; [4] p1_gpio_0; [5] p1_gpio_1; [6] p1_gpio_2;
1542 [7] p1_gpio_3; */
1543#define MISC_REG_GPIO_EVENT_EN 0xa2bc
1544/* [RW 32] GPIO INT. [31-28] OLD_CLR port1; [27-24] OLD_CLR port0; Writing a
1545 '1' to these bit clears the corresponding bit in the #OLD_VALUE register.
1546 This will acknowledge an interrupt on the falling edge of corresponding
1547 GPIO input (reset value 0). [23-16] OLD_SET [23-16] port1; OLD_SET port0;
1548 Writing a '1' to these bit sets the corresponding bit in the #OLD_VALUE
1549 register. This will acknowledge an interrupt on the rising edge of
1550 corresponding SPIO input (reset value 0). [15-12] OLD_VALUE [11-8] port1;
1551 OLD_VALUE port0; RO; These bits indicate the old value of the GPIO input
1552 value. When the ~INT_STATE bit is set; this bit indicates the OLD value
1553 of the pin such that if ~INT_STATE is set and this bit is '0'; then the
1554 interrupt is due to a low to high edge. If ~INT_STATE is set and this bit
1555 is '1'; then the interrupt is due to a high to low edge (reset value 0).
1556 [7-4] INT_STATE port1; [3-0] INT_STATE RO port0; These bits indicate the
1557 current GPIO interrupt state for each GPIO pin. This bit is cleared when
1558 the appropriate #OLD_SET or #OLD_CLR command bit is written. This bit is
1559 set when the GPIO input does not match the current value in #OLD_VALUE
1560 (reset value 0). */
1561#define MISC_REG_GPIO_INT 0xa494
1562/* [R 28] this field hold the last information that caused reserved
1563 attention. bits [19:0] - address; [22:20] function; [23] reserved;
1564 [27:24] the master that caused the attention - according to the following
1565 encodeing:1 = pxp; 2 = mcp; 3 = usdm; 4 = tsdm; 5 = xsdm; 6 = csdm; 7 =
1566 dbu; 8 = dmae */
1567#define MISC_REG_GRC_RSV_ATTN 0xa3c0
1568/* [R 28] this field hold the last information that caused timeout
1569 attention. bits [19:0] - address; [22:20] function; [23] reserved;
1570 [27:24] the master that caused the attention - according to the following
1571 encodeing:1 = pxp; 2 = mcp; 3 = usdm; 4 = tsdm; 5 = xsdm; 6 = csdm; 7 =
1572 dbu; 8 = dmae */
1573#define MISC_REG_GRC_TIMEOUT_ATTN 0xa3c4
1574/* [RW 1] Setting this bit enables a timer in the GRC block to timeout any
1575 access that does not finish within
1576 ~misc_registers_grc_timout_val.grc_timeout_val cycles. When this bit is
1577 cleared; this timeout is disabled. If this timeout occurs; the GRC shall
1578 assert it attention output. */
1579#define MISC_REG_GRC_TIMEOUT_EN 0xa280
1580/* [RW 28] 28 LSB of LCPLL first register; reset val = 521. inside order of
1581 the bits is: [2:0] OAC reset value 001) CML output buffer bias control;
1582 111 for +40%; 011 for +20%; 001 for 0%; 000 for -20%. [5:3] Icp_ctrl
1583 (reset value 001) Charge pump current control; 111 for 720u; 011 for
1584 600u; 001 for 480u and 000 for 360u. [7:6] Bias_ctrl (reset value 00)
1585 Global bias control; When bit 7 is high bias current will be 10 0gh; When
1586 bit 6 is high bias will be 100w; Valid values are 00; 10; 01. [10:8]
1587 Pll_observe (reset value 010) Bits to control observability. bit 10 is
1588 for test bias; bit 9 is for test CK; bit 8 is test Vc. [12:11] Vth_ctrl
1589 (reset value 00) Comparator threshold control. 00 for 0.6V; 01 for 0.54V
1590 and 10 for 0.66V. [13] pllSeqStart (reset value 0) Enables VCO tuning
1591 sequencer: 1= sequencer disabled; 0= sequencer enabled (inverted
1592 internally). [14] reserved (reset value 0) Reset for VCO sequencer is
1593 connected to RESET input directly. [15] capRetry_en (reset value 0)
1594 enable retry on cap search failure (inverted). [16] freqMonitor_e (reset
1595 value 0) bit to continuously monitor vco freq (inverted). [17]
1596 freqDetRestart_en (reset value 0) bit to enable restart when not freq
1597 locked (inverted). [18] freqDetRetry_en (reset value 0) bit to enable
1598 retry on freq det failure(inverted). [19] pllForceFdone_en (reset value
1599 0) bit to enable pllForceFdone & pllForceFpass into pllSeq. [20]
1600 pllForceFdone (reset value 0) bit to force freqDone. [21] pllForceFpass
1601 (reset value 0) bit to force freqPass. [22] pllForceDone_en (reset value
1602 0) bit to enable pllForceCapDone. [23] pllForceCapDone (reset value 0)
1603 bit to force capDone. [24] pllForceCapPass_en (reset value 0) bit to
1604 enable pllForceCapPass. [25] pllForceCapPass (reset value 0) bit to force
1605 capPass. [26] capRestart (reset value 0) bit to force cap sequencer to
1606 restart. [27] capSelectM_en (reset value 0) bit to enable cap select
1607 register bits. */
1608#define MISC_REG_LCPLL_CTRL_1 0xa2a4
1609#define MISC_REG_LCPLL_CTRL_REG_2 0xa2a8
1610/* [RW 4] Interrupt mask register #0 read/write */
1611#define MISC_REG_MISC_INT_MASK 0xa388
1612/* [RW 1] Parity mask register #0 read/write */
1613#define MISC_REG_MISC_PRTY_MASK 0xa398
1614/* [R 1] Parity register #0 read */
1615#define MISC_REG_MISC_PRTY_STS 0xa38c
1616/* [RC 1] Parity register #0 read clear */
1617#define MISC_REG_MISC_PRTY_STS_CLR 0xa390
1618#define MISC_REG_NIG_WOL_P0 0xa270
1619#define MISC_REG_NIG_WOL_P1 0xa274
1620/* [R 1] If set indicate that the pcie_rst_b was asserted without perst
1621 assertion */
1622#define MISC_REG_PCIE_HOT_RESET 0xa618
1623/* [RW 32] 32 LSB of storm PLL first register; reset val = 0x 071d2911.
1624 inside order of the bits is: [0] P1 divider[0] (reset value 1); [1] P1
1625 divider[1] (reset value 0); [2] P1 divider[2] (reset value 0); [3] P1
1626 divider[3] (reset value 0); [4] P2 divider[0] (reset value 1); [5] P2
1627 divider[1] (reset value 0); [6] P2 divider[2] (reset value 0); [7] P2
1628 divider[3] (reset value 0); [8] ph_det_dis (reset value 1); [9]
1629 freq_det_dis (reset value 0); [10] Icpx[0] (reset value 0); [11] Icpx[1]
1630 (reset value 1); [12] Icpx[2] (reset value 0); [13] Icpx[3] (reset value
1631 1); [14] Icpx[4] (reset value 0); [15] Icpx[5] (reset value 0); [16]
1632 Rx[0] (reset value 1); [17] Rx[1] (reset value 0); [18] vc_en (reset
1633 value 1); [19] vco_rng[0] (reset value 1); [20] vco_rng[1] (reset value
1634 1); [21] Kvco_xf[0] (reset value 0); [22] Kvco_xf[1] (reset value 0);
1635 [23] Kvco_xf[2] (reset value 0); [24] Kvco_xs[0] (reset value 1); [25]
1636 Kvco_xs[1] (reset value 1); [26] Kvco_xs[2] (reset value 1); [27]
1637 testd_en (reset value 0); [28] testd_sel[0] (reset value 0); [29]
1638 testd_sel[1] (reset value 0); [30] testd_sel[2] (reset value 0); [31]
1639 testa_en (reset value 0); */
1640#define MISC_REG_PLL_STORM_CTRL_1 0xa294
1641#define MISC_REG_PLL_STORM_CTRL_2 0xa298
1642#define MISC_REG_PLL_STORM_CTRL_3 0xa29c
1643#define MISC_REG_PLL_STORM_CTRL_4 0xa2a0
1644/* [R 1] Status of 4 port mode enable input pin. */
1645#define MISC_REG_PORT4MODE_EN 0xa750
1646/* [RW 2] 4 port mode enable overwrite.[0] - Overwrite control; if it is 0 -
1647 * the port4mode_en output is equal to 4 port mode input pin; if it is 1 -
1648 * the port4mode_en output is equal to bit[1] of this register; [1] -
1649 * Overwrite value. If bit[0] of this register is 1 this is the value that
1650 * receives the port4mode_en output . */
1651#define MISC_REG_PORT4MODE_EN_OVWR 0xa720
1652/* [RW 32] reset reg#2; rite/read one = the specific block is out of reset;
1653 write/read zero = the specific block is in reset; addr 0-wr- the write
1654 value will be written to the register; addr 1-set - one will be written
1655 to all the bits that have the value of one in the data written (bits that
1656 have the value of zero will not be change) ; addr 2-clear - zero will be
1657 written to all the bits that have the value of one in the data written
1658 (bits that have the value of zero will not be change); addr 3-ignore;
1659 read ignore from all addr except addr 00; inside order of the bits is:
1660 [0] rst_bmac0; [1] rst_bmac1; [2] rst_emac0; [3] rst_emac1; [4] rst_grc;
1661 [5] rst_mcp_n_reset_reg_hard_core; [6] rst_ mcp_n_hard_core_rst_b; [7]
1662 rst_ mcp_n_reset_cmn_cpu; [8] rst_ mcp_n_reset_cmn_core; [9] rst_rbcn;
1663 [10] rst_dbg; [11] rst_misc_core; [12] rst_dbue (UART); [13]
1664 Pci_resetmdio_n; [14] rst_emac0_hard_core; [15] rst_emac1_hard_core; 16]
1665 rst_pxp_rq_rd_wr; 31:17] reserved */
1666#define MISC_REG_RESET_REG_2 0xa590
1667/* [RW 20] 20 bit GRC address where the scratch-pad of the MCP that is
1668 shared with the driver resides */
1669#define MISC_REG_SHARED_MEM_ADDR 0xa2b4
1670/* [RW 32] SPIO. [31-24] FLOAT When any of these bits is written as a '1';
1671 the corresponding SPIO bit will turn off it's drivers and become an
1672 input. This is the reset state of all SPIO pins. The read value of these
1673 bits will be a '1' if that last command (#SET; #CL; or #FLOAT) for this
1674 bit was a #FLOAT. (reset value 0xff). [23-16] CLR When any of these bits
1675 is written as a '1'; the corresponding SPIO bit will drive low. The read
1676 value of these bits will be a '1' if that last command (#SET; #CLR; or
1677#FLOAT) for this bit was a #CLR. (reset value 0). [15-8] SET When any of
1678 these bits is written as a '1'; the corresponding SPIO bit will drive
1679 high (if it has that capability). The read value of these bits will be a
1680 '1' if that last command (#SET; #CLR; or #FLOAT) for this bit was a #SET.
1681 (reset value 0). [7-0] VALUE RO; These bits indicate the read value of
1682 each of the eight SPIO pins. This is the result value of the pin; not the
1683 drive value. Writing these bits will have not effect. Each 8 bits field
1684 is divided as follows: [0] VAUX Enable; when pulsed low; enables supply
1685 from VAUX. (This is an output pin only; the FLOAT field is not applicable
1686 for this pin); [1] VAUX Disable; when pulsed low; disables supply form
1687 VAUX. (This is an output pin only; FLOAT field is not applicable for this
1688 pin); [2] SEL_VAUX_B - Control to power switching logic. Drive low to
1689 select VAUX supply. (This is an output pin only; it is not controlled by
1690 the SET and CLR fields; it is controlled by the Main Power SM; the FLOAT
1691 field is not applicable for this pin; only the VALUE fields is relevant -
1692 it reflects the output value); [3] port swap [4] spio_4; [5] spio_5; [6]
1693 Bit 0 of UMP device ID select; read by UMP firmware; [7] Bit 1 of UMP
1694 device ID select; read by UMP firmware. */
1695#define MISC_REG_SPIO 0xa4fc
1696/* [RW 8] These bits enable the SPIO_INTs to signals event to the IGU/MC.
1697 according to the following map: [3:0] reserved; [4] spio_4 [5] spio_5;
1698 [7:0] reserved */
1699#define MISC_REG_SPIO_EVENT_EN 0xa2b8
1700/* [RW 32] SPIO INT. [31-24] OLD_CLR Writing a '1' to these bit clears the
1701 corresponding bit in the #OLD_VALUE register. This will acknowledge an
1702 interrupt on the falling edge of corresponding SPIO input (reset value
1703 0). [23-16] OLD_SET Writing a '1' to these bit sets the corresponding bit
1704 in the #OLD_VALUE register. This will acknowledge an interrupt on the
1705 rising edge of corresponding SPIO input (reset value 0). [15-8] OLD_VALUE
1706 RO; These bits indicate the old value of the SPIO input value. When the
1707 ~INT_STATE bit is set; this bit indicates the OLD value of the pin such
1708 that if ~INT_STATE is set and this bit is '0'; then the interrupt is due
1709 to a low to high edge. If ~INT_STATE is set and this bit is '1'; then the
1710 interrupt is due to a high to low edge (reset value 0). [7-0] INT_STATE
1711 RO; These bits indicate the current SPIO interrupt state for each SPIO
1712 pin. This bit is cleared when the appropriate #OLD_SET or #OLD_CLR
1713 command bit is written. This bit is set when the SPIO input does not
1714 match the current value in #OLD_VALUE (reset value 0). */
1715#define MISC_REG_SPIO_INT 0xa500
1716/* [RW 32] reload value for counter 4 if reload; the value will be reload if
1717 the counter reached zero and the reload bit
1718 (~misc_registers_sw_timer_cfg_4.sw_timer_cfg_4[1] ) is set */
1719#define MISC_REG_SW_TIMER_RELOAD_VAL_4 0xa2fc
1720/* [RW 32] the value of the counter for sw timers1-8. there are 8 addresses
1721 in this register. address 0 - timer 1; address 1 - timer 2, ... address 7 -
1722 timer 8 */
1723#define MISC_REG_SW_TIMER_VAL 0xa5c0
1724/* [R 1] Status of two port mode path swap input pin. */
1725#define MISC_REG_TWO_PORT_PATH_SWAP 0xa758
1726/* [RW 2] 2 port swap overwrite.[0] - Overwrite control; if it is 0 - the
1727 path_swap output is equal to 2 port mode path swap input pin; if it is 1
1728 - the path_swap output is equal to bit[1] of this register; [1] -
1729 Overwrite value. If bit[0] of this register is 1 this is the value that
1730 receives the path_swap output. Reset on Hard reset. */
1731#define MISC_REG_TWO_PORT_PATH_SWAP_OVWR 0xa72c
1732/* [RW 1] Set by the MCP to remember if one or more of the drivers is/are
1733 loaded; 0-prepare; -unprepare */
1734#define MISC_REG_UNPREPARED 0xa424
1735#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_BRCST (0x1<<0)
1736#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_MLCST (0x1<<1)
1737#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_NO_VLAN (0x1<<4)
1738#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_UNCST (0x1<<2)
1739#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_VLAN (0x1<<3)
1740/* [RW 5] MDIO PHY Address. The WC uses this address to determine whether or
1741 * not it is the recipient of the message on the MDIO interface. The value
1742 * is compared to the value on ctrl_md_devad. Drives output
1743 * misc_xgxs0_phy_addr. Global register. */
1744#define MISC_REG_WC0_CTRL_PHY_ADDR 0xa9cc
1745/* [RW 2] XMAC Core port mode. Indicates the number of ports on the system
1746 side. This should be less than or equal to phy_port_mode; if some of the
1747 ports are not used. This enables reduction of frequency on the core side.
1748 This is a strap input for the XMAC_MP core. 00 - Single Port Mode; 01 -
1749 Dual Port Mode; 10 - Tri Port Mode; 11 - Quad Port Mode. This is a strap
1750 input for the XMAC_MP core; and should be changed only while reset is
1751 held low. Reset on Hard reset. */
1752#define MISC_REG_XMAC_CORE_PORT_MODE 0xa964
1753/* [RW 2] XMAC PHY port mode. Indicates the number of ports on the Warp
1754 Core. This is a strap input for the XMAC_MP core. 00 - Single Port Mode;
1755 01 - Dual Port Mode; 1x - Quad Port Mode; This is a strap input for the
1756 XMAC_MP core; and should be changed only while reset is held low. Reset
1757 on Hard reset. */
1758#define MISC_REG_XMAC_PHY_PORT_MODE 0xa960
1759/* [RW 32] 1 [47] Packet Size = 64 Write to this register write bits 31:0.
1760 * Reads from this register will clear bits 31:0. */
1761#define MSTAT_REG_RX_STAT_GR64_LO 0x200
1762/* [RW 32] 1 [00] Tx Good Packet Count Write to this register write bits
1763 * 31:0. Reads from this register will clear bits 31:0. */
1764#define MSTAT_REG_TX_STAT_GTXPOK_LO 0
1765#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_BRCST (0x1<<0)
1766#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_MLCST (0x1<<1)
1767#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_NO_VLAN (0x1<<4)
1768#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_UNCST (0x1<<2)
1769#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_VLAN (0x1<<3)
1770#define NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN (0x1<<0)
1771#define NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN (0x1<<0)
1772#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT (0x1<<0)
1773#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS (0x1<<9)
1774#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G (0x1<<15)
1775#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS (0xf<<18)
1776/* [RW 1] Input enable for RX_BMAC0 IF */
1777#define NIG_REG_BMAC0_IN_EN 0x100ac
1778/* [RW 1] output enable for TX_BMAC0 IF */
1779#define NIG_REG_BMAC0_OUT_EN 0x100e0
1780/* [RW 1] output enable for TX BMAC pause port 0 IF */
1781#define NIG_REG_BMAC0_PAUSE_OUT_EN 0x10110
1782/* [RW 1] output enable for RX_BMAC0_REGS IF */
1783#define NIG_REG_BMAC0_REGS_OUT_EN 0x100e8
1784/* [RW 1] output enable for RX BRB1 port0 IF */
1785#define NIG_REG_BRB0_OUT_EN 0x100f8
1786/* [RW 1] Input enable for TX BRB1 pause port 0 IF */
1787#define NIG_REG_BRB0_PAUSE_IN_EN 0x100c4
1788/* [RW 1] output enable for RX BRB1 port1 IF */
1789#define NIG_REG_BRB1_OUT_EN 0x100fc
1790/* [RW 1] Input enable for TX BRB1 pause port 1 IF */
1791#define NIG_REG_BRB1_PAUSE_IN_EN 0x100c8
1792/* [RW 1] output enable for RX BRB1 LP IF */
1793#define NIG_REG_BRB_LB_OUT_EN 0x10100
1794/* [WB_W 82] Debug packet to LP from RBC; Data spelling:[63:0] data; 64]
1795 error; [67:65]eop_bvalid; [68]eop; [69]sop; [70]port_id; 71]flush;
1796 72:73]-vnic_num; 81:74]-sideband_info */
1797#define NIG_REG_DEBUG_PACKET_LB 0x10800
1798/* [RW 1] Input enable for TX Debug packet */
1799#define NIG_REG_EGRESS_DEBUG_IN_EN 0x100dc
1800/* [RW 1] If 1 - egress drain mode for port0 is active. In this mode all
1801 packets from PBFare not forwarded to the MAC and just deleted from FIFO.
1802 First packet may be deleted from the middle. And last packet will be
1803 always deleted till the end. */
1804#define NIG_REG_EGRESS_DRAIN0_MODE 0x10060
1805/* [RW 1] Output enable to EMAC0 */
1806#define NIG_REG_EGRESS_EMAC0_OUT_EN 0x10120
1807/* [RW 1] MAC configuration for packets of port0. If 1 - all packet outputs
1808 to emac for port0; other way to bmac for port0 */
1809#define NIG_REG_EGRESS_EMAC0_PORT 0x10058
1810/* [RW 1] Input enable for TX PBF user packet port0 IF */
1811#define NIG_REG_EGRESS_PBF0_IN_EN 0x100cc
1812/* [RW 1] Input enable for TX PBF user packet port1 IF */
1813#define NIG_REG_EGRESS_PBF1_IN_EN 0x100d0
1814/* [RW 1] Input enable for TX UMP management packet port0 IF */
1815#define NIG_REG_EGRESS_UMP0_IN_EN 0x100d4
1816/* [RW 1] Input enable for RX_EMAC0 IF */
1817#define NIG_REG_EMAC0_IN_EN 0x100a4
1818/* [RW 1] output enable for TX EMAC pause port 0 IF */
1819#define NIG_REG_EMAC0_PAUSE_OUT_EN 0x10118
1820/* [R 1] status from emac0. This bit is set when MDINT from either the
1821 EXT_MDINT pin or from the Copper PHY is driven low. This condition must
1822 be cleared in the attached PHY device that is driving the MINT pin. */
1823#define NIG_REG_EMAC0_STATUS_MISC_MI_INT 0x10494
1824/* [WB 48] This address space contains BMAC0 registers. The BMAC registers
1825 are described in appendix A. In order to access the BMAC0 registers; the
1826 base address; NIG_REGISTERS_INGRESS_BMAC0_MEM; Offset: 0x10c00; should be
1827 added to each BMAC register offset */
1828#define NIG_REG_INGRESS_BMAC0_MEM 0x10c00
1829/* [WB 48] This address space contains BMAC1 registers. The BMAC registers
1830 are described in appendix A. In order to access the BMAC0 registers; the
1831 base address; NIG_REGISTERS_INGRESS_BMAC1_MEM; Offset: 0x11000; should be
1832 added to each BMAC register offset */
1833#define NIG_REG_INGRESS_BMAC1_MEM 0x11000
1834/* [R 1] FIFO empty in EOP descriptor FIFO of LP in NIG_RX_EOP */
1835#define NIG_REG_INGRESS_EOP_LB_EMPTY 0x104e0
1836/* [RW 17] Debug only. RX_EOP_DSCR_lb_FIFO in NIG_RX_EOP. Data
1837 packet_length[13:0]; mac_error[14]; trunc_error[15]; parity[16] */
1838#define NIG_REG_INGRESS_EOP_LB_FIFO 0x104e4
1839/* [RW 27] 0 - must be active for Everest A0; 1- for Everest B0 when latch
1840 logic for interrupts must be used. Enable per bit of interrupt of
1841 ~latch_status.latch_status */
1842#define NIG_REG_LATCH_BC_0 0x16210
1843/* [RW 27] Latch for each interrupt from Unicore.b[0]
1844 status_emac0_misc_mi_int; b[1] status_emac0_misc_mi_complete;
1845 b[2]status_emac0_misc_cfg_change; b[3]status_emac0_misc_link_status;
1846 b[4]status_emac0_misc_link_change; b[5]status_emac0_misc_attn;
1847 b[6]status_serdes0_mac_crs; b[7]status_serdes0_autoneg_complete;
1848 b[8]status_serdes0_fiber_rxact; b[9]status_serdes0_link_status;
1849 b[10]status_serdes0_mr_page_rx; b[11]status_serdes0_cl73_an_complete;
1850 b[12]status_serdes0_cl73_mr_page_rx; b[13]status_serdes0_rx_sigdet;
1851 b[14]status_xgxs0_remotemdioreq; b[15]status_xgxs0_link10g;
1852 b[16]status_xgxs0_autoneg_complete; b[17]status_xgxs0_fiber_rxact;
1853 b[21:18]status_xgxs0_link_status; b[22]status_xgxs0_mr_page_rx;
1854 b[23]status_xgxs0_cl73_an_complete; b[24]status_xgxs0_cl73_mr_page_rx;
1855 b[25]status_xgxs0_rx_sigdet; b[26]status_xgxs0_mac_crs */
1856#define NIG_REG_LATCH_STATUS_0 0x18000
1857/* [RW 1] led 10g for port 0 */
1858#define NIG_REG_LED_10G_P0 0x10320
1859/* [RW 1] led 10g for port 1 */
1860#define NIG_REG_LED_10G_P1 0x10324
1861/* [RW 1] Port0: This bit is set to enable the use of the
1862 ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 field
1863 defined below. If this bit is cleared; then the blink rate will be about
1864 8Hz. */
1865#define NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 0x10318
1866/* [RW 12] Port0: Specifies the period of each blink cycle (on + off) for
1867 Traffic LED in milliseconds. Must be a non-zero value. This 12-bit field
1868 is reset to 0x080; giving a default blink period of approximately 8Hz. */
1869#define NIG_REG_LED_CONTROL_BLINK_RATE_P0 0x10310
1870/* [RW 1] Port0: If set along with the
1871 ~nig_registers_led_control_override_traffic_p0.led_control_override_traffic_p0
1872 bit and ~nig_registers_led_control_traffic_p0.led_control_traffic_p0 LED
1873 bit; the Traffic LED will blink with the blink rate specified in
1874 ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 and
1875 ~nig_registers_led_control_blink_rate_ena_p0.led_control_blink_rate_ena_p0
1876 fields. */
1877#define NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 0x10308
1878/* [RW 1] Port0: If set overrides hardware control of the Traffic LED. The
1879 Traffic LED will then be controlled via bit ~nig_registers_
1880 led_control_traffic_p0.led_control_traffic_p0 and bit
1881 ~nig_registers_led_control_blink_traffic_p0.led_control_blink_traffic_p0 */
1882#define NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 0x102f8
1883/* [RW 1] Port0: If set along with the led_control_override_trafic_p0 bit;
1884 turns on the Traffic LED. If the led_control_blink_traffic_p0 bit is also
1885 set; the LED will blink with blink rate specified in
1886 ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 and
1887 ~nig_regsters_led_control_blink_rate_ena_p0.led_control_blink_rate_ena_p0
1888 fields. */
1889#define NIG_REG_LED_CONTROL_TRAFFIC_P0 0x10300
1890/* [RW 4] led mode for port0: 0 MAC; 1-3 PHY1; 4 MAC2; 5-7 PHY4; 8-MAC3;
1891 9-11PHY7; 12 MAC4; 13-15 PHY10; */
1892#define NIG_REG_LED_MODE_P0 0x102f0
1893/* [RW 3] for port0 enable for llfc ppp and pause. b0 - brb1 enable; b1-
1894 tsdm enable; b2- usdm enable */
1895#define NIG_REG_LLFC_EGRESS_SRC_ENABLE_0 0x16070
1896#define NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 0x16074
1897/* [RW 1] SAFC enable for port0. This register may get 1 only when
1898 ~ppp_enable.ppp_enable = 0 and pause_enable.pause_enable =0 for the same
1899 port */
1900#define NIG_REG_LLFC_ENABLE_0 0x16208
1901#define NIG_REG_LLFC_ENABLE_1 0x1620c
1902/* [RW 16] classes are high-priority for port0 */
1903#define NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0 0x16058
1904#define NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 0x1605c
1905/* [RW 16] classes are low-priority for port0 */
1906#define NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0 0x16060
1907#define NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 0x16064
1908/* [RW 1] Output enable of message to LLFC BMAC IF for port0 */
1909#define NIG_REG_LLFC_OUT_EN_0 0x160c8
1910#define NIG_REG_LLFC_OUT_EN_1 0x160cc
1911#define NIG_REG_LLH0_ACPI_PAT_0_CRC 0x1015c
1912#define NIG_REG_LLH0_ACPI_PAT_6_LEN 0x10154
1913#define NIG_REG_LLH0_BRB1_DRV_MASK 0x10244
1914#define NIG_REG_LLH0_BRB1_DRV_MASK_MF 0x16048
1915/* [RW 1] send to BRB1 if no match on any of RMP rules. */
1916#define NIG_REG_LLH0_BRB1_NOT_MCP 0x1025c
1917/* [RW 2] Determine the classification participants. 0: no classification.1:
1918 classification upon VLAN id. 2: classification upon MAC address. 3:
1919 classification upon both VLAN id & MAC addr. */
1920#define NIG_REG_LLH0_CLS_TYPE 0x16080
1921/* [RW 32] cm header for llh0 */
1922#define NIG_REG_LLH0_CM_HEADER 0x1007c
1923#define NIG_REG_LLH0_DEST_IP_0_1 0x101dc
1924#define NIG_REG_LLH0_DEST_MAC_0_0 0x101c0
1925/* [RW 16] destination TCP address 1. The LLH will look for this address in
1926 all incoming packets. */
1927#define NIG_REG_LLH0_DEST_TCP_0 0x10220
1928/* [RW 16] destination UDP address 1 The LLH will look for this address in
1929 all incoming packets. */
1930#define NIG_REG_LLH0_DEST_UDP_0 0x10214
1931#define NIG_REG_LLH0_ERROR_MASK 0x1008c
1932/* [RW 8] event id for llh0 */
1933#define NIG_REG_LLH0_EVENT_ID 0x10084
1934#define NIG_REG_LLH0_FUNC_EN 0x160fc
1935#define NIG_REG_LLH0_FUNC_MEM 0x16180
1936#define NIG_REG_LLH0_FUNC_MEM_ENABLE 0x16140
1937#define NIG_REG_LLH0_FUNC_VLAN_ID 0x16100
1938/* [RW 1] Determine the IP version to look for in
1939 ~nig_registers_llh0_dest_ip_0.llh0_dest_ip_0. 0 - IPv6; 1-IPv4 */
1940#define NIG_REG_LLH0_IPV4_IPV6_0 0x10208
1941/* [RW 1] t bit for llh0 */
1942#define NIG_REG_LLH0_T_BIT 0x10074
1943/* [RW 12] VLAN ID 1. In case of VLAN packet the LLH will look for this ID. */
1944#define NIG_REG_LLH0_VLAN_ID_0 0x1022c
1945/* [RW 8] init credit counter for port0 in LLH */
1946#define NIG_REG_LLH0_XCM_INIT_CREDIT 0x10554
1947#define NIG_REG_LLH0_XCM_MASK 0x10130
1948#define NIG_REG_LLH1_BRB1_DRV_MASK 0x10248
1949/* [RW 1] send to BRB1 if no match on any of RMP rules. */
1950#define NIG_REG_LLH1_BRB1_NOT_MCP 0x102dc
1951/* [RW 2] Determine the classification participants. 0: no classification.1:
1952 classification upon VLAN id. 2: classification upon MAC address. 3:
1953 classification upon both VLAN id & MAC addr. */
1954#define NIG_REG_LLH1_CLS_TYPE 0x16084
1955/* [RW 32] cm header for llh1 */
1956#define NIG_REG_LLH1_CM_HEADER 0x10080
1957#define NIG_REG_LLH1_ERROR_MASK 0x10090
1958/* [RW 8] event id for llh1 */
1959#define NIG_REG_LLH1_EVENT_ID 0x10088
1960#define NIG_REG_LLH1_FUNC_MEM 0x161c0
1961#define NIG_REG_LLH1_FUNC_MEM_ENABLE 0x16160
1962#define NIG_REG_LLH1_FUNC_MEM_SIZE 16
1963/* [RW 1] When this bit is set; the LLH will classify the packet before
1964 * sending it to the BRB or calculating WoL on it. This bit controls port 1
1965 * only. The legacy llh_multi_function_mode bit controls port 0. */
1966#define NIG_REG_LLH1_MF_MODE 0x18614
1967/* [RW 8] init credit counter for port1 in LLH */
1968#define NIG_REG_LLH1_XCM_INIT_CREDIT 0x10564
1969#define NIG_REG_LLH1_XCM_MASK 0x10134
1970/* [RW 1] When this bit is set; the LLH will expect all packets to be with
1971 e1hov */
1972#define NIG_REG_LLH_E1HOV_MODE 0x160d8
1973/* [RW 1] When this bit is set; the LLH will classify the packet before
1974 sending it to the BRB or calculating WoL on it. */
1975#define NIG_REG_LLH_MF_MODE 0x16024
1976#define NIG_REG_MASK_INTERRUPT_PORT0 0x10330
1977#define NIG_REG_MASK_INTERRUPT_PORT1 0x10334
1978/* [RW 1] Output signal from NIG to EMAC0. When set enables the EMAC0 block. */
1979#define NIG_REG_NIG_EMAC0_EN 0x1003c
1980/* [RW 1] Output signal from NIG to EMAC1. When set enables the EMAC1 block. */
1981#define NIG_REG_NIG_EMAC1_EN 0x10040
1982/* [RW 1] Output signal from NIG to TX_EMAC0. When set indicates to the
1983 EMAC0 to strip the CRC from the ingress packets. */
1984#define NIG_REG_NIG_INGRESS_EMAC0_NO_CRC 0x10044
1985/* [R 32] Interrupt register #0 read */
1986#define NIG_REG_NIG_INT_STS_0 0x103b0
1987#define NIG_REG_NIG_INT_STS_1 0x103c0
1988/* [R 32] Legacy E1 and E1H location for parity error mask register. */
1989#define NIG_REG_NIG_PRTY_MASK 0x103dc
1990/* [RW 32] Parity mask register #0 read/write */
1991#define NIG_REG_NIG_PRTY_MASK_0 0x183c8
1992#define NIG_REG_NIG_PRTY_MASK_1 0x183d8
1993/* [R 32] Legacy E1 and E1H location for parity error status register. */
1994#define NIG_REG_NIG_PRTY_STS 0x103d0
1995/* [R 32] Parity register #0 read */
1996#define NIG_REG_NIG_PRTY_STS_0 0x183bc
1997#define NIG_REG_NIG_PRTY_STS_1 0x183cc
1998/* [R 32] Legacy E1 and E1H location for parity error status clear register. */
1999#define NIG_REG_NIG_PRTY_STS_CLR 0x103d4
2000/* [RC 32] Parity register #0 read clear */
2001#define NIG_REG_NIG_PRTY_STS_CLR_0 0x183c0
2002#define NIG_REG_NIG_PRTY_STS_CLR_1 0x183d0
2003#define MCPR_IMC_COMMAND_ENABLE (1L<<31)
2004#define MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT 16
2005#define MCPR_IMC_COMMAND_OPERATION_BITSHIFT 28
2006#define MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT 8
2007/* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic
2008 * Ethernet header. */
2009#define NIG_REG_P0_HDRS_AFTER_BASIC 0x18038
2010/* [RW 1] HW PFC enable bit. Set this bit to enable the PFC functionality in
2011 * the NIG. Other flow control modes such as PAUSE and SAFC/LLFC should be
2012 * disabled when this bit is set. */
2013#define NIG_REG_P0_HWPFC_ENABLE 0x18078
2014#define NIG_REG_P0_LLH_FUNC_MEM2 0x18480
2015#define NIG_REG_P0_LLH_FUNC_MEM2_ENABLE 0x18440
2016/* [RW 1] Input enable for RX MAC interface. */
2017#define NIG_REG_P0_MAC_IN_EN 0x185ac
2018/* [RW 1] Output enable for TX MAC interface */
2019#define NIG_REG_P0_MAC_OUT_EN 0x185b0
2020/* [RW 1] Output enable for TX PAUSE signal to the MAC. */
2021#define NIG_REG_P0_MAC_PAUSE_OUT_EN 0x185b4
2022/* [RW 32] Eight 4-bit configurations for specifying which COS (0-15 for
2023 * future expansion) each priorty is to be mapped to. Bits 3:0 specify the
2024 * COS for priority 0. Bits 31:28 specify the COS for priority 7. The 3-bit
2025 * priority field is extracted from the outer-most VLAN in receive packet.
2026 * Only COS 0 and COS 1 are supported in E2. */
2027#define NIG_REG_P0_PKT_PRIORITY_TO_COS 0x18054
2028/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 0. A
2029 * priority is mapped to COS 0 when the corresponding mask bit is 1. More
2030 * than one bit may be set; allowing multiple priorities to be mapped to one
2031 * COS. */
2032#define NIG_REG_P0_RX_COS0_PRIORITY_MASK 0x18058
2033/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 1. A
2034 * priority is mapped to COS 1 when the corresponding mask bit is 1. More
2035 * than one bit may be set; allowing multiple priorities to be mapped to one
2036 * COS. */
2037#define NIG_REG_P0_RX_COS1_PRIORITY_MASK 0x1805c
2038/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 2. A
2039 * priority is mapped to COS 2 when the corresponding mask bit is 1. More
2040 * than one bit may be set; allowing multiple priorities to be mapped to one
2041 * COS. */
2042#define NIG_REG_P0_RX_COS2_PRIORITY_MASK 0x186b0
2043/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 3. A
2044 * priority is mapped to COS 3 when the corresponding mask bit is 1. More
2045 * than one bit may be set; allowing multiple priorities to be mapped to one
2046 * COS. */
2047#define NIG_REG_P0_RX_COS3_PRIORITY_MASK 0x186b4
2048/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 4. A
2049 * priority is mapped to COS 4 when the corresponding mask bit is 1. More
2050 * than one bit may be set; allowing multiple priorities to be mapped to one
2051 * COS. */
2052#define NIG_REG_P0_RX_COS4_PRIORITY_MASK 0x186b8
2053/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 5. A
2054 * priority is mapped to COS 5 when the corresponding mask bit is 1. More
2055 * than one bit may be set; allowing multiple priorities to be mapped to one
2056 * COS. */
2057#define NIG_REG_P0_RX_COS5_PRIORITY_MASK 0x186bc
2058/* [R 1] RX FIFO for receiving data from MAC is empty. */
2059/* [RW 15] Specify which of the credit registers the client is to be mapped
2060 * to. Bits[2:0] are for client 0; bits [14:12] are for client 4. For
2061 * clients that are not subject to WFQ credit blocking - their
2062 * specifications here are not used. */
2063#define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP 0x180f0
2064/* [RW 32] Specify which of the credit registers the client is to be mapped
2065 * to. This register specifies bits 31:0 of the 36-bit value. Bits[3:0] are
2066 * for client 0; bits [35:32] are for client 8. For clients that are not
2067 * subject to WFQ credit blocking - their specifications here are not used.
2068 * This is a new register (with 2_) added in E3 B0 to accommodate the 9
2069 * input clients to ETS arbiter. The reset default is set for management and
2070 * debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to
2071 * use credit registers 0-5 respectively (0x543210876). Note that credit
2072 * registers can not be shared between clients. */
2073#define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB 0x18688
2074/* [RW 4] Specify which of the credit registers the client is to be mapped
2075 * to. This register specifies bits 35:32 of the 36-bit value. Bits[3:0] are
2076 * for client 0; bits [35:32] are for client 8. For clients that are not
2077 * subject to WFQ credit blocking - their specifications here are not used.
2078 * This is a new register (with 2_) added in E3 B0 to accommodate the 9
2079 * input clients to ETS arbiter. The reset default is set for management and
2080 * debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to
2081 * use credit registers 0-5 respectively (0x543210876). Note that credit
2082 * registers can not be shared between clients. */
2083#define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB 0x1868c
2084/* [RW 5] Specify whether the client competes directly in the strict
2085 * priority arbiter. The bits are mapped according to client ID (client IDs
2086 * are defined in tx_arb_priority_client). Default value is set to enable
2087 * strict priorities for clients 0-2 -- management and debug traffic. */
2088#define NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT 0x180e8
2089/* [RW 5] Specify whether the client is subject to WFQ credit blocking. The
2090 * bits are mapped according to client ID (client IDs are defined in
2091 * tx_arb_priority_client). Default value is 0 for not using WFQ credit
2092 * blocking. */
2093#define NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ 0x180ec
2094/* [RW 32] Specify the upper bound that credit register 0 is allowed to
2095 * reach. */
2096#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0 0x1810c
2097#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1 0x18110
2098#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2 0x18114
2099#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3 0x18118
2100#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4 0x1811c
2101#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5 0x186a0
2102#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6 0x186a4
2103#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7 0x186a8
2104#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8 0x186ac
2105/* [RW 32] Specify the weight (in bytes) to be added to credit register 0
2106 * when it is time to increment. */
2107#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0 0x180f8
2108#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1 0x180fc
2109#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2 0x18100
2110#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3 0x18104
2111#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4 0x18108
2112#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5 0x18690
2113#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6 0x18694
2114#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7 0x18698
2115#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8 0x1869c
2116/* [RW 12] Specify the number of strict priority arbitration slots between
2117 * two round-robin arbitration slots to avoid starvation. A value of 0 means
2118 * no strict priority cycles - the strict priority with anti-starvation
2119 * arbiter becomes a round-robin arbiter. */
2120#define NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS 0x180f4
2121/* [RW 15] Specify the client number to be assigned to each priority of the
2122 * strict priority arbiter. Priority 0 is the highest priority. Bits [2:0]
2123 * are for priority 0 client; bits [14:12] are for priority 4 client. The
2124 * clients are assigned the following IDs: 0-management; 1-debug traffic
2125 * from this port; 2-debug traffic from other port; 3-COS0 traffic; 4-COS1
2126 * traffic. The reset value[14:0] is set to 0x4688 (15'b100_011_010_001_000)
2127 * for management at priority 0; debug traffic at priorities 1 and 2; COS0
2128 * traffic at priority 3; and COS1 traffic at priority 4. */
2129#define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT 0x180e4
2130/* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic
2131 * Ethernet header. */
2132#define NIG_REG_P1_HDRS_AFTER_BASIC 0x1818c
2133#define NIG_REG_P1_LLH_FUNC_MEM2 0x184c0
2134#define NIG_REG_P1_LLH_FUNC_MEM2_ENABLE 0x18460
2135/* [RW 32] Specify the client number to be assigned to each priority of the
2136 * strict priority arbiter. This register specifies bits 31:0 of the 36-bit
2137 * value. Priority 0 is the highest priority. Bits [3:0] are for priority 0
2138 * client; bits [35-32] are for priority 8 client. The clients are assigned
2139 * the following IDs: 0-management; 1-debug traffic from this port; 2-debug
2140 * traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 traffic;
2141 * 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. The reset value[35:0] is
2142 * set to 0x345678021. This is a new register (with 2_) added in E3 B0 to
2143 * accommodate the 9 input clients to ETS arbiter. */
2144#define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB 0x18680
2145/* [RW 4] Specify the client number to be assigned to each priority of the
2146 * strict priority arbiter. This register specifies bits 35:32 of the 36-bit
2147 * value. Priority 0 is the highest priority. Bits [3:0] are for priority 0
2148 * client; bits [35-32] are for priority 8 client. The clients are assigned
2149 * the following IDs: 0-management; 1-debug traffic from this port; 2-debug
2150 * traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 traffic;
2151 * 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. The reset value[35:0] is
2152 * set to 0x345678021. This is a new register (with 2_) added in E3 B0 to
2153 * accommodate the 9 input clients to ETS arbiter. */
2154#define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB 0x18684
2155#define NIG_REG_P1_MAC_IN_EN 0x185c0
2156/* [RW 1] Output enable for TX MAC interface */
2157#define NIG_REG_P1_MAC_OUT_EN 0x185c4
2158/* [RW 1] Output enable for TX PAUSE signal to the MAC. */
2159#define NIG_REG_P1_MAC_PAUSE_OUT_EN 0x185c8
2160/* [RW 32] Eight 4-bit configurations for specifying which COS (0-15 for
2161 * future expansion) each priorty is to be mapped to. Bits 3:0 specify the
2162 * COS for priority 0. Bits 31:28 specify the COS for priority 7. The 3-bit
2163 * priority field is extracted from the outer-most VLAN in receive packet.
2164 * Only COS 0 and COS 1 are supported in E2. */
2165#define NIG_REG_P1_PKT_PRIORITY_TO_COS 0x181a8
2166/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 0. A
2167 * priority is mapped to COS 0 when the corresponding mask bit is 1. More
2168 * than one bit may be set; allowing multiple priorities to be mapped to one
2169 * COS. */
2170#define NIG_REG_P1_RX_COS0_PRIORITY_MASK 0x181ac
2171/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 1. A
2172 * priority is mapped to COS 1 when the corresponding mask bit is 1. More
2173 * than one bit may be set; allowing multiple priorities to be mapped to one
2174 * COS. */
2175#define NIG_REG_P1_RX_COS1_PRIORITY_MASK 0x181b0
2176/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 2. A
2177 * priority is mapped to COS 2 when the corresponding mask bit is 1. More
2178 * than one bit may be set; allowing multiple priorities to be mapped to one
2179 * COS. */
2180#define NIG_REG_P1_RX_COS2_PRIORITY_MASK 0x186f8
2181/* [R 1] RX FIFO for receiving data from MAC is empty. */
2182#define NIG_REG_P1_RX_MACFIFO_EMPTY 0x1858c
2183/* [R 1] TLLH FIFO is empty. */
2184#define NIG_REG_P1_TLLH_FIFO_EMPTY 0x18338
2185/* [RW 32] Specify which of the credit registers the client is to be mapped
2186 * to. This register specifies bits 31:0 of the 36-bit value. Bits[3:0] are
2187 * for client 0; bits [35:32] are for client 8. For clients that are not
2188 * subject to WFQ credit blocking - their specifications here are not used.
2189 * This is a new register (with 2_) added in E3 B0 to accommodate the 9
2190 * input clients to ETS arbiter. The reset default is set for management and
2191 * debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to
2192 * use credit registers 0-5 respectively (0x543210876). Note that credit
2193 * registers can not be shared between clients. Note also that there are
2194 * only COS0-2 in port 1- there is a total of 6 clients in port 1. Only
2195 * credit registers 0-5 are valid. This register should be configured
2196 * appropriately before enabling WFQ. */
2197#define NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB 0x186e8
2198/* [RW 4] Specify which of the credit registers the client is to be mapped
2199 * to. This register specifies bits 35:32 of the 36-bit value. Bits[3:0] are
2200 * for client 0; bits [35:32] are for client 8. For clients that are not
2201 * subject to WFQ credit blocking - their specifications here are not used.
2202 * This is a new register (with 2_) added in E3 B0 to accommodate the 9
2203 * input clients to ETS arbiter. The reset default is set for management and
2204 * debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to
2205 * use credit registers 0-5 respectively (0x543210876). Note that credit
2206 * registers can not be shared between clients. Note also that there are
2207 * only COS0-2 in port 1- there is a total of 6 clients in port 1. Only
2208 * credit registers 0-5 are valid. This register should be configured
2209 * appropriately before enabling WFQ. */
2210#define NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB 0x186ec
2211/* [RW 9] Specify whether the client competes directly in the strict
2212 * priority arbiter. The bits are mapped according to client ID (client IDs
2213 * are defined in tx_arb_priority_client2): 0-management; 1-debug traffic
2214 * from this port; 2-debug traffic from other port; 3-COS0 traffic; 4-COS1
2215 * traffic; 5-COS2 traffic; 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic.
2216 * Default value is set to enable strict priorities for all clients. */
2217#define NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT 0x18234
2218/* [RW 9] Specify whether the client is subject to WFQ credit blocking. The
2219 * bits are mapped according to client ID (client IDs are defined in
2220 * tx_arb_priority_client2): 0-management; 1-debug traffic from this port;
2221 * 2-debug traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2
2222 * traffic; 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. Default value is
2223 * 0 for not using WFQ credit blocking. */
2224#define NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ 0x18238
2225#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 0x18258
2226#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 0x1825c
2227#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 0x18260
2228#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 0x18264
2229#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 0x18268
2230#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 0x186f4
2231/* [RW 32] Specify the weight (in bytes) to be added to credit register 0
2232 * when it is time to increment. */
2233#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 0x18244
2234#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 0x18248
2235#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 0x1824c
2236#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 0x18250
2237#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 0x18254
2238#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 0x186f0
2239/* [RW 12] Specify the number of strict priority arbitration slots between
2240 two round-robin arbitration slots to avoid starvation. A value of 0 means
2241 no strict priority cycles - the strict priority with anti-starvation
2242 arbiter becomes a round-robin arbiter. */
2243#define NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS 0x18240
2244/* [RW 32] Specify the client number to be assigned to each priority of the
2245 strict priority arbiter. This register specifies bits 31:0 of the 36-bit
2246 value. Priority 0 is the highest priority. Bits [3:0] are for priority 0
2247 client; bits [35-32] are for priority 8 client. The clients are assigned
2248 the following IDs: 0-management; 1-debug traffic from this port; 2-debug
2249 traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 traffic;
2250 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. The reset value[35:0] is
2251 set to 0x345678021. This is a new register (with 2_) added in E3 B0 to
2252 accommodate the 9 input clients to ETS arbiter. Note that this register
2253 is the same as the one for port 0, except that port 1 only has COS 0-2
2254 traffic. There is no traffic for COS 3-5 of port 1. */
2255#define NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB 0x186e0
2256/* [RW 4] Specify the client number to be assigned to each priority of the
2257 strict priority arbiter. This register specifies bits 35:32 of the 36-bit
2258 value. Priority 0 is the highest priority. Bits [3:0] are for priority 0
2259 client; bits [35-32] are for priority 8 client. The clients are assigned
2260 the following IDs: 0-management; 1-debug traffic from this port; 2-debug
2261 traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 traffic;
2262 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. The reset value[35:0] is
2263 set to 0x345678021. This is a new register (with 2_) added in E3 B0 to
2264 accommodate the 9 input clients to ETS arbiter. Note that this register
2265 is the same as the one for port 0, except that port 1 only has COS 0-2
2266 traffic. There is no traffic for COS 3-5 of port 1. */
2267#define NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB 0x186e4
2268/* [R 1] TX FIFO for transmitting data to MAC is empty. */
2269#define NIG_REG_P1_TX_MACFIFO_EMPTY 0x18594
2270/* [R 1] FIFO empty status of the MCP TX FIFO used for storing MCP packets
2271 forwarded to the host. */
2272#define NIG_REG_P1_TX_MNG_HOST_FIFO_EMPTY 0x182b8
2273/* [RW 32] Specify the upper bound that credit register 0 is allowed to
2274 * reach. */
2275/* [RW 1] Pause enable for port0. This register may get 1 only when
2276 ~safc_enable.safc_enable = 0 and ppp_enable.ppp_enable =0 for the same
2277 port */
2278#define NIG_REG_PAUSE_ENABLE_0 0x160c0
2279#define NIG_REG_PAUSE_ENABLE_1 0x160c4
2280/* [RW 1] Input enable for RX PBF LP IF */
2281#define NIG_REG_PBF_LB_IN_EN 0x100b4
2282/* [RW 1] Value of this register will be transmitted to port swap when
2283 ~nig_registers_strap_override.strap_override =1 */
2284#define NIG_REG_PORT_SWAP 0x10394
2285/* [RW 1] PPP enable for port0. This register may get 1 only when
2286 * ~safc_enable.safc_enable = 0 and pause_enable.pause_enable =0 for the
2287 * same port */
2288#define NIG_REG_PPP_ENABLE_0 0x160b0
2289#define NIG_REG_PPP_ENABLE_1 0x160b4
2290/* [RW 1] output enable for RX parser descriptor IF */
2291#define NIG_REG_PRS_EOP_OUT_EN 0x10104
2292/* [RW 1] Input enable for RX parser request IF */
2293#define NIG_REG_PRS_REQ_IN_EN 0x100b8
2294/* [RW 5] control to serdes - CL45 DEVAD */
2295#define NIG_REG_SERDES0_CTRL_MD_DEVAD 0x10370
2296/* [RW 1] control to serdes; 0 - clause 45; 1 - clause 22 */
2297#define NIG_REG_SERDES0_CTRL_MD_ST 0x1036c
2298/* [RW 5] control to serdes - CL22 PHY_ADD and CL45 PRTAD */
2299#define NIG_REG_SERDES0_CTRL_PHY_ADDR 0x10374
2300/* [R 1] status from serdes0 that inputs to interrupt logic of link status */
2301#define NIG_REG_SERDES0_STATUS_LINK_STATUS 0x10578
2302/* [R 32] Rx statistics : In user packets discarded due to BRB backpressure
2303 for port0 */
2304#define NIG_REG_STAT0_BRB_DISCARD 0x105f0
2305/* [R 32] Rx statistics : In user packets truncated due to BRB backpressure
2306 for port0 */
2307#define NIG_REG_STAT0_BRB_TRUNCATE 0x105f8
2308/* [WB_R 36] Tx statistics : Number of packets from emac0 or bmac0 that
2309 between 1024 and 1522 bytes for port0 */
2310#define NIG_REG_STAT0_EGRESS_MAC_PKT0 0x10750
2311/* [WB_R 36] Tx statistics : Number of packets from emac0 or bmac0 that
2312 between 1523 bytes and above for port0 */
2313#define NIG_REG_STAT0_EGRESS_MAC_PKT1 0x10760
2314/* [R 32] Rx statistics : In user packets discarded due to BRB backpressure
2315 for port1 */
2316#define NIG_REG_STAT1_BRB_DISCARD 0x10628
2317/* [WB_R 36] Tx statistics : Number of packets from emac1 or bmac1 that
2318 between 1024 and 1522 bytes for port1 */
2319#define NIG_REG_STAT1_EGRESS_MAC_PKT0 0x107a0
2320/* [WB_R 36] Tx statistics : Number of packets from emac1 or bmac1 that
2321 between 1523 bytes and above for port1 */
2322#define NIG_REG_STAT1_EGRESS_MAC_PKT1 0x107b0
2323/* [WB_R 64] Rx statistics : User octets received for LP */
2324#define NIG_REG_STAT2_BRB_OCTET 0x107e0
2325#define NIG_REG_STATUS_INTERRUPT_PORT0 0x10328
2326#define NIG_REG_STATUS_INTERRUPT_PORT1 0x1032c
2327/* [RW 1] port swap mux selection. If this register equal to 0 then port
2328 swap is equal to SPIO pin that inputs from ifmux_serdes_swap. If 1 then
2329 ort swap is equal to ~nig_registers_port_swap.port_swap */
2330#define NIG_REG_STRAP_OVERRIDE 0x10398
2331/* [RW 1] output enable for RX_XCM0 IF */
2332#define NIG_REG_XCM0_OUT_EN 0x100f0
2333/* [RW 1] output enable for RX_XCM1 IF */
2334#define NIG_REG_XCM1_OUT_EN 0x100f4
2335/* [RW 1] control to xgxs - remote PHY in-band MDIO */
2336#define NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST 0x10348
2337/* [RW 5] control to xgxs - CL45 DEVAD */
2338#define NIG_REG_XGXS0_CTRL_MD_DEVAD 0x1033c
2339/* [RW 1] control to xgxs; 0 - clause 45; 1 - clause 22 */
2340#define NIG_REG_XGXS0_CTRL_MD_ST 0x10338
2341/* [RW 5] control to xgxs - CL22 PHY_ADD and CL45 PRTAD */
2342#define NIG_REG_XGXS0_CTRL_PHY_ADDR 0x10340
2343/* [R 1] status from xgxs0 that inputs to interrupt logic of link10g. */
2344#define NIG_REG_XGXS0_STATUS_LINK10G 0x10680
2345/* [R 4] status from xgxs0 that inputs to interrupt logic of link status */
2346#define NIG_REG_XGXS0_STATUS_LINK_STATUS 0x10684
2347/* [RW 2] selection for XGXS lane of port 0 in NIG_MUX block */
2348#define NIG_REG_XGXS_LANE_SEL_P0 0x102e8
2349/* [RW 1] selection for port0 for NIG_MUX block : 0 = SerDes; 1 = XGXS */
2350#define NIG_REG_XGXS_SERDES0_MODE_SEL 0x102e0
2351#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT (0x1<<0)
2352#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS (0x1<<9)
2353#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G (0x1<<15)
2354#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS (0xf<<18)
2355#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE 18
2356/* [RW 31] The upper bound of the weight of COS0 in the ETS command arbiter. */
2357#define PBF_REG_COS0_UPPER_BOUND 0x15c05c
2358/* [RW 31] The upper bound of the weight of COS0 in the ETS command arbiter
2359 * of port 0. */
2360#define PBF_REG_COS0_UPPER_BOUND_P0 0x15c2cc
2361/* [RW 31] The upper bound of the weight of COS0 in the ETS command arbiter
2362 * of port 1. */
2363#define PBF_REG_COS0_UPPER_BOUND_P1 0x15c2e4
2364/* [RW 31] The weight of COS0 in the ETS command arbiter. */
2365#define PBF_REG_COS0_WEIGHT 0x15c054
2366/* [RW 31] The weight of COS0 in port 0 ETS command arbiter. */
2367#define PBF_REG_COS0_WEIGHT_P0 0x15c2a8
2368/* [RW 31] The weight of COS0 in port 1 ETS command arbiter. */
2369#define PBF_REG_COS0_WEIGHT_P1 0x15c2c0
2370/* [RW 31] The upper bound of the weight of COS1 in the ETS command arbiter. */
2371#define PBF_REG_COS1_UPPER_BOUND 0x15c060
2372/* [RW 31] The weight of COS1 in the ETS command arbiter. */
2373#define PBF_REG_COS1_WEIGHT 0x15c058
2374/* [RW 31] The weight of COS1 in port 0 ETS command arbiter. */
2375#define PBF_REG_COS1_WEIGHT_P0 0x15c2ac
2376/* [RW 31] The weight of COS1 in port 1 ETS command arbiter. */
2377#define PBF_REG_COS1_WEIGHT_P1 0x15c2c4
2378/* [RW 31] The weight of COS2 in port 0 ETS command arbiter. */
2379#define PBF_REG_COS2_WEIGHT_P0 0x15c2b0
2380/* [RW 31] The weight of COS2 in port 1 ETS command arbiter. */
2381#define PBF_REG_COS2_WEIGHT_P1 0x15c2c8
2382/* [RW 31] The weight of COS3 in port 0 ETS command arbiter. */
2383#define PBF_REG_COS3_WEIGHT_P0 0x15c2b4
2384/* [RW 31] The weight of COS4 in port 0 ETS command arbiter. */
2385#define PBF_REG_COS4_WEIGHT_P0 0x15c2b8
2386/* [RW 31] The weight of COS5 in port 0 ETS command arbiter. */
2387#define PBF_REG_COS5_WEIGHT_P0 0x15c2bc
2388/* [R 11] Current credit for the LB queue in the tx port buffers in 16 byte
2389 * lines. */
2390#define PBF_REG_CREDIT_LB_Q 0x140338
2391/* [R 11] Current credit for queue 0 in the tx port buffers in 16 byte
2392 * lines. */
2393#define PBF_REG_CREDIT_Q0 0x14033c
2394/* [R 11] Current credit for queue 1 in the tx port buffers in 16 byte
2395 * lines. */
2396#define PBF_REG_CREDIT_Q1 0x140340
2397/* [RW 1] Disable processing further tasks from port 0 (after ending the
2398 current task in process). */
2399#define PBF_REG_DISABLE_NEW_TASK_PROC_P0 0x14005c
2400/* [RW 1] Disable processing further tasks from port 1 (after ending the
2401 current task in process). */
2402#define PBF_REG_DISABLE_NEW_TASK_PROC_P1 0x140060
2403/* [RW 1] Disable processing further tasks from port 4 (after ending the
2404 current task in process). */
2405#define PBF_REG_DISABLE_NEW_TASK_PROC_P4 0x14006c
2406#define PBF_REG_DISABLE_PF 0x1402e8
2407/* [RW 18] For port 0: For each client that is subject to WFQ (the
2408 * corresponding bit is 1); indicates to which of the credit registers this
2409 * client is mapped. For clients which are not credit blocked; their mapping
2410 * is dont care. */
2411#define PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0 0x15c288
2412/* [RW 9] For port 1: For each client that is subject to WFQ (the
2413 * corresponding bit is 1); indicates to which of the credit registers this
2414 * client is mapped. For clients which are not credit blocked; their mapping
2415 * is dont care. */
2416#define PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1 0x15c28c
2417/* [RW 6] For port 0: Bit per client to indicate if the client competes in
2418 * the strict priority arbiter directly (corresponding bit = 1); or first
2419 * goes to the RR arbiter (corresponding bit = 0); and then competes in the
2420 * lowest priority in the strict-priority arbiter. */
2421#define PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 0x15c278
2422/* [RW 3] For port 1: Bit per client to indicate if the client competes in
2423 * the strict priority arbiter directly (corresponding bit = 1); or first
2424 * goes to the RR arbiter (corresponding bit = 0); and then competes in the
2425 * lowest priority in the strict-priority arbiter. */
2426#define PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 0x15c27c
2427/* [RW 6] For port 0: Bit per client to indicate if the client is subject to
2428 * WFQ credit blocking (corresponding bit = 1). */
2429#define PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0 0x15c280
2430/* [RW 3] For port 0: Bit per client to indicate if the client is subject to
2431 * WFQ credit blocking (corresponding bit = 1). */
2432#define PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 0x15c284
2433/* [RW 16] For port 0: The number of strict priority arbitration slots
2434 * between 2 RR arbitration slots. A value of 0 means no strict priority
2435 * cycles; i.e. the strict-priority w/ anti-starvation arbiter is a RR
2436 * arbiter. */
2437#define PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0 0x15c2a0
2438/* [RW 16] For port 1: The number of strict priority arbitration slots
2439 * between 2 RR arbitration slots. A value of 0 means no strict priority
2440 * cycles; i.e. the strict-priority w/ anti-starvation arbiter is a RR
2441 * arbiter. */
2442#define PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 0x15c2a4
2443/* [RW 18] For port 0: Indicates which client is connected to each priority
2444 * in the strict-priority arbiter. Priority 0 is the highest priority, and
2445 * priority 5 is the lowest; to which the RR output is connected to (this is
2446 * not configurable). */
2447#define PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 0x15c270
2448/* [RW 9] For port 1: Indicates which client is connected to each priority
2449 * in the strict-priority arbiter. Priority 0 is the highest priority, and
2450 * priority 5 is the lowest; to which the RR output is connected to (this is
2451 * not configurable). */
2452#define PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 0x15c274
2453/* [RW 1] Indicates that ETS is performed between the COSes in the command
2454 * arbiter. If reset strict priority w/ anti-starvation will be performed
2455 * w/o WFQ. */
2456#define PBF_REG_ETS_ENABLED 0x15c050
2457/* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic
2458 * Ethernet header. */
2459#define PBF_REG_HDRS_AFTER_BASIC 0x15c0a8
2460/* [RW 6] Bit-map indicating which L2 hdrs may appear after L2 tag 0 */
2461#define PBF_REG_HDRS_AFTER_TAG_0 0x15c0b8
2462/* [R 1] Removed for E3 B0 - Indicates which COS is conncted to the highest
2463 * priority in the command arbiter. */
2464#define PBF_REG_HIGH_PRIORITY_COS_NUM 0x15c04c
2465#define PBF_REG_IF_ENABLE_REG 0x140044
2466/* [RW 1] Init bit. When set the initial credits are copied to the credit
2467 registers (except the port credits). Should be set and then reset after
2468 the configuration of the block has ended. */
2469#define PBF_REG_INIT 0x140000
2470/* [RW 11] Initial credit for the LB queue in the tx port buffers in 16 byte
2471 * lines. */
2472#define PBF_REG_INIT_CRD_LB_Q 0x15c248
2473/* [RW 11] Initial credit for queue 0 in the tx port buffers in 16 byte
2474 * lines. */
2475#define PBF_REG_INIT_CRD_Q0 0x15c230
2476/* [RW 11] Initial credit for queue 1 in the tx port buffers in 16 byte
2477 * lines. */
2478#define PBF_REG_INIT_CRD_Q1 0x15c234
2479/* [RW 1] Init bit for port 0. When set the initial credit of port 0 is
2480 copied to the credit register. Should be set and then reset after the
2481 configuration of the port has ended. */
2482#define PBF_REG_INIT_P0 0x140004
2483/* [RW 1] Init bit for port 1. When set the initial credit of port 1 is
2484 copied to the credit register. Should be set and then reset after the
2485 configuration of the port has ended. */
2486#define PBF_REG_INIT_P1 0x140008
2487/* [RW 1] Init bit for port 4. When set the initial credit of port 4 is
2488 copied to the credit register. Should be set and then reset after the
2489 configuration of the port has ended. */
2490#define PBF_REG_INIT_P4 0x14000c
2491/* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for
2492 * the LB queue. Reset upon init. */
2493#define PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q 0x140354
2494/* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for
2495 * queue 0. Reset upon init. */
2496#define PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 0x140358
2497/* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for
2498 * queue 1. Reset upon init. */
2499#define PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 0x14035c
2500/* [RW 1] Enable for mac interface 0. */
2501#define PBF_REG_MAC_IF0_ENABLE 0x140030
2502/* [RW 1] Enable for mac interface 1. */
2503#define PBF_REG_MAC_IF1_ENABLE 0x140034
2504/* [RW 1] Enable for the loopback interface. */
2505#define PBF_REG_MAC_LB_ENABLE 0x140040
2506/* [RW 6] Bit-map indicating which headers must appear in the packet */
2507#define PBF_REG_MUST_HAVE_HDRS 0x15c0c4
2508/* [RW 16] The number of strict priority arbitration slots between 2 RR
2509 * arbitration slots. A value of 0 means no strict priority cycles; i.e. the
2510 * strict-priority w/ anti-starvation arbiter is a RR arbiter. */
2511#define PBF_REG_NUM_STRICT_ARB_SLOTS 0x15c064
2512/* [RW 10] Port 0 threshold used by arbiter in 16 byte lines used when pause
2513 not suppoterd. */
2514#define PBF_REG_P0_ARB_THRSH 0x1400e4
2515/* [R 11] Current credit for port 0 in the tx port buffers in 16 byte lines. */
2516#define PBF_REG_P0_CREDIT 0x140200
2517/* [RW 11] Initial credit for port 0 in the tx port buffers in 16 byte
2518 lines. */
2519#define PBF_REG_P0_INIT_CRD 0x1400d0
2520/* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for
2521 * port 0. Reset upon init. */
2522#define PBF_REG_P0_INTERNAL_CRD_FREED_CNT 0x140308
2523/* [R 1] Removed for E3 B0 - Indication that pause is enabled for port 0. */
2524#define PBF_REG_P0_PAUSE_ENABLE 0x140014
2525/* [R 8] Removed for E3 B0 - Number of tasks in port 0 task queue. */
2526#define PBF_REG_P0_TASK_CNT 0x140204
2527/* [R 32] Removed for E3 B0 - Cyclic counter for number of 8 byte lines
2528 * freed from the task queue of port 0. Reset upon init. */
2529#define PBF_REG_P0_TQ_LINES_FREED_CNT 0x1402f0
2530/* [R 12] Number of 8 bytes lines occupied in the task queue of port 0. */
2531#define PBF_REG_P0_TQ_OCCUPANCY 0x1402fc
2532/* [R 11] Removed for E3 B0 - Current credit for port 1 in the tx port
2533 * buffers in 16 byte lines. */
2534#define PBF_REG_P1_CREDIT 0x140208
2535/* [R 11] Removed for E3 B0 - Initial credit for port 0 in the tx port
2536 * buffers in 16 byte lines. */
2537#define PBF_REG_P1_INIT_CRD 0x1400d4
2538/* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for
2539 * port 1. Reset upon init. */
2540#define PBF_REG_P1_INTERNAL_CRD_FREED_CNT 0x14030c
2541/* [R 8] Removed for E3 B0 - Number of tasks in port 1 task queue. */
2542#define PBF_REG_P1_TASK_CNT 0x14020c
2543/* [R 32] Removed for E3 B0 - Cyclic counter for number of 8 byte lines
2544 * freed from the task queue of port 1. Reset upon init. */
2545#define PBF_REG_P1_TQ_LINES_FREED_CNT 0x1402f4
2546/* [R 12] Number of 8 bytes lines occupied in the task queue of port 1. */
2547#define PBF_REG_P1_TQ_OCCUPANCY 0x140300
2548/* [R 11] Current credit for port 4 in the tx port buffers in 16 byte lines. */
2549#define PBF_REG_P4_CREDIT 0x140210
2550/* [RW 11] Initial credit for port 4 in the tx port buffers in 16 byte
2551 lines. */
2552#define PBF_REG_P4_INIT_CRD 0x1400e0
2553/* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for
2554 * port 4. Reset upon init. */
2555#define PBF_REG_P4_INTERNAL_CRD_FREED_CNT 0x140310
2556/* [R 8] Removed for E3 B0 - Number of tasks in port 4 task queue. */
2557#define PBF_REG_P4_TASK_CNT 0x140214
2558/* [R 32] Removed for E3 B0 - Cyclic counter for number of 8 byte lines
2559 * freed from the task queue of port 4. Reset upon init. */
2560#define PBF_REG_P4_TQ_LINES_FREED_CNT 0x1402f8
2561/* [R 12] Number of 8 bytes lines occupied in the task queue of port 4. */
2562#define PBF_REG_P4_TQ_OCCUPANCY 0x140304
2563/* [RW 5] Interrupt mask register #0 read/write */
2564#define PBF_REG_PBF_INT_MASK 0x1401d4
2565/* [R 5] Interrupt register #0 read */
2566#define PBF_REG_PBF_INT_STS 0x1401c8
2567/* [RW 20] Parity mask register #0 read/write */
2568#define PBF_REG_PBF_PRTY_MASK 0x1401e4
2569/* [RC 20] Parity register #0 read clear */
2570#define PBF_REG_PBF_PRTY_STS_CLR 0x1401dc
2571/* [RW 16] The Ethernet type value for L2 tag 0 */
2572#define PBF_REG_TAG_ETHERTYPE_0 0x15c090
2573/* [RW 4] The length of the info field for L2 tag 0. The length is between
2574 * 2B and 14B; in 2B granularity */
2575#define PBF_REG_TAG_LEN_0 0x15c09c
2576/* [R 32] Cyclic counter for number of 8 byte lines freed from the LB task
2577 * queue. Reset upon init. */
2578#define PBF_REG_TQ_LINES_FREED_CNT_LB_Q 0x14038c
2579/* [R 32] Cyclic counter for number of 8 byte lines freed from the task
2580 * queue 0. Reset upon init. */
2581#define PBF_REG_TQ_LINES_FREED_CNT_Q0 0x140390
2582/* [R 32] Cyclic counter for number of 8 byte lines freed from task queue 1.
2583 * Reset upon init. */
2584#define PBF_REG_TQ_LINES_FREED_CNT_Q1 0x140394
2585/* [R 13] Number of 8 bytes lines occupied in the task queue of the LB
2586 * queue. */
2587#define PBF_REG_TQ_OCCUPANCY_LB_Q 0x1403a8
2588/* [R 13] Number of 8 bytes lines occupied in the task queue of queue 0. */
2589#define PBF_REG_TQ_OCCUPANCY_Q0 0x1403ac
2590/* [R 13] Number of 8 bytes lines occupied in the task queue of queue 1. */
2591#define PBF_REG_TQ_OCCUPANCY_Q1 0x1403b0
2592#define PB_REG_CONTROL 0
2593/* [RW 2] Interrupt mask register #0 read/write */
2594#define PB_REG_PB_INT_MASK 0x28
2595/* [R 2] Interrupt register #0 read */
2596#define PB_REG_PB_INT_STS 0x1c
2597/* [RW 4] Parity mask register #0 read/write */
2598#define PB_REG_PB_PRTY_MASK 0x38
2599/* [R 4] Parity register #0 read */
2600#define PB_REG_PB_PRTY_STS 0x2c
2601/* [RC 4] Parity register #0 read clear */
2602#define PB_REG_PB_PRTY_STS_CLR 0x30
2603#define PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
2604#define PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW (0x1<<8)
2605#define PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR (0x1<<1)
2606#define PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN (0x1<<6)
2607#define PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN (0x1<<7)
2608#define PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN (0x1<<4)
2609#define PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN (0x1<<3)
2610#define PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN (0x1<<5)
2611#define PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN (0x1<<2)
2612/* [R 8] Config space A attention dirty bits. Each bit indicates that the
2613 * corresponding PF generates config space A attention. Set by PXP. Reset by
2614 * MCP writing 1 to icfg_space_a_request_clr. Note: register contains bits
2615 * from both paths. */
2616#define PGLUE_B_REG_CFG_SPACE_A_REQUEST 0x9010
2617/* [R 8] Config space B attention dirty bits. Each bit indicates that the
2618 * corresponding PF generates config space B attention. Set by PXP. Reset by
2619 * MCP writing 1 to icfg_space_b_request_clr. Note: register contains bits
2620 * from both paths. */
2621#define PGLUE_B_REG_CFG_SPACE_B_REQUEST 0x9014
2622/* [RW 1] Type A PF enable inbound interrupt table for CSDM. 0 - disable; 1
2623 * - enable. */
2624#define PGLUE_B_REG_CSDM_INB_INT_A_PF_ENABLE 0x9194
2625/* [RW 18] Type B VF inbound interrupt table for CSDM: bits[17:9]-mask;
2626 * its[8:0]-address. Bits [1:0] must be zero (DW resolution address). */
2627#define PGLUE_B_REG_CSDM_INB_INT_B_VF 0x916c
2628/* [RW 1] Type B VF enable inbound interrupt table for CSDM. 0 - disable; 1
2629 * - enable. */
2630#define PGLUE_B_REG_CSDM_INB_INT_B_VF_ENABLE 0x919c
2631/* [RW 16] Start offset of CSDM zone A (queue zone) in the internal RAM */
2632#define PGLUE_B_REG_CSDM_START_OFFSET_A 0x9100
2633/* [RW 16] Start offset of CSDM zone B (legacy zone) in the internal RAM */
2634#define PGLUE_B_REG_CSDM_START_OFFSET_B 0x9108
2635/* [RW 5] VF Shift of CSDM zone B (legacy zone) in the internal RAM */
2636#define PGLUE_B_REG_CSDM_VF_SHIFT_B 0x9110
2637/* [RW 1] 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B. */
2638#define PGLUE_B_REG_CSDM_ZONE_A_SIZE_PF 0x91ac
2639/* [R 8] FLR request attention dirty bits for PFs 0 to 7. Each bit indicates
2640 * that the FLR register of the corresponding PF was set. Set by PXP. Reset
2641 * by MCP writing 1 to flr_request_pf_7_0_clr. Note: register contains bits
2642 * from both paths. */
2643#define PGLUE_B_REG_FLR_REQUEST_PF_7_0 0x9028
2644/* [W 8] FLR request attention dirty bits clear for PFs 0 to 7. MCP writes 1
2645 * to a bit in this register in order to clear the corresponding bit in
2646 * flr_request_pf_7_0 register. Note: register contains bits from both
2647 * paths. */
2648#define PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR 0x9418
2649/* [R 32] FLR request attention dirty bits for VFs 96 to 127. Each bit
2650 * indicates that the FLR register of the corresponding VF was set. Set by
2651 * PXP. Reset by MCP writing 1 to flr_request_vf_127_96_clr. */
2652#define PGLUE_B_REG_FLR_REQUEST_VF_127_96 0x9024
2653/* [R 32] FLR request attention dirty bits for VFs 0 to 31. Each bit
2654 * indicates that the FLR register of the corresponding VF was set. Set by
2655 * PXP. Reset by MCP writing 1 to flr_request_vf_31_0_clr. */
2656#define PGLUE_B_REG_FLR_REQUEST_VF_31_0 0x9018
2657/* [R 32] FLR request attention dirty bits for VFs 32 to 63. Each bit
2658 * indicates that the FLR register of the corresponding VF was set. Set by
2659 * PXP. Reset by MCP writing 1 to flr_request_vf_63_32_clr. */
2660#define PGLUE_B_REG_FLR_REQUEST_VF_63_32 0x901c
2661/* [R 32] FLR request attention dirty bits for VFs 64 to 95. Each bit
2662 * indicates that the FLR register of the corresponding VF was set. Set by
2663 * PXP. Reset by MCP writing 1 to flr_request_vf_95_64_clr. */
2664#define PGLUE_B_REG_FLR_REQUEST_VF_95_64 0x9020
2665/* [R 8] Each bit indicates an incorrect behavior in user RX interface. Bit
2666 * 0 - Target memory read arrived with a correctable error. Bit 1 - Target
2667 * memory read arrived with an uncorrectable error. Bit 2 - Configuration RW
2668 * arrived with a correctable error. Bit 3 - Configuration RW arrived with
2669 * an uncorrectable error. Bit 4 - Completion with Configuration Request
2670 * Retry Status. Bit 5 - Expansion ROM access received with a write request.
2671 * Bit 6 - Completion with pcie_rx_err of 0000; CMPL_STATUS of non-zero; and
2672 * pcie_rx_last not asserted. Bit 7 - Completion with pcie_rx_err of 1010;
2673 * and pcie_rx_last not asserted. */
2674#define PGLUE_B_REG_INCORRECT_RCV_DETAILS 0x9068
2675#define PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER 0x942c
2676#define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ 0x9430
2677#define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_WRITE 0x9434
2678#define PGLUE_B_REG_INTERNAL_VFID_ENABLE 0x9438
2679/* [R 9] Interrupt register #0 read */
2680#define PGLUE_B_REG_PGLUE_B_INT_STS 0x9298
2681/* [RC 9] Interrupt register #0 read clear */
2682#define PGLUE_B_REG_PGLUE_B_INT_STS_CLR 0x929c
2683/* [RW 2] Parity mask register #0 read/write */
2684#define PGLUE_B_REG_PGLUE_B_PRTY_MASK 0x92b4
2685/* [R 2] Parity register #0 read */
2686#define PGLUE_B_REG_PGLUE_B_PRTY_STS 0x92a8
2687/* [RC 2] Parity register #0 read clear */
2688#define PGLUE_B_REG_PGLUE_B_PRTY_STS_CLR 0x92ac
2689/* [R 13] Details of first request received with error. [2:0] - PFID. [3] -
2690 * VF_VALID. [9:4] - VFID. [11:10] - Error Code - 0 - Indicates Completion
2691 * Timeout of a User Tx non-posted request. 1 - unsupported request. 2 -
2692 * completer abort. 3 - Illegal value for this field. [12] valid - indicates
2693 * if there was a completion error since the last time this register was
2694 * cleared. */
2695#define PGLUE_B_REG_RX_ERR_DETAILS 0x9080
2696/* [R 18] Details of first ATS Translation Completion request received with
2697 * error. [2:0] - PFID. [3] - VF_VALID. [9:4] - VFID. [11:10] - Error Code -
2698 * 0 - Indicates Completion Timeout of a User Tx non-posted request. 1 -
2699 * unsupported request. 2 - completer abort. 3 - Illegal value for this
2700 * field. [16:12] - ATC OTB EntryID. [17] valid - indicates if there was a
2701 * completion error since the last time this register was cleared. */
2702#define PGLUE_B_REG_RX_TCPL_ERR_DETAILS 0x9084
2703/* [W 8] Debug only - Shadow BME bits clear for PFs 0 to 7. MCP writes 1 to
2704 * a bit in this register in order to clear the corresponding bit in
2705 * shadow_bme_pf_7_0 register. MCP should never use this unless a
2706 * work-around is needed. Note: register contains bits from both paths. */
2707#define PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR 0x9458
2708/* [R 8] SR IOV disabled attention dirty bits. Each bit indicates that the
2709 * VF enable register of the corresponding PF is written to 0 and was
2710 * previously 1. Set by PXP. Reset by MCP writing 1 to
2711 * sr_iov_disabled_request_clr. Note: register contains bits from both
2712 * paths. */
2713#define PGLUE_B_REG_SR_IOV_DISABLED_REQUEST 0x9030
2714/* [R 32] Indicates the status of tags 32-63. 0 - tags is used - read
2715 * completion did not return yet. 1 - tag is unused. Same functionality as
2716 * pxp2_registers_pgl_exp_rom_data2 for tags 0-31. */
2717#define PGLUE_B_REG_TAGS_63_32 0x9244
2718/* [RW 1] Type A PF enable inbound interrupt table for TSDM. 0 - disable; 1
2719 * - enable. */
2720#define PGLUE_B_REG_TSDM_INB_INT_A_PF_ENABLE 0x9170
2721/* [RW 16] Start offset of TSDM zone A (queue zone) in the internal RAM */
2722#define PGLUE_B_REG_TSDM_START_OFFSET_A 0x90c4
2723/* [RW 16] Start offset of TSDM zone B (legacy zone) in the internal RAM */
2724#define PGLUE_B_REG_TSDM_START_OFFSET_B 0x90cc
2725/* [RW 5] VF Shift of TSDM zone B (legacy zone) in the internal RAM */
2726#define PGLUE_B_REG_TSDM_VF_SHIFT_B 0x90d4
2727/* [RW 1] 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B. */
2728#define PGLUE_B_REG_TSDM_ZONE_A_SIZE_PF 0x91a0
2729/* [R 32] Address [31:0] of first read request not submitted due to error */
2730#define PGLUE_B_REG_TX_ERR_RD_ADD_31_0 0x9098
2731/* [R 32] Address [63:32] of first read request not submitted due to error */
2732#define PGLUE_B_REG_TX_ERR_RD_ADD_63_32 0x909c
2733/* [R 31] Details of first read request not submitted due to error. [4:0]
2734 * VQID. [5] TREQ. 1 - Indicates the request is a Translation Request.
2735 * [20:8] - Length in bytes. [23:21] - PFID. [24] - VF_VALID. [30:25] -
2736 * VFID. */
2737#define PGLUE_B_REG_TX_ERR_RD_DETAILS 0x90a0
2738/* [R 26] Details of first read request not submitted due to error. [15:0]
2739 * Request ID. [19:16] client ID. [20] - last SR. [24:21] - Error type -
2740 * [21] - Indicates was_error was set; [22] - Indicates BME was cleared;
2741 * [23] - Indicates FID_enable was cleared; [24] - Indicates VF with parent
2742 * PF FLR_request or IOV_disable_request dirty bit is set. [25] valid -
2743 * indicates if there was a request not submitted due to error since the
2744 * last time this register was cleared. */
2745#define PGLUE_B_REG_TX_ERR_RD_DETAILS2 0x90a4
2746/* [R 32] Address [31:0] of first write request not submitted due to error */
2747#define PGLUE_B_REG_TX_ERR_WR_ADD_31_0 0x9088
2748/* [R 32] Address [63:32] of first write request not submitted due to error */
2749#define PGLUE_B_REG_TX_ERR_WR_ADD_63_32 0x908c
2750/* [R 31] Details of first write request not submitted due to error. [4:0]
2751 * VQID. [20:8] - Length in bytes. [23:21] - PFID. [24] - VF_VALID. [30:25]
2752 * - VFID. */
2753#define PGLUE_B_REG_TX_ERR_WR_DETAILS 0x9090
2754/* [R 26] Details of first write request not submitted due to error. [15:0]
2755 * Request ID. [19:16] client ID. [20] - last SR. [24:21] - Error type -
2756 * [21] - Indicates was_error was set; [22] - Indicates BME was cleared;
2757 * [23] - Indicates FID_enable was cleared; [24] - Indicates VF with parent
2758 * PF FLR_request or IOV_disable_request dirty bit is set. [25] valid -
2759 * indicates if there was a request not submitted due to error since the
2760 * last time this register was cleared. */
2761#define PGLUE_B_REG_TX_ERR_WR_DETAILS2 0x9094
2762/* [RW 10] Type A PF/VF inbound interrupt table for USDM: bits[9:5]-mask;
2763 * its[4:0]-address relative to start_offset_a. Bits [1:0] can have any
2764 * value (Byte resolution address). */
2765#define PGLUE_B_REG_USDM_INB_INT_A_0 0x9128
2766#define PGLUE_B_REG_USDM_INB_INT_A_1 0x912c
2767#define PGLUE_B_REG_USDM_INB_INT_A_2 0x9130
2768#define PGLUE_B_REG_USDM_INB_INT_A_3 0x9134
2769#define PGLUE_B_REG_USDM_INB_INT_A_4 0x9138
2770#define PGLUE_B_REG_USDM_INB_INT_A_5 0x913c
2771#define PGLUE_B_REG_USDM_INB_INT_A_6 0x9140
2772/* [RW 1] Type A PF enable inbound interrupt table for USDM. 0 - disable; 1
2773 * - enable. */
2774#define PGLUE_B_REG_USDM_INB_INT_A_PF_ENABLE 0x917c
2775/* [RW 1] Type A VF enable inbound interrupt table for USDM. 0 - disable; 1
2776 * - enable. */
2777#define PGLUE_B_REG_USDM_INB_INT_A_VF_ENABLE 0x9180
2778/* [RW 1] Type B VF enable inbound interrupt table for USDM. 0 - disable; 1
2779 * - enable. */
2780#define PGLUE_B_REG_USDM_INB_INT_B_VF_ENABLE 0x9184
2781/* [RW 16] Start offset of USDM zone A (queue zone) in the internal RAM */
2782#define PGLUE_B_REG_USDM_START_OFFSET_A 0x90d8
2783/* [RW 16] Start offset of USDM zone B (legacy zone) in the internal RAM */
2784#define PGLUE_B_REG_USDM_START_OFFSET_B 0x90e0
2785/* [RW 5] VF Shift of USDM zone B (legacy zone) in the internal RAM */
2786#define PGLUE_B_REG_USDM_VF_SHIFT_B 0x90e8
2787/* [RW 1] 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B. */
2788#define PGLUE_B_REG_USDM_ZONE_A_SIZE_PF 0x91a4
2789/* [R 26] Details of first target VF request accessing VF GRC space that
2790 * failed permission check. [14:0] Address. [15] w_nr: 0 - Read; 1 - Write.
2791 * [21:16] VFID. [24:22] - PFID. [25] valid - indicates if there was a
2792 * request accessing VF GRC space that failed permission check since the
2793 * last time this register was cleared. Permission checks are: function
2794 * permission; R/W permission; address range permission. */
2795#define PGLUE_B_REG_VF_GRC_SPACE_VIOLATION_DETAILS 0x9234
2796/* [R 31] Details of first target VF request with length violation (too many
2797 * DWs) accessing BAR0. [12:0] Address in DWs (bits [14:2] of byte address).
2798 * [14:13] BAR. [20:15] VFID. [23:21] - PFID. [29:24] - Length in DWs. [30]
2799 * valid - indicates if there was a request with length violation since the
2800 * last time this register was cleared. Length violations: length of more
2801 * than 2DWs; length of 2DWs and address not QW aligned; window is GRC and
2802 * length is more than 1 DW. */
2803#define PGLUE_B_REG_VF_LENGTH_VIOLATION_DETAILS 0x9230
2804/* [R 8] Was_error indication dirty bits for PFs 0 to 7. Each bit indicates
2805 * that there was a completion with uncorrectable error for the
2806 * corresponding PF. Set by PXP. Reset by MCP writing 1 to
2807 * was_error_pf_7_0_clr. */
2808#define PGLUE_B_REG_WAS_ERROR_PF_7_0 0x907c
2809/* [W 8] Was_error indication dirty bits clear for PFs 0 to 7. MCP writes 1
2810 * to a bit in this register in order to clear the corresponding bit in
2811 * flr_request_pf_7_0 register. */
2812#define PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR 0x9470
2813/* [R 32] Was_error indication dirty bits for VFs 96 to 127. Each bit
2814 * indicates that there was a completion with uncorrectable error for the
2815 * corresponding VF. Set by PXP. Reset by MCP writing 1 to
2816 * was_error_vf_127_96_clr. */
2817#define PGLUE_B_REG_WAS_ERROR_VF_127_96 0x9078
2818/* [W 32] Was_error indication dirty bits clear for VFs 96 to 127. MCP
2819 * writes 1 to a bit in this register in order to clear the corresponding
2820 * bit in was_error_vf_127_96 register. */
2821#define PGLUE_B_REG_WAS_ERROR_VF_127_96_CLR 0x9474
2822/* [R 32] Was_error indication dirty bits for VFs 0 to 31. Each bit
2823 * indicates that there was a completion with uncorrectable error for the
2824 * corresponding VF. Set by PXP. Reset by MCP writing 1 to
2825 * was_error_vf_31_0_clr. */
2826#define PGLUE_B_REG_WAS_ERROR_VF_31_0 0x906c
2827/* [W 32] Was_error indication dirty bits clear for VFs 0 to 31. MCP writes
2828 * 1 to a bit in this register in order to clear the corresponding bit in
2829 * was_error_vf_31_0 register. */
2830#define PGLUE_B_REG_WAS_ERROR_VF_31_0_CLR 0x9478
2831/* [R 32] Was_error indication dirty bits for VFs 32 to 63. Each bit
2832 * indicates that there was a completion with uncorrectable error for the
2833 * corresponding VF. Set by PXP. Reset by MCP writing 1 to
2834 * was_error_vf_63_32_clr. */
2835#define PGLUE_B_REG_WAS_ERROR_VF_63_32 0x9070
2836/* [W 32] Was_error indication dirty bits clear for VFs 32 to 63. MCP writes
2837 * 1 to a bit in this register in order to clear the corresponding bit in
2838 * was_error_vf_63_32 register. */
2839#define PGLUE_B_REG_WAS_ERROR_VF_63_32_CLR 0x947c
2840/* [R 32] Was_error indication dirty bits for VFs 64 to 95. Each bit
2841 * indicates that there was a completion with uncorrectable error for the
2842 * corresponding VF. Set by PXP. Reset by MCP writing 1 to
2843 * was_error_vf_95_64_clr. */
2844#define PGLUE_B_REG_WAS_ERROR_VF_95_64 0x9074
2845/* [W 32] Was_error indication dirty bits clear for VFs 64 to 95. MCP writes
2846 * 1 to a bit in this register in order to clear the corresponding bit in
2847 * was_error_vf_95_64 register. */
2848#define PGLUE_B_REG_WAS_ERROR_VF_95_64_CLR 0x9480
2849/* [RW 1] Type A PF enable inbound interrupt table for XSDM. 0 - disable; 1
2850 * - enable. */
2851#define PGLUE_B_REG_XSDM_INB_INT_A_PF_ENABLE 0x9188
2852/* [RW 16] Start offset of XSDM zone A (queue zone) in the internal RAM */
2853#define PGLUE_B_REG_XSDM_START_OFFSET_A 0x90ec
2854/* [RW 16] Start offset of XSDM zone B (legacy zone) in the internal RAM */
2855#define PGLUE_B_REG_XSDM_START_OFFSET_B 0x90f4
2856/* [RW 5] VF Shift of XSDM zone B (legacy zone) in the internal RAM */
2857#define PGLUE_B_REG_XSDM_VF_SHIFT_B 0x90fc
2858/* [RW 1] 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B. */
2859#define PGLUE_B_REG_XSDM_ZONE_A_SIZE_PF 0x91a8
2860#define PRS_REG_A_PRSU_20 0x40134
2861/* [R 8] debug only: CFC load request current credit. Transaction based. */
2862#define PRS_REG_CFC_LD_CURRENT_CREDIT 0x40164
2863/* [R 8] debug only: CFC search request current credit. Transaction based. */
2864#define PRS_REG_CFC_SEARCH_CURRENT_CREDIT 0x40168
2865/* [RW 6] The initial credit for the search message to the CFC interface.
2866 Credit is transaction based. */
2867#define PRS_REG_CFC_SEARCH_INITIAL_CREDIT 0x4011c
2868/* [RW 24] CID for port 0 if no match */
2869#define PRS_REG_CID_PORT_0 0x400fc
2870/* [RW 32] The CM header for flush message where 'load existed' bit in CFC
2871 load response is reset and packet type is 0. Used in packet start message
2872 to TCM. */
2873#define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_0 0x400dc
2874#define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_1 0x400e0
2875#define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_2 0x400e4
2876#define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_3 0x400e8
2877#define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_4 0x400ec
2878#define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_5 0x400f0
2879/* [RW 32] The CM header for flush message where 'load existed' bit in CFC
2880 load response is set and packet type is 0. Used in packet start message
2881 to TCM. */
2882#define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_0 0x400bc
2883#define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_1 0x400c0
2884#define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_2 0x400c4
2885#define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_3 0x400c8
2886#define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_4 0x400cc
2887#define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_5 0x400d0
2888/* [RW 32] The CM header for a match and packet type 1 for loopback port.
2889 Used in packet start message to TCM. */
2890#define PRS_REG_CM_HDR_LOOPBACK_TYPE_1 0x4009c
2891#define PRS_REG_CM_HDR_LOOPBACK_TYPE_2 0x400a0
2892#define PRS_REG_CM_HDR_LOOPBACK_TYPE_3 0x400a4
2893#define PRS_REG_CM_HDR_LOOPBACK_TYPE_4 0x400a8
2894/* [RW 32] The CM header for a match and packet type 0. Used in packet start
2895 message to TCM. */
2896#define PRS_REG_CM_HDR_TYPE_0 0x40078
2897#define PRS_REG_CM_HDR_TYPE_1 0x4007c
2898#define PRS_REG_CM_HDR_TYPE_2 0x40080
2899#define PRS_REG_CM_HDR_TYPE_3 0x40084
2900#define PRS_REG_CM_HDR_TYPE_4 0x40088
2901/* [RW 32] The CM header in case there was not a match on the connection */
2902#define PRS_REG_CM_NO_MATCH_HDR 0x400b8
2903/* [RW 1] Indicates if in e1hov mode. 0=non-e1hov mode; 1=e1hov mode. */
2904#define PRS_REG_E1HOV_MODE 0x401c8
2905/* [RW 8] The 8-bit event ID for a match and packet type 1. Used in packet
2906 start message to TCM. */
2907#define PRS_REG_EVENT_ID_1 0x40054
2908#define PRS_REG_EVENT_ID_2 0x40058
2909#define PRS_REG_EVENT_ID_3 0x4005c
2910/* [RW 16] The Ethernet type value for FCoE */
2911#define PRS_REG_FCOE_TYPE 0x401d0
2912/* [RW 8] Context region for flush packet with packet type 0. Used in CFC
2913 load request message. */
2914#define PRS_REG_FLUSH_REGIONS_TYPE_0 0x40004
2915#define PRS_REG_FLUSH_REGIONS_TYPE_1 0x40008
2916#define PRS_REG_FLUSH_REGIONS_TYPE_2 0x4000c
2917#define PRS_REG_FLUSH_REGIONS_TYPE_3 0x40010
2918#define PRS_REG_FLUSH_REGIONS_TYPE_4 0x40014
2919#define PRS_REG_FLUSH_REGIONS_TYPE_5 0x40018
2920#define PRS_REG_FLUSH_REGIONS_TYPE_6 0x4001c
2921#define PRS_REG_FLUSH_REGIONS_TYPE_7 0x40020
2922/* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic
2923 * Ethernet header. */
2924#define PRS_REG_HDRS_AFTER_BASIC 0x40238
2925/* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic
2926 * Ethernet header for port 0 packets. */
2927#define PRS_REG_HDRS_AFTER_BASIC_PORT_0 0x40270
2928#define PRS_REG_HDRS_AFTER_BASIC_PORT_1 0x40290
2929/* [R 6] Bit-map indicating which L2 hdrs may appear after L2 tag 0 */
2930#define PRS_REG_HDRS_AFTER_TAG_0 0x40248
2931/* [RW 6] Bit-map indicating which L2 hdrs may appear after L2 tag 0 for
2932 * port 0 packets */
2933#define PRS_REG_HDRS_AFTER_TAG_0_PORT_0 0x40280
2934#define PRS_REG_HDRS_AFTER_TAG_0_PORT_1 0x402a0
2935/* [RW 4] The increment value to send in the CFC load request message */
2936#define PRS_REG_INC_VALUE 0x40048
2937/* [RW 6] Bit-map indicating which headers must appear in the packet */
2938#define PRS_REG_MUST_HAVE_HDRS 0x40254
2939/* [RW 6] Bit-map indicating which headers must appear in the packet for
2940 * port 0 packets */
2941#define PRS_REG_MUST_HAVE_HDRS_PORT_0 0x4028c
2942#define PRS_REG_MUST_HAVE_HDRS_PORT_1 0x402ac
2943#define PRS_REG_NIC_MODE 0x40138
2944/* [RW 8] The 8-bit event ID for cases where there is no match on the
2945 connection. Used in packet start message to TCM. */
2946#define PRS_REG_NO_MATCH_EVENT_ID 0x40070
2947/* [ST 24] The number of input CFC flush packets */
2948#define PRS_REG_NUM_OF_CFC_FLUSH_MESSAGES 0x40128
2949/* [ST 32] The number of cycles the Parser halted its operation since it
2950 could not allocate the next serial number */
2951#define PRS_REG_NUM_OF_DEAD_CYCLES 0x40130
2952/* [ST 24] The number of input packets */
2953#define PRS_REG_NUM_OF_PACKETS 0x40124
2954/* [ST 24] The number of input transparent flush packets */
2955#define PRS_REG_NUM_OF_TRANSPARENT_FLUSH_MESSAGES 0x4012c
2956/* [RW 8] Context region for received Ethernet packet with a match and
2957 packet type 0. Used in CFC load request message */
2958#define PRS_REG_PACKET_REGIONS_TYPE_0 0x40028
2959#define PRS_REG_PACKET_REGIONS_TYPE_1 0x4002c
2960#define PRS_REG_PACKET_REGIONS_TYPE_2 0x40030
2961#define PRS_REG_PACKET_REGIONS_TYPE_3 0x40034
2962#define PRS_REG_PACKET_REGIONS_TYPE_4 0x40038
2963#define PRS_REG_PACKET_REGIONS_TYPE_5 0x4003c
2964#define PRS_REG_PACKET_REGIONS_TYPE_6 0x40040
2965#define PRS_REG_PACKET_REGIONS_TYPE_7 0x40044
2966/* [R 2] debug only: Number of pending requests for CAC on port 0. */
2967#define PRS_REG_PENDING_BRB_CAC0_RQ 0x40174
2968/* [R 2] debug only: Number of pending requests for header parsing. */
2969#define PRS_REG_PENDING_BRB_PRS_RQ 0x40170
2970/* [R 1] Interrupt register #0 read */
2971#define PRS_REG_PRS_INT_STS 0x40188
2972/* [RW 8] Parity mask register #0 read/write */
2973#define PRS_REG_PRS_PRTY_MASK 0x401a4
2974/* [R 8] Parity register #0 read */
2975#define PRS_REG_PRS_PRTY_STS 0x40198
2976/* [RC 8] Parity register #0 read clear */
2977#define PRS_REG_PRS_PRTY_STS_CLR 0x4019c
2978/* [RW 8] Context region for pure acknowledge packets. Used in CFC load
2979 request message */
2980#define PRS_REG_PURE_REGIONS 0x40024
2981/* [R 32] debug only: Serial number status lsb 32 bits. '1' indicates this
2982 serail number was released by SDM but cannot be used because a previous
2983 serial number was not released. */
2984#define PRS_REG_SERIAL_NUM_STATUS_LSB 0x40154
2985/* [R 32] debug only: Serial number status msb 32 bits. '1' indicates this
2986 serail number was released by SDM but cannot be used because a previous
2987 serial number was not released. */
2988#define PRS_REG_SERIAL_NUM_STATUS_MSB 0x40158
2989/* [R 4] debug only: SRC current credit. Transaction based. */
2990#define PRS_REG_SRC_CURRENT_CREDIT 0x4016c
2991/* [RW 16] The Ethernet type value for L2 tag 0 */
2992#define PRS_REG_TAG_ETHERTYPE_0 0x401d4
2993/* [RW 4] The length of the info field for L2 tag 0. The length is between
2994 * 2B and 14B; in 2B granularity */
2995#define PRS_REG_TAG_LEN_0 0x4022c
2996/* [R 8] debug only: TCM current credit. Cycle based. */
2997#define PRS_REG_TCM_CURRENT_CREDIT 0x40160
2998/* [R 8] debug only: TSDM current credit. Transaction based. */
2999#define PRS_REG_TSDM_CURRENT_CREDIT 0x4015c
3000#define PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT (0x1<<19)
3001#define PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF (0x1<<20)
3002#define PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN (0x1<<22)
3003#define PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED (0x1<<23)
3004#define PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED (0x1<<24)
3005#define PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR (0x1<<7)
3006#define PXP2_PXP2_INT_STS_CLR_0_REG_WR_PGLUE_EOP_ERROR (0x1<<7)
3007/* [R 6] Debug only: Number of used entries in the data FIFO */
3008#define PXP2_REG_HST_DATA_FIFO_STATUS 0x12047c
3009/* [R 7] Debug only: Number of used entries in the header FIFO */
3010#define PXP2_REG_HST_HEADER_FIFO_STATUS 0x120478
3011#define PXP2_REG_PGL_ADDR_88_F0 0x120534
3012#define PXP2_REG_PGL_ADDR_8C_F0 0x120538
3013#define PXP2_REG_PGL_ADDR_90_F0 0x12053c
3014#define PXP2_REG_PGL_ADDR_94_F0 0x120540
3015#define PXP2_REG_PGL_CONTROL0 0x120490
3016#define PXP2_REG_PGL_CONTROL1 0x120514
3017#define PXP2_REG_PGL_DEBUG 0x120520
3018/* [RW 32] third dword data of expansion rom request. this register is
3019 special. reading from it provides a vector outstanding read requests. if
3020 a bit is zero it means that a read request on the corresponding tag did
3021 not finish yet (not all completions have arrived for it) */
3022#define PXP2_REG_PGL_EXP_ROM2 0x120808
3023/* [RW 32] Inbound interrupt table for CSDM: bits[31:16]-mask;
3024 its[15:0]-address */
3025#define PXP2_REG_PGL_INT_CSDM_0 0x1204f4
3026#define PXP2_REG_PGL_INT_CSDM_1 0x1204f8
3027#define PXP2_REG_PGL_INT_CSDM_2 0x1204fc
3028#define PXP2_REG_PGL_INT_CSDM_3 0x120500
3029#define PXP2_REG_PGL_INT_CSDM_4 0x120504
3030#define PXP2_REG_PGL_INT_CSDM_5 0x120508
3031#define PXP2_REG_PGL_INT_CSDM_6 0x12050c
3032#define PXP2_REG_PGL_INT_CSDM_7 0x120510
3033/* [RW 32] Inbound interrupt table for TSDM: bits[31:16]-mask;
3034 its[15:0]-address */
3035#define PXP2_REG_PGL_INT_TSDM_0 0x120494
3036#define PXP2_REG_PGL_INT_TSDM_1 0x120498
3037#define PXP2_REG_PGL_INT_TSDM_2 0x12049c
3038#define PXP2_REG_PGL_INT_TSDM_3 0x1204a0
3039#define PXP2_REG_PGL_INT_TSDM_4 0x1204a4
3040#define PXP2_REG_PGL_INT_TSDM_5 0x1204a8
3041#define PXP2_REG_PGL_INT_TSDM_6 0x1204ac
3042#define PXP2_REG_PGL_INT_TSDM_7 0x1204b0
3043/* [RW 32] Inbound interrupt table for USDM: bits[31:16]-mask;
3044 its[15:0]-address */
3045#define PXP2_REG_PGL_INT_USDM_0 0x1204b4
3046#define PXP2_REG_PGL_INT_USDM_1 0x1204b8
3047#define PXP2_REG_PGL_INT_USDM_2 0x1204bc
3048#define PXP2_REG_PGL_INT_USDM_3 0x1204c0
3049#define PXP2_REG_PGL_INT_USDM_4 0x1204c4
3050#define PXP2_REG_PGL_INT_USDM_5 0x1204c8
3051#define PXP2_REG_PGL_INT_USDM_6 0x1204cc
3052#define PXP2_REG_PGL_INT_USDM_7 0x1204d0
3053/* [RW 32] Inbound interrupt table for XSDM: bits[31:16]-mask;
3054 its[15:0]-address */
3055#define PXP2_REG_PGL_INT_XSDM_0 0x1204d4
3056#define PXP2_REG_PGL_INT_XSDM_1 0x1204d8
3057#define PXP2_REG_PGL_INT_XSDM_2 0x1204dc
3058#define PXP2_REG_PGL_INT_XSDM_3 0x1204e0
3059#define PXP2_REG_PGL_INT_XSDM_4 0x1204e4
3060#define PXP2_REG_PGL_INT_XSDM_5 0x1204e8
3061#define PXP2_REG_PGL_INT_XSDM_6 0x1204ec
3062#define PXP2_REG_PGL_INT_XSDM_7 0x1204f0
3063/* [RW 3] this field allows one function to pretend being another function
3064 when accessing any BAR mapped resource within the device. the value of
3065 the field is the number of the function that will be accessed
3066 effectively. after software write to this bit it must read it in order to
3067 know that the new value is updated */
3068#define PXP2_REG_PGL_PRETEND_FUNC_F0 0x120674
3069#define PXP2_REG_PGL_PRETEND_FUNC_F1 0x120678
3070#define PXP2_REG_PGL_PRETEND_FUNC_F2 0x12067c
3071#define PXP2_REG_PGL_PRETEND_FUNC_F3 0x120680
3072#define PXP2_REG_PGL_PRETEND_FUNC_F4 0x120684
3073#define PXP2_REG_PGL_PRETEND_FUNC_F5 0x120688
3074#define PXP2_REG_PGL_PRETEND_FUNC_F6 0x12068c
3075#define PXP2_REG_PGL_PRETEND_FUNC_F7 0x120690
3076/* [R 1] this bit indicates that a read request was blocked because of
3077 bus_master_en was deasserted */
3078#define PXP2_REG_PGL_READ_BLOCKED 0x120568
3079#define PXP2_REG_PGL_TAGS_LIMIT 0x1205a8
3080/* [R 18] debug only */
3081#define PXP2_REG_PGL_TXW_CDTS 0x12052c
3082/* [R 1] this bit indicates that a write request was blocked because of
3083 bus_master_en was deasserted */
3084#define PXP2_REG_PGL_WRITE_BLOCKED 0x120564
3085#define PXP2_REG_PSWRQ_BW_ADD1 0x1201c0
3086#define PXP2_REG_PSWRQ_BW_ADD10 0x1201e4
3087#define PXP2_REG_PSWRQ_BW_ADD11 0x1201e8
3088#define PXP2_REG_PSWRQ_BW_ADD2 0x1201c4
3089#define PXP2_REG_PSWRQ_BW_ADD28 0x120228
3090#define PXP2_REG_PSWRQ_BW_ADD3 0x1201c8
3091#define PXP2_REG_PSWRQ_BW_ADD6 0x1201d4
3092#define PXP2_REG_PSWRQ_BW_ADD7 0x1201d8
3093#define PXP2_REG_PSWRQ_BW_ADD8 0x1201dc
3094#define PXP2_REG_PSWRQ_BW_ADD9 0x1201e0
3095#define PXP2_REG_PSWRQ_BW_CREDIT 0x12032c
3096#define PXP2_REG_PSWRQ_BW_L1 0x1202b0
3097#define PXP2_REG_PSWRQ_BW_L10 0x1202d4
3098#define PXP2_REG_PSWRQ_BW_L11 0x1202d8
3099#define PXP2_REG_PSWRQ_BW_L2 0x1202b4
3100#define PXP2_REG_PSWRQ_BW_L28 0x120318
3101#define PXP2_REG_PSWRQ_BW_L3 0x1202b8
3102#define PXP2_REG_PSWRQ_BW_L6 0x1202c4
3103#define PXP2_REG_PSWRQ_BW_L7 0x1202c8
3104#define PXP2_REG_PSWRQ_BW_L8 0x1202cc
3105#define PXP2_REG_PSWRQ_BW_L9 0x1202d0
3106#define PXP2_REG_PSWRQ_BW_RD 0x120324
3107#define PXP2_REG_PSWRQ_BW_UB1 0x120238
3108#define PXP2_REG_PSWRQ_BW_UB10 0x12025c
3109#define PXP2_REG_PSWRQ_BW_UB11 0x120260
3110#define PXP2_REG_PSWRQ_BW_UB2 0x12023c
3111#define PXP2_REG_PSWRQ_BW_UB28 0x1202a0
3112#define PXP2_REG_PSWRQ_BW_UB3 0x120240
3113#define PXP2_REG_PSWRQ_BW_UB6 0x12024c
3114#define PXP2_REG_PSWRQ_BW_UB7 0x120250
3115#define PXP2_REG_PSWRQ_BW_UB8 0x120254
3116#define PXP2_REG_PSWRQ_BW_UB9 0x120258
3117#define PXP2_REG_PSWRQ_BW_WR 0x120328
3118#define PXP2_REG_PSWRQ_CDU0_L2P 0x120000
3119#define PXP2_REG_PSWRQ_QM0_L2P 0x120038
3120#define PXP2_REG_PSWRQ_SRC0_L2P 0x120054
3121#define PXP2_REG_PSWRQ_TM0_L2P 0x12001c
3122#define PXP2_REG_PSWRQ_TSDM0_L2P 0x1200e0
3123/* [RW 32] Interrupt mask register #0 read/write */
3124#define PXP2_REG_PXP2_INT_MASK_0 0x120578
3125/* [R 32] Interrupt register #0 read */
3126#define PXP2_REG_PXP2_INT_STS_0 0x12056c
3127#define PXP2_REG_PXP2_INT_STS_1 0x120608
3128/* [RC 32] Interrupt register #0 read clear */
3129#define PXP2_REG_PXP2_INT_STS_CLR_0 0x120570
3130/* [RW 32] Parity mask register #0 read/write */
3131#define PXP2_REG_PXP2_PRTY_MASK_0 0x120588
3132#define PXP2_REG_PXP2_PRTY_MASK_1 0x120598
3133/* [R 32] Parity register #0 read */
3134#define PXP2_REG_PXP2_PRTY_STS_0 0x12057c
3135#define PXP2_REG_PXP2_PRTY_STS_1 0x12058c
3136/* [RC 32] Parity register #0 read clear */
3137#define PXP2_REG_PXP2_PRTY_STS_CLR_0 0x120580
3138#define PXP2_REG_PXP2_PRTY_STS_CLR_1 0x120590
3139/* [R 1] Debug only: The 'almost full' indication from each fifo (gives
3140 indication about backpressure) */
3141#define PXP2_REG_RD_ALMOST_FULL_0 0x120424
3142/* [R 8] Debug only: The blocks counter - number of unused block ids */
3143#define PXP2_REG_RD_BLK_CNT 0x120418
3144/* [RW 8] Debug only: Total number of available blocks in Tetris Buffer.
3145 Must be bigger than 6. Normally should not be changed. */
3146#define PXP2_REG_RD_BLK_NUM_CFG 0x12040c
3147/* [RW 2] CDU byte swapping mode configuration for master read requests */
3148#define PXP2_REG_RD_CDURD_SWAP_MODE 0x120404
3149/* [RW 1] When '1'; inputs to the PSWRD block are ignored */
3150#define PXP2_REG_RD_DISABLE_INPUTS 0x120374
3151/* [R 1] PSWRD internal memories initialization is done */
3152#define PXP2_REG_RD_INIT_DONE 0x120370
3153/* [RW 8] The maximum number of blocks in Tetris Buffer that can be
3154 allocated for vq10 */
3155#define PXP2_REG_RD_MAX_BLKS_VQ10 0x1203a0
3156/* [RW 8] The maximum number of blocks in Tetris Buffer that can be
3157 allocated for vq11 */
3158#define PXP2_REG_RD_MAX_BLKS_VQ11 0x1203a4
3159/* [RW 8] The maximum number of blocks in Tetris Buffer that can be
3160 allocated for vq17 */
3161#define PXP2_REG_RD_MAX_BLKS_VQ17 0x1203bc
3162/* [RW 8] The maximum number of blocks in Tetris Buffer that can be
3163 allocated for vq18 */
3164#define PXP2_REG_RD_MAX_BLKS_VQ18 0x1203c0
3165/* [RW 8] The maximum number of blocks in Tetris Buffer that can be
3166 allocated for vq19 */
3167#define PXP2_REG_RD_MAX_BLKS_VQ19 0x1203c4
3168/* [RW 8] The maximum number of blocks in Tetris Buffer that can be
3169 allocated for vq22 */
3170#define PXP2_REG_RD_MAX_BLKS_VQ22 0x1203d0
3171/* [RW 8] The maximum number of blocks in Tetris Buffer that can be
3172 allocated for vq25 */
3173#define PXP2_REG_RD_MAX_BLKS_VQ25 0x1203dc
3174/* [RW 8] The maximum number of blocks in Tetris Buffer that can be
3175 allocated for vq6 */
3176#define PXP2_REG_RD_MAX_BLKS_VQ6 0x120390
3177/* [RW 8] The maximum number of blocks in Tetris Buffer that can be
3178 allocated for vq9 */
3179#define PXP2_REG_RD_MAX_BLKS_VQ9 0x12039c
3180/* [RW 2] PBF byte swapping mode configuration for master read requests */
3181#define PXP2_REG_RD_PBF_SWAP_MODE 0x1203f4
3182/* [R 1] Debug only: Indication if delivery ports are idle */
3183#define PXP2_REG_RD_PORT_IS_IDLE_0 0x12041c
3184#define PXP2_REG_RD_PORT_IS_IDLE_1 0x120420
3185/* [RW 2] QM byte swapping mode configuration for master read requests */
3186#define PXP2_REG_RD_QM_SWAP_MODE 0x1203f8
3187/* [R 7] Debug only: The SR counter - number of unused sub request ids */
3188#define PXP2_REG_RD_SR_CNT 0x120414
3189/* [RW 2] SRC byte swapping mode configuration for master read requests */
3190#define PXP2_REG_RD_SRC_SWAP_MODE 0x120400
3191/* [RW 7] Debug only: Total number of available PCI read sub-requests. Must
3192 be bigger than 1. Normally should not be changed. */
3193#define PXP2_REG_RD_SR_NUM_CFG 0x120408
3194/* [RW 1] Signals the PSWRD block to start initializing internal memories */
3195#define PXP2_REG_RD_START_INIT 0x12036c
3196/* [RW 2] TM byte swapping mode configuration for master read requests */
3197#define PXP2_REG_RD_TM_SWAP_MODE 0x1203fc
3198/* [RW 10] Bandwidth addition to VQ0 write requests */
3199#define PXP2_REG_RQ_BW_RD_ADD0 0x1201bc
3200/* [RW 10] Bandwidth addition to VQ12 read requests */
3201#define PXP2_REG_RQ_BW_RD_ADD12 0x1201ec
3202/* [RW 10] Bandwidth addition to VQ13 read requests */
3203#define PXP2_REG_RQ_BW_RD_ADD13 0x1201f0
3204/* [RW 10] Bandwidth addition to VQ14 read requests */
3205#define PXP2_REG_RQ_BW_RD_ADD14 0x1201f4
3206/* [RW 10] Bandwidth addition to VQ15 read requests */
3207#define PXP2_REG_RQ_BW_RD_ADD15 0x1201f8
3208/* [RW 10] Bandwidth addition to VQ16 read requests */
3209#define PXP2_REG_RQ_BW_RD_ADD16 0x1201fc
3210/* [RW 10] Bandwidth addition to VQ17 read requests */
3211#define PXP2_REG_RQ_BW_RD_ADD17 0x120200
3212/* [RW 10] Bandwidth addition to VQ18 read requests */
3213#define PXP2_REG_RQ_BW_RD_ADD18 0x120204
3214/* [RW 10] Bandwidth addition to VQ19 read requests */
3215#define PXP2_REG_RQ_BW_RD_ADD19 0x120208
3216/* [RW 10] Bandwidth addition to VQ20 read requests */
3217#define PXP2_REG_RQ_BW_RD_ADD20 0x12020c
3218/* [RW 10] Bandwidth addition to VQ22 read requests */
3219#define PXP2_REG_RQ_BW_RD_ADD22 0x120210
3220/* [RW 10] Bandwidth addition to VQ23 read requests */
3221#define PXP2_REG_RQ_BW_RD_ADD23 0x120214
3222/* [RW 10] Bandwidth addition to VQ24 read requests */
3223#define PXP2_REG_RQ_BW_RD_ADD24 0x120218
3224/* [RW 10] Bandwidth addition to VQ25 read requests */
3225#define PXP2_REG_RQ_BW_RD_ADD25 0x12021c
3226/* [RW 10] Bandwidth addition to VQ26 read requests */
3227#define PXP2_REG_RQ_BW_RD_ADD26 0x120220
3228/* [RW 10] Bandwidth addition to VQ27 read requests */
3229#define PXP2_REG_RQ_BW_RD_ADD27 0x120224
3230/* [RW 10] Bandwidth addition to VQ4 read requests */
3231#define PXP2_REG_RQ_BW_RD_ADD4 0x1201cc
3232/* [RW 10] Bandwidth addition to VQ5 read requests */
3233#define PXP2_REG_RQ_BW_RD_ADD5 0x1201d0
3234/* [RW 10] Bandwidth Typical L for VQ0 Read requests */
3235#define PXP2_REG_RQ_BW_RD_L0 0x1202ac
3236/* [RW 10] Bandwidth Typical L for VQ12 Read requests */
3237#define PXP2_REG_RQ_BW_RD_L12 0x1202dc
3238/* [RW 10] Bandwidth Typical L for VQ13 Read requests */
3239#define PXP2_REG_RQ_BW_RD_L13 0x1202e0
3240/* [RW 10] Bandwidth Typical L for VQ14 Read requests */
3241#define PXP2_REG_RQ_BW_RD_L14 0x1202e4
3242/* [RW 10] Bandwidth Typical L for VQ15 Read requests */
3243#define PXP2_REG_RQ_BW_RD_L15 0x1202e8
3244/* [RW 10] Bandwidth Typical L for VQ16 Read requests */
3245#define PXP2_REG_RQ_BW_RD_L16 0x1202ec
3246/* [RW 10] Bandwidth Typical L for VQ17 Read requests */
3247#define PXP2_REG_RQ_BW_RD_L17 0x1202f0
3248/* [RW 10] Bandwidth Typical L for VQ18 Read requests */
3249#define PXP2_REG_RQ_BW_RD_L18 0x1202f4
3250/* [RW 10] Bandwidth Typical L for VQ19 Read requests */
3251#define PXP2_REG_RQ_BW_RD_L19 0x1202f8
3252/* [RW 10] Bandwidth Typical L for VQ20 Read requests */
3253#define PXP2_REG_RQ_BW_RD_L20 0x1202fc
3254/* [RW 10] Bandwidth Typical L for VQ22 Read requests */
3255#define PXP2_REG_RQ_BW_RD_L22 0x120300
3256/* [RW 10] Bandwidth Typical L for VQ23 Read requests */
3257#define PXP2_REG_RQ_BW_RD_L23 0x120304
3258/* [RW 10] Bandwidth Typical L for VQ24 Read requests */
3259#define PXP2_REG_RQ_BW_RD_L24 0x120308
3260/* [RW 10] Bandwidth Typical L for VQ25 Read requests */
3261#define PXP2_REG_RQ_BW_RD_L25 0x12030c
3262/* [RW 10] Bandwidth Typical L for VQ26 Read requests */
3263#define PXP2_REG_RQ_BW_RD_L26 0x120310
3264/* [RW 10] Bandwidth Typical L for VQ27 Read requests */
3265#define PXP2_REG_RQ_BW_RD_L27 0x120314
3266/* [RW 10] Bandwidth Typical L for VQ4 Read requests */
3267#define PXP2_REG_RQ_BW_RD_L4 0x1202bc
3268/* [RW 10] Bandwidth Typical L for VQ5 Read- currently not used */
3269#define PXP2_REG_RQ_BW_RD_L5 0x1202c0
3270/* [RW 7] Bandwidth upper bound for VQ0 read requests */
3271#define PXP2_REG_RQ_BW_RD_UBOUND0 0x120234
3272/* [RW 7] Bandwidth upper bound for VQ12 read requests */
3273#define PXP2_REG_RQ_BW_RD_UBOUND12 0x120264
3274/* [RW 7] Bandwidth upper bound for VQ13 read requests */
3275#define PXP2_REG_RQ_BW_RD_UBOUND13 0x120268
3276/* [RW 7] Bandwidth upper bound for VQ14 read requests */
3277#define PXP2_REG_RQ_BW_RD_UBOUND14 0x12026c
3278/* [RW 7] Bandwidth upper bound for VQ15 read requests */
3279#define PXP2_REG_RQ_BW_RD_UBOUND15 0x120270
3280/* [RW 7] Bandwidth upper bound for VQ16 read requests */
3281#define PXP2_REG_RQ_BW_RD_UBOUND16 0x120274
3282/* [RW 7] Bandwidth upper bound for VQ17 read requests */
3283#define PXP2_REG_RQ_BW_RD_UBOUND17 0x120278
3284/* [RW 7] Bandwidth upper bound for VQ18 read requests */
3285#define PXP2_REG_RQ_BW_RD_UBOUND18 0x12027c
3286/* [RW 7] Bandwidth upper bound for VQ19 read requests */
3287#define PXP2_REG_RQ_BW_RD_UBOUND19 0x120280
3288/* [RW 7] Bandwidth upper bound for VQ20 read requests */
3289#define PXP2_REG_RQ_BW_RD_UBOUND20 0x120284
3290/* [RW 7] Bandwidth upper bound for VQ22 read requests */
3291#define PXP2_REG_RQ_BW_RD_UBOUND22 0x120288
3292/* [RW 7] Bandwidth upper bound for VQ23 read requests */
3293#define PXP2_REG_RQ_BW_RD_UBOUND23 0x12028c
3294/* [RW 7] Bandwidth upper bound for VQ24 read requests */
3295#define PXP2_REG_RQ_BW_RD_UBOUND24 0x120290
3296/* [RW 7] Bandwidth upper bound for VQ25 read requests */
3297#define PXP2_REG_RQ_BW_RD_UBOUND25 0x120294
3298/* [RW 7] Bandwidth upper bound for VQ26 read requests */
3299#define PXP2_REG_RQ_BW_RD_UBOUND26 0x120298
3300/* [RW 7] Bandwidth upper bound for VQ27 read requests */
3301#define PXP2_REG_RQ_BW_RD_UBOUND27 0x12029c
3302/* [RW 7] Bandwidth upper bound for VQ4 read requests */
3303#define PXP2_REG_RQ_BW_RD_UBOUND4 0x120244
3304/* [RW 7] Bandwidth upper bound for VQ5 read requests */
3305#define PXP2_REG_RQ_BW_RD_UBOUND5 0x120248
3306/* [RW 10] Bandwidth addition to VQ29 write requests */
3307#define PXP2_REG_RQ_BW_WR_ADD29 0x12022c
3308/* [RW 10] Bandwidth addition to VQ30 write requests */
3309#define PXP2_REG_RQ_BW_WR_ADD30 0x120230
3310/* [RW 10] Bandwidth Typical L for VQ29 Write requests */
3311#define PXP2_REG_RQ_BW_WR_L29 0x12031c
3312/* [RW 10] Bandwidth Typical L for VQ30 Write requests */
3313#define PXP2_REG_RQ_BW_WR_L30 0x120320
3314/* [RW 7] Bandwidth upper bound for VQ29 */
3315#define PXP2_REG_RQ_BW_WR_UBOUND29 0x1202a4
3316/* [RW 7] Bandwidth upper bound for VQ30 */
3317#define PXP2_REG_RQ_BW_WR_UBOUND30 0x1202a8
3318/* [RW 18] external first_mem_addr field in L2P table for CDU module port 0 */
3319#define PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR 0x120008
3320/* [RW 2] Endian mode for cdu */
3321#define PXP2_REG_RQ_CDU_ENDIAN_M 0x1201a0
3322#define PXP2_REG_RQ_CDU_FIRST_ILT 0x12061c
3323#define PXP2_REG_RQ_CDU_LAST_ILT 0x120620
3324/* [RW 3] page size in L2P table for CDU module; -4k; -8k; -16k; -32k; -64k;
3325 -128k */
3326#define PXP2_REG_RQ_CDU_P_SIZE 0x120018
3327/* [R 1] 1' indicates that the requester has finished its internal
3328 configuration */
3329#define PXP2_REG_RQ_CFG_DONE 0x1201b4
3330/* [RW 2] Endian mode for debug */
3331#define PXP2_REG_RQ_DBG_ENDIAN_M 0x1201a4
3332/* [RW 1] When '1'; requests will enter input buffers but wont get out
3333 towards the glue */
3334#define PXP2_REG_RQ_DISABLE_INPUTS 0x120330
3335/* [RW 4] Determines alignment of write SRs when a request is split into
3336 * several SRs. 0 - 8B aligned. 1 - 64B aligned. 2 - 128B aligned. 3 - 256B
3337 * aligned. 4 - 512B aligned. */
3338#define PXP2_REG_RQ_DRAM_ALIGN 0x1205b0
3339/* [RW 4] Determines alignment of read SRs when a request is split into
3340 * several SRs. 0 - 8B aligned. 1 - 64B aligned. 2 - 128B aligned. 3 - 256B
3341 * aligned. 4 - 512B aligned. */
3342#define PXP2_REG_RQ_DRAM_ALIGN_RD 0x12092c
3343/* [RW 1] when set the new alignment method (E2) will be applied; when reset
3344 * the original alignment method (E1 E1H) will be applied */
3345#define PXP2_REG_RQ_DRAM_ALIGN_SEL 0x120930
3346/* [RW 1] If 1 ILT failiue will not result in ELT access; An interrupt will
3347 be asserted */
3348#define PXP2_REG_RQ_ELT_DISABLE 0x12066c
3349/* [RW 2] Endian mode for hc */
3350#define PXP2_REG_RQ_HC_ENDIAN_M 0x1201a8
3351/* [RW 1] when '0' ILT logic will work as in A0; otherwise B0; for back
3352 compatibility needs; Note that different registers are used per mode */
3353#define PXP2_REG_RQ_ILT_MODE 0x1205b4
3354/* [WB 53] Onchip address table */
3355#define PXP2_REG_RQ_ONCHIP_AT 0x122000
3356/* [WB 53] Onchip address table - B0 */
3357#define PXP2_REG_RQ_ONCHIP_AT_B0 0x128000
3358/* [RW 13] Pending read limiter threshold; in Dwords */
3359#define PXP2_REG_RQ_PDR_LIMIT 0x12033c
3360/* [RW 2] Endian mode for qm */
3361#define PXP2_REG_RQ_QM_ENDIAN_M 0x120194
3362#define PXP2_REG_RQ_QM_FIRST_ILT 0x120634
3363#define PXP2_REG_RQ_QM_LAST_ILT 0x120638
3364/* [RW 3] page size in L2P table for QM module; -4k; -8k; -16k; -32k; -64k;
3365 -128k */
3366#define PXP2_REG_RQ_QM_P_SIZE 0x120050
3367/* [RW 1] 1' indicates that the RBC has finished configuring the PSWRQ */
3368#define PXP2_REG_RQ_RBC_DONE 0x1201b0
3369/* [RW 3] Max burst size filed for read requests port 0; 000 - 128B;
3370 001:256B; 010: 512B; 11:1K:100:2K; 01:4K */
3371#define PXP2_REG_RQ_RD_MBS0 0x120160
3372/* [RW 3] Max burst size filed for read requests port 1; 000 - 128B;
3373 001:256B; 010: 512B; 11:1K:100:2K; 01:4K */
3374#define PXP2_REG_RQ_RD_MBS1 0x120168
3375/* [RW 2] Endian mode for src */
3376#define PXP2_REG_RQ_SRC_ENDIAN_M 0x12019c
3377#define PXP2_REG_RQ_SRC_FIRST_ILT 0x12063c
3378#define PXP2_REG_RQ_SRC_LAST_ILT 0x120640
3379/* [RW 3] page size in L2P table for SRC module; -4k; -8k; -16k; -32k; -64k;
3380 -128k */
3381#define PXP2_REG_RQ_SRC_P_SIZE 0x12006c
3382/* [RW 2] Endian mode for tm */
3383#define PXP2_REG_RQ_TM_ENDIAN_M 0x120198
3384#define PXP2_REG_RQ_TM_FIRST_ILT 0x120644
3385#define PXP2_REG_RQ_TM_LAST_ILT 0x120648
3386/* [RW 3] page size in L2P table for TM module; -4k; -8k; -16k; -32k; -64k;
3387 -128k */
3388#define PXP2_REG_RQ_TM_P_SIZE 0x120034
3389/* [R 5] Number of entries in the ufifo; his fifo has l2p completions */
3390#define PXP2_REG_RQ_UFIFO_NUM_OF_ENTRY 0x12080c
3391/* [RW 18] external first_mem_addr field in L2P table for USDM module port 0 */
3392#define PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR 0x120094
3393/* [R 8] Number of entries occupied by vq 0 in pswrq memory */
3394#define PXP2_REG_RQ_VQ0_ENTRY_CNT 0x120810
3395/* [R 8] Number of entries occupied by vq 10 in pswrq memory */
3396#define PXP2_REG_RQ_VQ10_ENTRY_CNT 0x120818
3397/* [R 8] Number of entries occupied by vq 11 in pswrq memory */
3398#define PXP2_REG_RQ_VQ11_ENTRY_CNT 0x120820
3399/* [R 8] Number of entries occupied by vq 12 in pswrq memory */
3400#define PXP2_REG_RQ_VQ12_ENTRY_CNT 0x120828
3401/* [R 8] Number of entries occupied by vq 13 in pswrq memory */
3402#define PXP2_REG_RQ_VQ13_ENTRY_CNT 0x120830
3403/* [R 8] Number of entries occupied by vq 14 in pswrq memory */
3404#define PXP2_REG_RQ_VQ14_ENTRY_CNT 0x120838
3405/* [R 8] Number of entries occupied by vq 15 in pswrq memory */
3406#define PXP2_REG_RQ_VQ15_ENTRY_CNT 0x120840
3407/* [R 8] Number of entries occupied by vq 16 in pswrq memory */
3408#define PXP2_REG_RQ_VQ16_ENTRY_CNT 0x120848
3409/* [R 8] Number of entries occupied by vq 17 in pswrq memory */
3410#define PXP2_REG_RQ_VQ17_ENTRY_CNT 0x120850
3411/* [R 8] Number of entries occupied by vq 18 in pswrq memory */
3412#define PXP2_REG_RQ_VQ18_ENTRY_CNT 0x120858
3413/* [R 8] Number of entries occupied by vq 19 in pswrq memory */
3414#define PXP2_REG_RQ_VQ19_ENTRY_CNT 0x120860
3415/* [R 8] Number of entries occupied by vq 1 in pswrq memory */
3416#define PXP2_REG_RQ_VQ1_ENTRY_CNT 0x120868
3417/* [R 8] Number of entries occupied by vq 20 in pswrq memory */
3418#define PXP2_REG_RQ_VQ20_ENTRY_CNT 0x120870
3419/* [R 8] Number of entries occupied by vq 21 in pswrq memory */
3420#define PXP2_REG_RQ_VQ21_ENTRY_CNT 0x120878
3421/* [R 8] Number of entries occupied by vq 22 in pswrq memory */
3422#define PXP2_REG_RQ_VQ22_ENTRY_CNT 0x120880
3423/* [R 8] Number of entries occupied by vq 23 in pswrq memory */
3424#define PXP2_REG_RQ_VQ23_ENTRY_CNT 0x120888
3425/* [R 8] Number of entries occupied by vq 24 in pswrq memory */
3426#define PXP2_REG_RQ_VQ24_ENTRY_CNT 0x120890
3427/* [R 8] Number of entries occupied by vq 25 in pswrq memory */
3428#define PXP2_REG_RQ_VQ25_ENTRY_CNT 0x120898
3429/* [R 8] Number of entries occupied by vq 26 in pswrq memory */
3430#define PXP2_REG_RQ_VQ26_ENTRY_CNT 0x1208a0
3431/* [R 8] Number of entries occupied by vq 27 in pswrq memory */
3432#define PXP2_REG_RQ_VQ27_ENTRY_CNT 0x1208a8
3433/* [R 8] Number of entries occupied by vq 28 in pswrq memory */
3434#define PXP2_REG_RQ_VQ28_ENTRY_CNT 0x1208b0
3435/* [R 8] Number of entries occupied by vq 29 in pswrq memory */
3436#define PXP2_REG_RQ_VQ29_ENTRY_CNT 0x1208b8
3437/* [R 8] Number of entries occupied by vq 2 in pswrq memory */
3438#define PXP2_REG_RQ_VQ2_ENTRY_CNT 0x1208c0
3439/* [R 8] Number of entries occupied by vq 30 in pswrq memory */
3440#define PXP2_REG_RQ_VQ30_ENTRY_CNT 0x1208c8
3441/* [R 8] Number of entries occupied by vq 31 in pswrq memory */
3442#define PXP2_REG_RQ_VQ31_ENTRY_CNT 0x1208d0
3443/* [R 8] Number of entries occupied by vq 3 in pswrq memory */
3444#define PXP2_REG_RQ_VQ3_ENTRY_CNT 0x1208d8
3445/* [R 8] Number of entries occupied by vq 4 in pswrq memory */
3446#define PXP2_REG_RQ_VQ4_ENTRY_CNT 0x1208e0
3447/* [R 8] Number of entries occupied by vq 5 in pswrq memory */
3448#define PXP2_REG_RQ_VQ5_ENTRY_CNT 0x1208e8
3449/* [R 8] Number of entries occupied by vq 6 in pswrq memory */
3450#define PXP2_REG_RQ_VQ6_ENTRY_CNT 0x1208f0
3451/* [R 8] Number of entries occupied by vq 7 in pswrq memory */
3452#define PXP2_REG_RQ_VQ7_ENTRY_CNT 0x1208f8
3453/* [R 8] Number of entries occupied by vq 8 in pswrq memory */
3454#define PXP2_REG_RQ_VQ8_ENTRY_CNT 0x120900
3455/* [R 8] Number of entries occupied by vq 9 in pswrq memory */
3456#define PXP2_REG_RQ_VQ9_ENTRY_CNT 0x120908
3457/* [RW 3] Max burst size filed for write requests port 0; 000 - 128B;
3458 001:256B; 010: 512B; */
3459#define PXP2_REG_RQ_WR_MBS0 0x12015c
3460/* [RW 3] Max burst size filed for write requests port 1; 000 - 128B;
3461 001:256B; 010: 512B; */
3462#define PXP2_REG_RQ_WR_MBS1 0x120164
3463/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3464 buffer reaches this number has_payload will be asserted */
3465#define PXP2_REG_WR_CDU_MPS 0x1205f0
3466/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3467 buffer reaches this number has_payload will be asserted */
3468#define PXP2_REG_WR_CSDM_MPS 0x1205d0
3469/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3470 buffer reaches this number has_payload will be asserted */
3471#define PXP2_REG_WR_DBG_MPS 0x1205e8
3472/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3473 buffer reaches this number has_payload will be asserted */
3474#define PXP2_REG_WR_DMAE_MPS 0x1205ec
3475/* [RW 10] if Number of entries in dmae fifo will be higher than this
3476 threshold then has_payload indication will be asserted; the default value
3477 should be equal to &gt; write MBS size! */
3478#define PXP2_REG_WR_DMAE_TH 0x120368
3479/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3480 buffer reaches this number has_payload will be asserted */
3481#define PXP2_REG_WR_HC_MPS 0x1205c8
3482/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3483 buffer reaches this number has_payload will be asserted */
3484#define PXP2_REG_WR_QM_MPS 0x1205dc
3485/* [RW 1] 0 - working in A0 mode; - working in B0 mode */
3486#define PXP2_REG_WR_REV_MODE 0x120670
3487/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3488 buffer reaches this number has_payload will be asserted */
3489#define PXP2_REG_WR_SRC_MPS 0x1205e4
3490/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3491 buffer reaches this number has_payload will be asserted */
3492#define PXP2_REG_WR_TM_MPS 0x1205e0
3493/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3494 buffer reaches this number has_payload will be asserted */
3495#define PXP2_REG_WR_TSDM_MPS 0x1205d4
3496/* [RW 10] if Number of entries in usdmdp fifo will be higher than this
3497 threshold then has_payload indication will be asserted; the default value
3498 should be equal to &gt; write MBS size! */
3499#define PXP2_REG_WR_USDMDP_TH 0x120348
3500/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3501 buffer reaches this number has_payload will be asserted */
3502#define PXP2_REG_WR_USDM_MPS 0x1205cc
3503/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3504 buffer reaches this number has_payload will be asserted */
3505#define PXP2_REG_WR_XSDM_MPS 0x1205d8
3506/* [R 1] debug only: Indication if PSWHST arbiter is idle */
3507#define PXP_REG_HST_ARB_IS_IDLE 0x103004
3508/* [R 8] debug only: A bit mask for all PSWHST arbiter clients. '1' means
3509 this client is waiting for the arbiter. */
3510#define PXP_REG_HST_CLIENTS_WAITING_TO_ARB 0x103008
3511/* [RW 1] When 1; doorbells are discarded and not passed to doorbell queue
3512 block. Should be used for close the gates. */
3513#define PXP_REG_HST_DISCARD_DOORBELLS 0x1030a4
3514/* [R 1] debug only: '1' means this PSWHST is discarding doorbells. This bit
3515 should update according to 'hst_discard_doorbells' register when the state
3516 machine is idle */
3517#define PXP_REG_HST_DISCARD_DOORBELLS_STATUS 0x1030a0
3518/* [RW 1] When 1; new internal writes arriving to the block are discarded.
3519 Should be used for close the gates. */
3520#define PXP_REG_HST_DISCARD_INTERNAL_WRITES 0x1030a8
3521/* [R 6] debug only: A bit mask for all PSWHST internal write clients. '1'
3522 means this PSWHST is discarding inputs from this client. Each bit should
3523 update according to 'hst_discard_internal_writes' register when the state
3524 machine is idle. */
3525#define PXP_REG_HST_DISCARD_INTERNAL_WRITES_STATUS 0x10309c
3526/* [WB 160] Used for initialization of the inbound interrupts memory */
3527#define PXP_REG_HST_INBOUND_INT 0x103800
3528/* [RW 32] Interrupt mask register #0 read/write */
3529#define PXP_REG_PXP_INT_MASK_0 0x103074
3530#define PXP_REG_PXP_INT_MASK_1 0x103084
3531/* [R 32] Interrupt register #0 read */
3532#define PXP_REG_PXP_INT_STS_0 0x103068
3533#define PXP_REG_PXP_INT_STS_1 0x103078
3534/* [RC 32] Interrupt register #0 read clear */
3535#define PXP_REG_PXP_INT_STS_CLR_0 0x10306c
3536#define PXP_REG_PXP_INT_STS_CLR_1 0x10307c
3537/* [RW 27] Parity mask register #0 read/write */
3538#define PXP_REG_PXP_PRTY_MASK 0x103094
3539/* [R 26] Parity register #0 read */
3540#define PXP_REG_PXP_PRTY_STS 0x103088
3541/* [RC 27] Parity register #0 read clear */
3542#define PXP_REG_PXP_PRTY_STS_CLR 0x10308c
3543/* [RW 4] The activity counter initial increment value sent in the load
3544 request */
3545#define QM_REG_ACTCTRINITVAL_0 0x168040
3546#define QM_REG_ACTCTRINITVAL_1 0x168044
3547#define QM_REG_ACTCTRINITVAL_2 0x168048
3548#define QM_REG_ACTCTRINITVAL_3 0x16804c
3549/* [RW 32] The base logical address (in bytes) of each physical queue. The
3550 index I represents the physical queue number. The 12 lsbs are ignore and
3551 considered zero so practically there are only 20 bits in this register;
3552 queues 63-0 */
3553#define QM_REG_BASEADDR 0x168900
3554/* [RW 32] The base logical address (in bytes) of each physical queue. The
3555 index I represents the physical queue number. The 12 lsbs are ignore and
3556 considered zero so practically there are only 20 bits in this register;
3557 queues 127-64 */
3558#define QM_REG_BASEADDR_EXT_A 0x16e100
3559/* [RW 16] The byte credit cost for each task. This value is for both ports */
3560#define QM_REG_BYTECRDCOST 0x168234
3561/* [RW 16] The initial byte credit value for both ports. */
3562#define QM_REG_BYTECRDINITVAL 0x168238
3563/* [RW 32] A bit per physical queue. If the bit is cleared then the physical
3564 queue uses port 0 else it uses port 1; queues 31-0 */
3565#define QM_REG_BYTECRDPORT_LSB 0x168228
3566/* [RW 32] A bit per physical queue. If the bit is cleared then the physical
3567 queue uses port 0 else it uses port 1; queues 95-64 */
3568#define QM_REG_BYTECRDPORT_LSB_EXT_A 0x16e520
3569/* [RW 32] A bit per physical queue. If the bit is cleared then the physical
3570 queue uses port 0 else it uses port 1; queues 63-32 */
3571#define QM_REG_BYTECRDPORT_MSB 0x168224
3572/* [RW 32] A bit per physical queue. If the bit is cleared then the physical
3573 queue uses port 0 else it uses port 1; queues 127-96 */
3574#define QM_REG_BYTECRDPORT_MSB_EXT_A 0x16e51c
3575/* [RW 16] The byte credit value that if above the QM is considered almost
3576 full */
3577#define QM_REG_BYTECREDITAFULLTHR 0x168094
3578/* [RW 4] The initial credit for interface */
3579#define QM_REG_CMINITCRD_0 0x1680cc
3580#define QM_REG_BYTECRDCMDQ_0 0x16e6e8
3581#define QM_REG_CMINITCRD_1 0x1680d0
3582#define QM_REG_CMINITCRD_2 0x1680d4
3583#define QM_REG_CMINITCRD_3 0x1680d8
3584#define QM_REG_CMINITCRD_4 0x1680dc
3585#define QM_REG_CMINITCRD_5 0x1680e0
3586#define QM_REG_CMINITCRD_6 0x1680e4
3587#define QM_REG_CMINITCRD_7 0x1680e8
3588/* [RW 8] A mask bit per CM interface. If this bit is 0 then this interface
3589 is masked */
3590#define QM_REG_CMINTEN 0x1680ec
3591/* [RW 12] A bit vector which indicates which one of the queues are tied to
3592 interface 0 */
3593#define QM_REG_CMINTVOQMASK_0 0x1681f4
3594#define QM_REG_CMINTVOQMASK_1 0x1681f8
3595#define QM_REG_CMINTVOQMASK_2 0x1681fc
3596#define QM_REG_CMINTVOQMASK_3 0x168200
3597#define QM_REG_CMINTVOQMASK_4 0x168204
3598#define QM_REG_CMINTVOQMASK_5 0x168208
3599#define QM_REG_CMINTVOQMASK_6 0x16820c
3600#define QM_REG_CMINTVOQMASK_7 0x168210
3601/* [RW 20] The number of connections divided by 16 which dictates the size
3602 of each queue which belongs to even function number. */
3603#define QM_REG_CONNNUM_0 0x168020
3604/* [R 6] Keep the fill level of the fifo from write client 4 */
3605#define QM_REG_CQM_WRC_FIFOLVL 0x168018
3606/* [RW 8] The context regions sent in the CFC load request */
3607#define QM_REG_CTXREG_0 0x168030
3608#define QM_REG_CTXREG_1 0x168034
3609#define QM_REG_CTXREG_2 0x168038
3610#define QM_REG_CTXREG_3 0x16803c
3611/* [RW 12] The VOQ mask used to select the VOQs which needs to be full for
3612 bypass enable */
3613#define QM_REG_ENBYPVOQMASK 0x16823c
3614/* [RW 32] A bit mask per each physical queue. If a bit is set then the
3615 physical queue uses the byte credit; queues 31-0 */
3616#define QM_REG_ENBYTECRD_LSB 0x168220
3617/* [RW 32] A bit mask per each physical queue. If a bit is set then the
3618 physical queue uses the byte credit; queues 95-64 */
3619#define QM_REG_ENBYTECRD_LSB_EXT_A 0x16e518
3620/* [RW 32] A bit mask per each physical queue. If a bit is set then the
3621 physical queue uses the byte credit; queues 63-32 */
3622#define QM_REG_ENBYTECRD_MSB 0x16821c
3623/* [RW 32] A bit mask per each physical queue. If a bit is set then the
3624 physical queue uses the byte credit; queues 127-96 */
3625#define QM_REG_ENBYTECRD_MSB_EXT_A 0x16e514
3626/* [RW 4] If cleared then the secondary interface will not be served by the
3627 RR arbiter */
3628#define QM_REG_ENSEC 0x1680f0
3629/* [RW 32] NA */
3630#define QM_REG_FUNCNUMSEL_LSB 0x168230
3631/* [RW 32] NA */
3632#define QM_REG_FUNCNUMSEL_MSB 0x16822c
3633/* [RW 32] A mask register to mask the Almost empty signals which will not
3634 be use for the almost empty indication to the HW block; queues 31:0 */
3635#define QM_REG_HWAEMPTYMASK_LSB 0x168218
3636/* [RW 32] A mask register to mask the Almost empty signals which will not
3637 be use for the almost empty indication to the HW block; queues 95-64 */
3638#define QM_REG_HWAEMPTYMASK_LSB_EXT_A 0x16e510
3639/* [RW 32] A mask register to mask the Almost empty signals which will not
3640 be use for the almost empty indication to the HW block; queues 63:32 */
3641#define QM_REG_HWAEMPTYMASK_MSB 0x168214
3642/* [RW 32] A mask register to mask the Almost empty signals which will not
3643 be use for the almost empty indication to the HW block; queues 127-96 */
3644#define QM_REG_HWAEMPTYMASK_MSB_EXT_A 0x16e50c
3645/* [RW 4] The number of outstanding request to CFC */
3646#define QM_REG_OUTLDREQ 0x168804
3647/* [RC 1] A flag to indicate that overflow error occurred in one of the
3648 queues. */
3649#define QM_REG_OVFERROR 0x16805c
3650/* [RC 7] the Q where the overflow occurs */
3651#define QM_REG_OVFQNUM 0x168058
3652/* [R 16] Pause state for physical queues 15-0 */
3653#define QM_REG_PAUSESTATE0 0x168410
3654/* [R 16] Pause state for physical queues 31-16 */
3655#define QM_REG_PAUSESTATE1 0x168414
3656/* [R 16] Pause state for physical queues 47-32 */
3657#define QM_REG_PAUSESTATE2 0x16e684
3658/* [R 16] Pause state for physical queues 63-48 */
3659#define QM_REG_PAUSESTATE3 0x16e688
3660/* [R 16] Pause state for physical queues 79-64 */
3661#define QM_REG_PAUSESTATE4 0x16e68c
3662/* [R 16] Pause state for physical queues 95-80 */
3663#define QM_REG_PAUSESTATE5 0x16e690
3664/* [R 16] Pause state for physical queues 111-96 */
3665#define QM_REG_PAUSESTATE6 0x16e694
3666/* [R 16] Pause state for physical queues 127-112 */
3667#define QM_REG_PAUSESTATE7 0x16e698
3668/* [RW 2] The PCI attributes field used in the PCI request. */
3669#define QM_REG_PCIREQAT 0x168054
3670#define QM_REG_PF_EN 0x16e70c
3671/* [R 24] The number of tasks stored in the QM for the PF. only even
3672 * functions are valid in E2 (odd I registers will be hard wired to 0) */
3673#define QM_REG_PF_USG_CNT_0 0x16e040
3674/* [R 16] NOT USED */
3675#define QM_REG_PORT0BYTECRD 0x168300
3676/* [R 16] The byte credit of port 1 */
3677#define QM_REG_PORT1BYTECRD 0x168304
3678/* [RW 3] pci function number of queues 15-0 */
3679#define QM_REG_PQ2PCIFUNC_0 0x16e6bc
3680#define QM_REG_PQ2PCIFUNC_1 0x16e6c0
3681#define QM_REG_PQ2PCIFUNC_2 0x16e6c4
3682#define QM_REG_PQ2PCIFUNC_3 0x16e6c8
3683#define QM_REG_PQ2PCIFUNC_4 0x16e6cc
3684#define QM_REG_PQ2PCIFUNC_5 0x16e6d0
3685#define QM_REG_PQ2PCIFUNC_6 0x16e6d4
3686#define QM_REG_PQ2PCIFUNC_7 0x16e6d8
3687/* [WB 54] Pointer Table Memory for queues 63-0; The mapping is as follow:
3688 ptrtbl[53:30] read pointer; ptrtbl[29:6] write pointer; ptrtbl[5:4] read
3689 bank0; ptrtbl[3:2] read bank 1; ptrtbl[1:0] write bank; */
3690#define QM_REG_PTRTBL 0x168a00
3691/* [WB 54] Pointer Table Memory for queues 127-64; The mapping is as follow:
3692 ptrtbl[53:30] read pointer; ptrtbl[29:6] write pointer; ptrtbl[5:4] read
3693 bank0; ptrtbl[3:2] read bank 1; ptrtbl[1:0] write bank; */
3694#define QM_REG_PTRTBL_EXT_A 0x16e200
3695/* [RW 2] Interrupt mask register #0 read/write */
3696#define QM_REG_QM_INT_MASK 0x168444
3697/* [R 2] Interrupt register #0 read */
3698#define QM_REG_QM_INT_STS 0x168438
3699/* [RW 12] Parity mask register #0 read/write */
3700#define QM_REG_QM_PRTY_MASK 0x168454
3701/* [R 12] Parity register #0 read */
3702#define QM_REG_QM_PRTY_STS 0x168448
3703/* [RC 12] Parity register #0 read clear */
3704#define QM_REG_QM_PRTY_STS_CLR 0x16844c
3705/* [R 32] Current queues in pipeline: Queues from 32 to 63 */
3706#define QM_REG_QSTATUS_HIGH 0x16802c
3707/* [R 32] Current queues in pipeline: Queues from 96 to 127 */
3708#define QM_REG_QSTATUS_HIGH_EXT_A 0x16e408
3709/* [R 32] Current queues in pipeline: Queues from 0 to 31 */
3710#define QM_REG_QSTATUS_LOW 0x168028
3711/* [R 32] Current queues in pipeline: Queues from 64 to 95 */
3712#define QM_REG_QSTATUS_LOW_EXT_A 0x16e404
3713/* [R 24] The number of tasks queued for each queue; queues 63-0 */
3714#define QM_REG_QTASKCTR_0 0x168308
3715/* [R 24] The number of tasks queued for each queue; queues 127-64 */
3716#define QM_REG_QTASKCTR_EXT_A_0 0x16e584
3717/* [RW 4] Queue tied to VOQ */
3718#define QM_REG_QVOQIDX_0 0x1680f4
3719#define QM_REG_QVOQIDX_10 0x16811c
3720#define QM_REG_QVOQIDX_100 0x16e49c
3721#define QM_REG_QVOQIDX_101 0x16e4a0
3722#define QM_REG_QVOQIDX_102 0x16e4a4
3723#define QM_REG_QVOQIDX_103 0x16e4a8
3724#define QM_REG_QVOQIDX_104 0x16e4ac
3725#define QM_REG_QVOQIDX_105 0x16e4b0
3726#define QM_REG_QVOQIDX_106 0x16e4b4
3727#define QM_REG_QVOQIDX_107 0x16e4b8
3728#define QM_REG_QVOQIDX_108 0x16e4bc
3729#define QM_REG_QVOQIDX_109 0x16e4c0
3730#define QM_REG_QVOQIDX_11 0x168120
3731#define QM_REG_QVOQIDX_110 0x16e4c4
3732#define QM_REG_QVOQIDX_111 0x16e4c8
3733#define QM_REG_QVOQIDX_112 0x16e4cc
3734#define QM_REG_QVOQIDX_113 0x16e4d0
3735#define QM_REG_QVOQIDX_114 0x16e4d4
3736#define QM_REG_QVOQIDX_115 0x16e4d8
3737#define QM_REG_QVOQIDX_116 0x16e4dc
3738#define QM_REG_QVOQIDX_117 0x16e4e0
3739#define QM_REG_QVOQIDX_118 0x16e4e4
3740#define QM_REG_QVOQIDX_119 0x16e4e8
3741#define QM_REG_QVOQIDX_12 0x168124
3742#define QM_REG_QVOQIDX_120 0x16e4ec
3743#define QM_REG_QVOQIDX_121 0x16e4f0
3744#define QM_REG_QVOQIDX_122 0x16e4f4
3745#define QM_REG_QVOQIDX_123 0x16e4f8
3746#define QM_REG_QVOQIDX_124 0x16e4fc
3747#define QM_REG_QVOQIDX_125 0x16e500
3748#define QM_REG_QVOQIDX_126 0x16e504
3749#define QM_REG_QVOQIDX_127 0x16e508
3750#define QM_REG_QVOQIDX_13 0x168128
3751#define QM_REG_QVOQIDX_14 0x16812c
3752#define QM_REG_QVOQIDX_15 0x168130
3753#define QM_REG_QVOQIDX_16 0x168134
3754#define QM_REG_QVOQIDX_17 0x168138
3755#define QM_REG_QVOQIDX_21 0x168148
3756#define QM_REG_QVOQIDX_22 0x16814c
3757#define QM_REG_QVOQIDX_23 0x168150
3758#define QM_REG_QVOQIDX_24 0x168154
3759#define QM_REG_QVOQIDX_25 0x168158
3760#define QM_REG_QVOQIDX_26 0x16815c
3761#define QM_REG_QVOQIDX_27 0x168160
3762#define QM_REG_QVOQIDX_28 0x168164
3763#define QM_REG_QVOQIDX_29 0x168168
3764#define QM_REG_QVOQIDX_30 0x16816c
3765#define QM_REG_QVOQIDX_31 0x168170
3766#define QM_REG_QVOQIDX_32 0x168174
3767#define QM_REG_QVOQIDX_33 0x168178
3768#define QM_REG_QVOQIDX_34 0x16817c
3769#define QM_REG_QVOQIDX_35 0x168180
3770#define QM_REG_QVOQIDX_36 0x168184
3771#define QM_REG_QVOQIDX_37 0x168188
3772#define QM_REG_QVOQIDX_38 0x16818c
3773#define QM_REG_QVOQIDX_39 0x168190
3774#define QM_REG_QVOQIDX_40 0x168194
3775#define QM_REG_QVOQIDX_41 0x168198
3776#define QM_REG_QVOQIDX_42 0x16819c
3777#define QM_REG_QVOQIDX_43 0x1681a0
3778#define QM_REG_QVOQIDX_44 0x1681a4
3779#define QM_REG_QVOQIDX_45 0x1681a8
3780#define QM_REG_QVOQIDX_46 0x1681ac
3781#define QM_REG_QVOQIDX_47 0x1681b0
3782#define QM_REG_QVOQIDX_48 0x1681b4
3783#define QM_REG_QVOQIDX_49 0x1681b8
3784#define QM_REG_QVOQIDX_5 0x168108
3785#define QM_REG_QVOQIDX_50 0x1681bc
3786#define QM_REG_QVOQIDX_51 0x1681c0
3787#define QM_REG_QVOQIDX_52 0x1681c4
3788#define QM_REG_QVOQIDX_53 0x1681c8
3789#define QM_REG_QVOQIDX_54 0x1681cc
3790#define QM_REG_QVOQIDX_55 0x1681d0
3791#define QM_REG_QVOQIDX_56 0x1681d4
3792#define QM_REG_QVOQIDX_57 0x1681d8
3793#define QM_REG_QVOQIDX_58 0x1681dc
3794#define QM_REG_QVOQIDX_59 0x1681e0
3795#define QM_REG_QVOQIDX_6 0x16810c
3796#define QM_REG_QVOQIDX_60 0x1681e4
3797#define QM_REG_QVOQIDX_61 0x1681e8
3798#define QM_REG_QVOQIDX_62 0x1681ec
3799#define QM_REG_QVOQIDX_63 0x1681f0
3800#define QM_REG_QVOQIDX_64 0x16e40c
3801#define QM_REG_QVOQIDX_65 0x16e410
3802#define QM_REG_QVOQIDX_69 0x16e420
3803#define QM_REG_QVOQIDX_7 0x168110
3804#define QM_REG_QVOQIDX_70 0x16e424
3805#define QM_REG_QVOQIDX_71 0x16e428
3806#define QM_REG_QVOQIDX_72 0x16e42c
3807#define QM_REG_QVOQIDX_73 0x16e430
3808#define QM_REG_QVOQIDX_74 0x16e434
3809#define QM_REG_QVOQIDX_75 0x16e438
3810#define QM_REG_QVOQIDX_76 0x16e43c
3811#define QM_REG_QVOQIDX_77 0x16e440
3812#define QM_REG_QVOQIDX_78 0x16e444
3813#define QM_REG_QVOQIDX_79 0x16e448
3814#define QM_REG_QVOQIDX_8 0x168114
3815#define QM_REG_QVOQIDX_80 0x16e44c
3816#define QM_REG_QVOQIDX_81 0x16e450
3817#define QM_REG_QVOQIDX_85 0x16e460
3818#define QM_REG_QVOQIDX_86 0x16e464
3819#define QM_REG_QVOQIDX_87 0x16e468
3820#define QM_REG_QVOQIDX_88 0x16e46c
3821#define QM_REG_QVOQIDX_89 0x16e470
3822#define QM_REG_QVOQIDX_9 0x168118
3823#define QM_REG_QVOQIDX_90 0x16e474
3824#define QM_REG_QVOQIDX_91 0x16e478
3825#define QM_REG_QVOQIDX_92 0x16e47c
3826#define QM_REG_QVOQIDX_93 0x16e480
3827#define QM_REG_QVOQIDX_94 0x16e484
3828#define QM_REG_QVOQIDX_95 0x16e488
3829#define QM_REG_QVOQIDX_96 0x16e48c
3830#define QM_REG_QVOQIDX_97 0x16e490
3831#define QM_REG_QVOQIDX_98 0x16e494
3832#define QM_REG_QVOQIDX_99 0x16e498
3833/* [RW 1] Initialization bit command */
3834#define QM_REG_SOFT_RESET 0x168428
3835/* [RW 8] The credit cost per every task in the QM. A value per each VOQ */
3836#define QM_REG_TASKCRDCOST_0 0x16809c
3837#define QM_REG_TASKCRDCOST_1 0x1680a0
3838#define QM_REG_TASKCRDCOST_2 0x1680a4
3839#define QM_REG_TASKCRDCOST_4 0x1680ac
3840#define QM_REG_TASKCRDCOST_5 0x1680b0
3841/* [R 6] Keep the fill level of the fifo from write client 3 */
3842#define QM_REG_TQM_WRC_FIFOLVL 0x168010
3843/* [R 6] Keep the fill level of the fifo from write client 2 */
3844#define QM_REG_UQM_WRC_FIFOLVL 0x168008
3845/* [RC 32] Credit update error register */
3846#define QM_REG_VOQCRDERRREG 0x168408
3847/* [R 16] The credit value for each VOQ */
3848#define QM_REG_VOQCREDIT_0 0x1682d0
3849#define QM_REG_VOQCREDIT_1 0x1682d4
3850#define QM_REG_VOQCREDIT_4 0x1682e0
3851/* [RW 16] The credit value that if above the QM is considered almost full */
3852#define QM_REG_VOQCREDITAFULLTHR 0x168090
3853/* [RW 16] The init and maximum credit for each VoQ */
3854#define QM_REG_VOQINITCREDIT_0 0x168060
3855#define QM_REG_VOQINITCREDIT_1 0x168064
3856#define QM_REG_VOQINITCREDIT_2 0x168068
3857#define QM_REG_VOQINITCREDIT_4 0x168070
3858#define QM_REG_VOQINITCREDIT_5 0x168074
3859/* [RW 1] The port of which VOQ belongs */
3860#define QM_REG_VOQPORT_0 0x1682a0
3861#define QM_REG_VOQPORT_1 0x1682a4
3862#define QM_REG_VOQPORT_2 0x1682a8
3863/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3864#define QM_REG_VOQQMASK_0_LSB 0x168240
3865/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3866#define QM_REG_VOQQMASK_0_LSB_EXT_A 0x16e524
3867/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
3868#define QM_REG_VOQQMASK_0_MSB 0x168244
3869/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3870#define QM_REG_VOQQMASK_0_MSB_EXT_A 0x16e528
3871/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3872#define QM_REG_VOQQMASK_10_LSB 0x168290
3873/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3874#define QM_REG_VOQQMASK_10_LSB_EXT_A 0x16e574
3875/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
3876#define QM_REG_VOQQMASK_10_MSB 0x168294
3877/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3878#define QM_REG_VOQQMASK_10_MSB_EXT_A 0x16e578
3879/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3880#define QM_REG_VOQQMASK_11_LSB 0x168298
3881/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3882#define QM_REG_VOQQMASK_11_LSB_EXT_A 0x16e57c
3883/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
3884#define QM_REG_VOQQMASK_11_MSB 0x16829c
3885/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3886#define QM_REG_VOQQMASK_11_MSB_EXT_A 0x16e580
3887/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3888#define QM_REG_VOQQMASK_1_LSB 0x168248
3889/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3890#define QM_REG_VOQQMASK_1_LSB_EXT_A 0x16e52c
3891/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
3892#define QM_REG_VOQQMASK_1_MSB 0x16824c
3893/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3894#define QM_REG_VOQQMASK_1_MSB_EXT_A 0x16e530
3895/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3896#define QM_REG_VOQQMASK_2_LSB 0x168250
3897/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3898#define QM_REG_VOQQMASK_2_LSB_EXT_A 0x16e534
3899/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
3900#define QM_REG_VOQQMASK_2_MSB 0x168254
3901/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3902#define QM_REG_VOQQMASK_2_MSB_EXT_A 0x16e538
3903/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3904#define QM_REG_VOQQMASK_3_LSB 0x168258
3905/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3906#define QM_REG_VOQQMASK_3_LSB_EXT_A 0x16e53c
3907/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3908#define QM_REG_VOQQMASK_3_MSB_EXT_A 0x16e540
3909/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3910#define QM_REG_VOQQMASK_4_LSB 0x168260
3911/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3912#define QM_REG_VOQQMASK_4_LSB_EXT_A 0x16e544
3913/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
3914#define QM_REG_VOQQMASK_4_MSB 0x168264
3915/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3916#define QM_REG_VOQQMASK_4_MSB_EXT_A 0x16e548
3917/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3918#define QM_REG_VOQQMASK_5_LSB 0x168268
3919/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3920#define QM_REG_VOQQMASK_5_LSB_EXT_A 0x16e54c
3921/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
3922#define QM_REG_VOQQMASK_5_MSB 0x16826c
3923/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3924#define QM_REG_VOQQMASK_5_MSB_EXT_A 0x16e550
3925/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3926#define QM_REG_VOQQMASK_6_LSB 0x168270
3927/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3928#define QM_REG_VOQQMASK_6_LSB_EXT_A 0x16e554
3929/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
3930#define QM_REG_VOQQMASK_6_MSB 0x168274
3931/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3932#define QM_REG_VOQQMASK_6_MSB_EXT_A 0x16e558
3933/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3934#define QM_REG_VOQQMASK_7_LSB 0x168278
3935/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3936#define QM_REG_VOQQMASK_7_LSB_EXT_A 0x16e55c
3937/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
3938#define QM_REG_VOQQMASK_7_MSB 0x16827c
3939/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3940#define QM_REG_VOQQMASK_7_MSB_EXT_A 0x16e560
3941/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3942#define QM_REG_VOQQMASK_8_LSB 0x168280
3943/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3944#define QM_REG_VOQQMASK_8_LSB_EXT_A 0x16e564
3945/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
3946#define QM_REG_VOQQMASK_8_MSB 0x168284
3947/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3948#define QM_REG_VOQQMASK_8_MSB_EXT_A 0x16e568
3949/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3950#define QM_REG_VOQQMASK_9_LSB 0x168288
3951/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3952#define QM_REG_VOQQMASK_9_LSB_EXT_A 0x16e56c
3953/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3954#define QM_REG_VOQQMASK_9_MSB_EXT_A 0x16e570
3955/* [RW 32] Wrr weights */
3956#define QM_REG_WRRWEIGHTS_0 0x16880c
3957#define QM_REG_WRRWEIGHTS_1 0x168810
3958#define QM_REG_WRRWEIGHTS_10 0x168814
3959#define QM_REG_WRRWEIGHTS_11 0x168818
3960#define QM_REG_WRRWEIGHTS_12 0x16881c
3961#define QM_REG_WRRWEIGHTS_13 0x168820
3962#define QM_REG_WRRWEIGHTS_14 0x168824
3963#define QM_REG_WRRWEIGHTS_15 0x168828
3964#define QM_REG_WRRWEIGHTS_16 0x16e000
3965#define QM_REG_WRRWEIGHTS_17 0x16e004
3966#define QM_REG_WRRWEIGHTS_18 0x16e008
3967#define QM_REG_WRRWEIGHTS_19 0x16e00c
3968#define QM_REG_WRRWEIGHTS_2 0x16882c
3969#define QM_REG_WRRWEIGHTS_20 0x16e010
3970#define QM_REG_WRRWEIGHTS_21 0x16e014
3971#define QM_REG_WRRWEIGHTS_22 0x16e018
3972#define QM_REG_WRRWEIGHTS_23 0x16e01c
3973#define QM_REG_WRRWEIGHTS_24 0x16e020
3974#define QM_REG_WRRWEIGHTS_25 0x16e024
3975#define QM_REG_WRRWEIGHTS_26 0x16e028
3976#define QM_REG_WRRWEIGHTS_27 0x16e02c
3977#define QM_REG_WRRWEIGHTS_28 0x16e030
3978#define QM_REG_WRRWEIGHTS_29 0x16e034
3979#define QM_REG_WRRWEIGHTS_3 0x168830
3980#define QM_REG_WRRWEIGHTS_30 0x16e038
3981#define QM_REG_WRRWEIGHTS_31 0x16e03c
3982#define QM_REG_WRRWEIGHTS_4 0x168834
3983#define QM_REG_WRRWEIGHTS_5 0x168838
3984#define QM_REG_WRRWEIGHTS_6 0x16883c
3985#define QM_REG_WRRWEIGHTS_7 0x168840
3986#define QM_REG_WRRWEIGHTS_8 0x168844
3987#define QM_REG_WRRWEIGHTS_9 0x168848
3988/* [R 6] Keep the fill level of the fifo from write client 1 */
3989#define QM_REG_XQM_WRC_FIFOLVL 0x168000
3990/* [W 1] reset to parity interrupt */
3991#define SEM_FAST_REG_PARITY_RST 0x18840
3992#define SRC_REG_COUNTFREE0 0x40500
3993/* [RW 1] If clr the searcher is compatible to E1 A0 - support only two
3994 ports. If set the searcher support 8 functions. */
3995#define SRC_REG_E1HMF_ENABLE 0x404cc
3996#define SRC_REG_FIRSTFREE0 0x40510
3997#define SRC_REG_KEYRSS0_0 0x40408
3998#define SRC_REG_KEYRSS0_7 0x40424
3999#define SRC_REG_KEYRSS1_9 0x40454
4000#define SRC_REG_KEYSEARCH_0 0x40458
4001#define SRC_REG_KEYSEARCH_1 0x4045c
4002#define SRC_REG_KEYSEARCH_2 0x40460
4003#define SRC_REG_KEYSEARCH_3 0x40464
4004#define SRC_REG_KEYSEARCH_4 0x40468
4005#define SRC_REG_KEYSEARCH_5 0x4046c
4006#define SRC_REG_KEYSEARCH_6 0x40470
4007#define SRC_REG_KEYSEARCH_7 0x40474
4008#define SRC_REG_KEYSEARCH_8 0x40478
4009#define SRC_REG_KEYSEARCH_9 0x4047c
4010#define SRC_REG_LASTFREE0 0x40530
4011#define SRC_REG_NUMBER_HASH_BITS0 0x40400
4012/* [RW 1] Reset internal state machines. */
4013#define SRC_REG_SOFT_RST 0x4049c
4014/* [R 3] Interrupt register #0 read */
4015#define SRC_REG_SRC_INT_STS 0x404ac
4016/* [RW 3] Parity mask register #0 read/write */
4017#define SRC_REG_SRC_PRTY_MASK 0x404c8
4018/* [R 3] Parity register #0 read */
4019#define SRC_REG_SRC_PRTY_STS 0x404bc
4020/* [RC 3] Parity register #0 read clear */
4021#define SRC_REG_SRC_PRTY_STS_CLR 0x404c0
4022/* [R 4] Used to read the value of the XX protection CAM occupancy counter. */
4023#define TCM_REG_CAM_OCCUP 0x5017c
4024/* [RW 1] CDU AG read Interface enable. If 0 - the request input is
4025 disregarded; valid output is deasserted; all other signals are treated as
4026 usual; if 1 - normal activity. */
4027#define TCM_REG_CDU_AG_RD_IFEN 0x50034
4028/* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
4029 are disregarded; all other signals are treated as usual; if 1 - normal
4030 activity. */
4031#define TCM_REG_CDU_AG_WR_IFEN 0x50030
4032/* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
4033 disregarded; valid output is deasserted; all other signals are treated as
4034 usual; if 1 - normal activity. */
4035#define TCM_REG_CDU_SM_RD_IFEN 0x5003c
4036/* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
4037 input is disregarded; all other signals are treated as usual; if 1 -
4038 normal activity. */
4039#define TCM_REG_CDU_SM_WR_IFEN 0x50038
4040/* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
4041 the initial credit value; read returns the current value of the credit
4042 counter. Must be initialized to 1 at start-up. */
4043#define TCM_REG_CFC_INIT_CRD 0x50204
4044/* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for
4045 weight 8 (the most prioritised); 1 stands for weight 1(least
4046 prioritised); 2 stands for weight 2; tc. */
4047#define TCM_REG_CP_WEIGHT 0x500c0
4048/* [RW 1] Input csem Interface enable. If 0 - the valid input is
4049 disregarded; acknowledge output is deasserted; all other signals are
4050 treated as usual; if 1 - normal activity. */
4051#define TCM_REG_CSEM_IFEN 0x5002c
4052/* [RC 1] Message length mismatch (relative to last indication) at the In#9
4053 interface. */
4054#define TCM_REG_CSEM_LENGTH_MIS 0x50174
4055/* [RW 3] The weight of the input csem in the WRR mechanism. 0 stands for
4056 weight 8 (the most prioritised); 1 stands for weight 1(least
4057 prioritised); 2 stands for weight 2; tc. */
4058#define TCM_REG_CSEM_WEIGHT 0x500bc
4059/* [RW 8] The Event ID in case of ErrorFlg is set in the input message. */
4060#define TCM_REG_ERR_EVNT_ID 0x500a0
4061/* [RW 28] The CM erroneous header for QM and Timers formatting. */
4062#define TCM_REG_ERR_TCM_HDR 0x5009c
4063/* [RW 8] The Event ID for Timers expiration. */
4064#define TCM_REG_EXPR_EVNT_ID 0x500a4
4065/* [RW 8] FIC0 output initial credit. Max credit available - 255.Write
4066 writes the initial credit value; read returns the current value of the
4067 credit counter. Must be initialized to 64 at start-up. */
4068#define TCM_REG_FIC0_INIT_CRD 0x5020c
4069/* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
4070 writes the initial credit value; read returns the current value of the
4071 credit counter. Must be initialized to 64 at start-up. */
4072#define TCM_REG_FIC1_INIT_CRD 0x50210
4073/* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1
4074 - strict priority defined by ~tcm_registers_gr_ag_pr.gr_ag_pr;
4075 ~tcm_registers_gr_ld0_pr.gr_ld0_pr and
4076 ~tcm_registers_gr_ld1_pr.gr_ld1_pr. */
4077#define TCM_REG_GR_ARB_TYPE 0x50114
4078/* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
4079 highest priority is 3. It is supposed that the Store channel is the
4080 compliment of the other 3 groups. */
4081#define TCM_REG_GR_LD0_PR 0x5011c
4082/* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
4083 highest priority is 3. It is supposed that the Store channel is the
4084 compliment of the other 3 groups. */
4085#define TCM_REG_GR_LD1_PR 0x50120
4086/* [RW 4] The number of double REG-pairs; loaded from the STORM context and
4087 sent to STORM; for a specific connection type. The double REG-pairs are
4088 used to align to STORM context row size of 128 bits. The offset of these
4089 data in the STORM context is always 0. Index _i stands for the connection
4090 type (one of 16). */
4091#define TCM_REG_N_SM_CTX_LD_0 0x50050
4092#define TCM_REG_N_SM_CTX_LD_1 0x50054
4093#define TCM_REG_N_SM_CTX_LD_2 0x50058
4094#define TCM_REG_N_SM_CTX_LD_3 0x5005c
4095#define TCM_REG_N_SM_CTX_LD_4 0x50060
4096#define TCM_REG_N_SM_CTX_LD_5 0x50064
4097/* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded;
4098 acknowledge output is deasserted; all other signals are treated as usual;
4099 if 1 - normal activity. */
4100#define TCM_REG_PBF_IFEN 0x50024
4101/* [RC 1] Message length mismatch (relative to last indication) at the In#7
4102 interface. */
4103#define TCM_REG_PBF_LENGTH_MIS 0x5016c
4104/* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for
4105 weight 8 (the most prioritised); 1 stands for weight 1(least
4106 prioritised); 2 stands for weight 2; tc. */
4107#define TCM_REG_PBF_WEIGHT 0x500b4
4108#define TCM_REG_PHYS_QNUM0_0 0x500e0
4109#define TCM_REG_PHYS_QNUM0_1 0x500e4
4110#define TCM_REG_PHYS_QNUM1_0 0x500e8
4111#define TCM_REG_PHYS_QNUM1_1 0x500ec
4112#define TCM_REG_PHYS_QNUM2_0 0x500f0
4113#define TCM_REG_PHYS_QNUM2_1 0x500f4
4114#define TCM_REG_PHYS_QNUM3_0 0x500f8
4115#define TCM_REG_PHYS_QNUM3_1 0x500fc
4116/* [RW 1] Input prs Interface enable. If 0 - the valid input is disregarded;
4117 acknowledge output is deasserted; all other signals are treated as usual;
4118 if 1 - normal activity. */
4119#define TCM_REG_PRS_IFEN 0x50020
4120/* [RC 1] Message length mismatch (relative to last indication) at the In#6
4121 interface. */
4122#define TCM_REG_PRS_LENGTH_MIS 0x50168
4123/* [RW 3] The weight of the input prs in the WRR mechanism. 0 stands for
4124 weight 8 (the most prioritised); 1 stands for weight 1(least
4125 prioritised); 2 stands for weight 2; tc. */
4126#define TCM_REG_PRS_WEIGHT 0x500b0
4127/* [RW 8] The Event ID for Timers formatting in case of stop done. */
4128#define TCM_REG_STOP_EVNT_ID 0x500a8
4129/* [RC 1] Message length mismatch (relative to last indication) at the STORM
4130 interface. */
4131#define TCM_REG_STORM_LENGTH_MIS 0x50160
4132/* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
4133 disregarded; acknowledge output is deasserted; all other signals are
4134 treated as usual; if 1 - normal activity. */
4135#define TCM_REG_STORM_TCM_IFEN 0x50010
4136/* [RW 3] The weight of the STORM input in the WRR mechanism. 0 stands for
4137 weight 8 (the most prioritised); 1 stands for weight 1(least
4138 prioritised); 2 stands for weight 2; tc. */
4139#define TCM_REG_STORM_WEIGHT 0x500ac
4140/* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
4141 acknowledge output is deasserted; all other signals are treated as usual;
4142 if 1 - normal activity. */
4143#define TCM_REG_TCM_CFC_IFEN 0x50040
4144/* [RW 11] Interrupt mask register #0 read/write */
4145#define TCM_REG_TCM_INT_MASK 0x501dc
4146/* [R 11] Interrupt register #0 read */
4147#define TCM_REG_TCM_INT_STS 0x501d0
4148/* [RW 27] Parity mask register #0 read/write */
4149#define TCM_REG_TCM_PRTY_MASK 0x501ec
4150/* [R 27] Parity register #0 read */
4151#define TCM_REG_TCM_PRTY_STS 0x501e0
4152/* [RC 27] Parity register #0 read clear */
4153#define TCM_REG_TCM_PRTY_STS_CLR 0x501e4
4154/* [RW 3] The size of AG context region 0 in REG-pairs. Designates the MS
4155 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
4156 Is used to determine the number of the AG context REG-pairs written back;
4157 when the input message Reg1WbFlg isn't set. */
4158#define TCM_REG_TCM_REG0_SZ 0x500d8
4159/* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
4160 disregarded; valid is deasserted; all other signals are treated as usual;
4161 if 1 - normal activity. */
4162#define TCM_REG_TCM_STORM0_IFEN 0x50004
4163/* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
4164 disregarded; valid is deasserted; all other signals are treated as usual;
4165 if 1 - normal activity. */
4166#define TCM_REG_TCM_STORM1_IFEN 0x50008
4167/* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
4168 disregarded; valid is deasserted; all other signals are treated as usual;
4169 if 1 - normal activity. */
4170#define TCM_REG_TCM_TQM_IFEN 0x5000c
4171/* [RW 1] If set the Q index; received from the QM is inserted to event ID. */
4172#define TCM_REG_TCM_TQM_USE_Q 0x500d4
4173/* [RW 28] The CM header for Timers expiration command. */
4174#define TCM_REG_TM_TCM_HDR 0x50098
4175/* [RW 1] Timers - CM Interface enable. If 0 - the valid input is
4176 disregarded; acknowledge output is deasserted; all other signals are
4177 treated as usual; if 1 - normal activity. */
4178#define TCM_REG_TM_TCM_IFEN 0x5001c
4179/* [RW 3] The weight of the Timers input in the WRR mechanism. 0 stands for
4180 weight 8 (the most prioritised); 1 stands for weight 1(least
4181 prioritised); 2 stands for weight 2; tc. */
4182#define TCM_REG_TM_WEIGHT 0x500d0
4183/* [RW 6] QM output initial credit. Max credit available - 32.Write writes
4184 the initial credit value; read returns the current value of the credit
4185 counter. Must be initialized to 32 at start-up. */
4186#define TCM_REG_TQM_INIT_CRD 0x5021c
4187/* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
4188 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
4189 prioritised); 2 stands for weight 2; tc. */
4190#define TCM_REG_TQM_P_WEIGHT 0x500c8
4191/* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0
4192 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
4193 prioritised); 2 stands for weight 2; tc. */
4194#define TCM_REG_TQM_S_WEIGHT 0x500cc
4195/* [RW 28] The CM header value for QM request (primary). */
4196#define TCM_REG_TQM_TCM_HDR_P 0x50090
4197/* [RW 28] The CM header value for QM request (secondary). */
4198#define TCM_REG_TQM_TCM_HDR_S 0x50094
4199/* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
4200 acknowledge output is deasserted; all other signals are treated as usual;
4201 if 1 - normal activity. */
4202#define TCM_REG_TQM_TCM_IFEN 0x50014
4203/* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
4204 acknowledge output is deasserted; all other signals are treated as usual;
4205 if 1 - normal activity. */
4206#define TCM_REG_TSDM_IFEN 0x50018
4207/* [RC 1] Message length mismatch (relative to last indication) at the SDM
4208 interface. */
4209#define TCM_REG_TSDM_LENGTH_MIS 0x50164
4210/* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for
4211 weight 8 (the most prioritised); 1 stands for weight 1(least
4212 prioritised); 2 stands for weight 2; tc. */
4213#define TCM_REG_TSDM_WEIGHT 0x500c4
4214/* [RW 1] Input usem Interface enable. If 0 - the valid input is
4215 disregarded; acknowledge output is deasserted; all other signals are
4216 treated as usual; if 1 - normal activity. */
4217#define TCM_REG_USEM_IFEN 0x50028
4218/* [RC 1] Message length mismatch (relative to last indication) at the In#8
4219 interface. */
4220#define TCM_REG_USEM_LENGTH_MIS 0x50170
4221/* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for
4222 weight 8 (the most prioritised); 1 stands for weight 1(least
4223 prioritised); 2 stands for weight 2; tc. */
4224#define TCM_REG_USEM_WEIGHT 0x500b8
4225/* [RW 21] Indirect access to the descriptor table of the XX protection
4226 mechanism. The fields are: [5:0] - length of the message; 15:6] - message
4227 pointer; 20:16] - next pointer. */
4228#define TCM_REG_XX_DESCR_TABLE 0x50280
4229#define TCM_REG_XX_DESCR_TABLE_SIZE 29
4230/* [R 6] Use to read the value of XX protection Free counter. */
4231#define TCM_REG_XX_FREE 0x50178
4232/* [RW 6] Initial value for the credit counter; responsible for fulfilling
4233 of the Input Stage XX protection buffer by the XX protection pending
4234 messages. Max credit available - 127.Write writes the initial credit
4235 value; read returns the current value of the credit counter. Must be
4236 initialized to 19 at start-up. */
4237#define TCM_REG_XX_INIT_CRD 0x50220
4238/* [RW 6] Maximum link list size (messages locked) per connection in the XX
4239 protection. */
4240#define TCM_REG_XX_MAX_LL_SZ 0x50044
4241/* [RW 6] The maximum number of pending messages; which may be stored in XX
4242 protection. ~tcm_registers_xx_free.xx_free is read on read. */
4243#define TCM_REG_XX_MSG_NUM 0x50224
4244/* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
4245#define TCM_REG_XX_OVFL_EVNT_ID 0x50048
4246/* [RW 16] Indirect access to the XX table of the XX protection mechanism.
4247 The fields are:[4:0] - tail pointer; [10:5] - Link List size; 15:11] -
4248 header pointer. */
4249#define TCM_REG_XX_TABLE 0x50240
4250/* [RW 4] Load value for cfc ac credit cnt. */
4251#define TM_REG_CFC_AC_CRDCNT_VAL 0x164208
4252/* [RW 4] Load value for cfc cld credit cnt. */
4253#define TM_REG_CFC_CLD_CRDCNT_VAL 0x164210
4254/* [RW 8] Client0 context region. */
4255#define TM_REG_CL0_CONT_REGION 0x164030
4256/* [RW 8] Client1 context region. */
4257#define TM_REG_CL1_CONT_REGION 0x164034
4258/* [RW 8] Client2 context region. */
4259#define TM_REG_CL2_CONT_REGION 0x164038
4260/* [RW 2] Client in High priority client number. */
4261#define TM_REG_CLIN_PRIOR0_CLIENT 0x164024
4262/* [RW 4] Load value for clout0 cred cnt. */
4263#define TM_REG_CLOUT_CRDCNT0_VAL 0x164220
4264/* [RW 4] Load value for clout1 cred cnt. */
4265#define TM_REG_CLOUT_CRDCNT1_VAL 0x164228
4266/* [RW 4] Load value for clout2 cred cnt. */
4267#define TM_REG_CLOUT_CRDCNT2_VAL 0x164230
4268/* [RW 1] Enable client0 input. */
4269#define TM_REG_EN_CL0_INPUT 0x164008
4270/* [RW 1] Enable client1 input. */
4271#define TM_REG_EN_CL1_INPUT 0x16400c
4272/* [RW 1] Enable client2 input. */
4273#define TM_REG_EN_CL2_INPUT 0x164010
4274#define TM_REG_EN_LINEAR0_TIMER 0x164014
4275/* [RW 1] Enable real time counter. */
4276#define TM_REG_EN_REAL_TIME_CNT 0x1640d8
4277/* [RW 1] Enable for Timers state machines. */
4278#define TM_REG_EN_TIMERS 0x164000
4279/* [RW 4] Load value for expiration credit cnt. CFC max number of
4280 outstanding load requests for timers (expiration) context loading. */
4281#define TM_REG_EXP_CRDCNT_VAL 0x164238
4282/* [RW 32] Linear0 logic address. */
4283#define TM_REG_LIN0_LOGIC_ADDR 0x164240
4284/* [RW 18] Linear0 Max active cid (in banks of 32 entries). */
4285#define TM_REG_LIN0_MAX_ACTIVE_CID 0x164048
4286/* [ST 16] Linear0 Number of scans counter. */
4287#define TM_REG_LIN0_NUM_SCANS 0x1640a0
4288/* [WB 64] Linear0 phy address. */
4289#define TM_REG_LIN0_PHY_ADDR 0x164270
4290/* [RW 1] Linear0 physical address valid. */
4291#define TM_REG_LIN0_PHY_ADDR_VALID 0x164248
4292#define TM_REG_LIN0_SCAN_ON 0x1640d0
4293/* [RW 24] Linear0 array scan timeout. */
4294#define TM_REG_LIN0_SCAN_TIME 0x16403c
4295#define TM_REG_LIN0_VNIC_UC 0x164128
4296/* [RW 32] Linear1 logic address. */
4297#define TM_REG_LIN1_LOGIC_ADDR 0x164250
4298/* [WB 64] Linear1 phy address. */
4299#define TM_REG_LIN1_PHY_ADDR 0x164280
4300/* [RW 1] Linear1 physical address valid. */
4301#define TM_REG_LIN1_PHY_ADDR_VALID 0x164258
4302/* [RW 6] Linear timer set_clear fifo threshold. */
4303#define TM_REG_LIN_SETCLR_FIFO_ALFULL_THR 0x164070
4304/* [RW 2] Load value for pci arbiter credit cnt. */
4305#define TM_REG_PCIARB_CRDCNT_VAL 0x164260
4306/* [RW 20] The amount of hardware cycles for each timer tick. */
4307#define TM_REG_TIMER_TICK_SIZE 0x16401c
4308/* [RW 8] Timers Context region. */
4309#define TM_REG_TM_CONTEXT_REGION 0x164044
4310/* [RW 1] Interrupt mask register #0 read/write */
4311#define TM_REG_TM_INT_MASK 0x1640fc
4312/* [R 1] Interrupt register #0 read */
4313#define TM_REG_TM_INT_STS 0x1640f0
4314/* [RW 7] Parity mask register #0 read/write */
4315#define TM_REG_TM_PRTY_MASK 0x16410c
4316/* [RC 7] Parity register #0 read clear */
4317#define TM_REG_TM_PRTY_STS_CLR 0x164104
4318/* [RW 8] The event id for aggregated interrupt 0 */
4319#define TSDM_REG_AGG_INT_EVENT_0 0x42038
4320#define TSDM_REG_AGG_INT_EVENT_1 0x4203c
4321#define TSDM_REG_AGG_INT_EVENT_2 0x42040
4322#define TSDM_REG_AGG_INT_EVENT_3 0x42044
4323#define TSDM_REG_AGG_INT_EVENT_4 0x42048
4324/* [RW 1] The T bit for aggregated interrupt 0 */
4325#define TSDM_REG_AGG_INT_T_0 0x420b8
4326#define TSDM_REG_AGG_INT_T_1 0x420bc
4327/* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
4328#define TSDM_REG_CFC_RSP_START_ADDR 0x42008
4329/* [RW 16] The maximum value of the completion counter #0 */
4330#define TSDM_REG_CMP_COUNTER_MAX0 0x4201c
4331/* [RW 16] The maximum value of the completion counter #1 */
4332#define TSDM_REG_CMP_COUNTER_MAX1 0x42020
4333/* [RW 16] The maximum value of the completion counter #2 */
4334#define TSDM_REG_CMP_COUNTER_MAX2 0x42024
4335/* [RW 16] The maximum value of the completion counter #3 */
4336#define TSDM_REG_CMP_COUNTER_MAX3 0x42028
4337/* [RW 13] The start address in the internal RAM for the completion
4338 counters. */
4339#define TSDM_REG_CMP_COUNTER_START_ADDR 0x4200c
4340#define TSDM_REG_ENABLE_IN1 0x42238
4341#define TSDM_REG_ENABLE_IN2 0x4223c
4342#define TSDM_REG_ENABLE_OUT1 0x42240
4343#define TSDM_REG_ENABLE_OUT2 0x42244
4344/* [RW 4] The initial number of messages that can be sent to the pxp control
4345 interface without receiving any ACK. */
4346#define TSDM_REG_INIT_CREDIT_PXP_CTRL 0x424bc
4347/* [ST 32] The number of ACK after placement messages received */
4348#define TSDM_REG_NUM_OF_ACK_AFTER_PLACE 0x4227c
4349/* [ST 32] The number of packet end messages received from the parser */
4350#define TSDM_REG_NUM_OF_PKT_END_MSG 0x42274
4351/* [ST 32] The number of requests received from the pxp async if */
4352#define TSDM_REG_NUM_OF_PXP_ASYNC_REQ 0x42278
4353/* [ST 32] The number of commands received in queue 0 */
4354#define TSDM_REG_NUM_OF_Q0_CMD 0x42248
4355/* [ST 32] The number of commands received in queue 10 */
4356#define TSDM_REG_NUM_OF_Q10_CMD 0x4226c
4357/* [ST 32] The number of commands received in queue 11 */
4358#define TSDM_REG_NUM_OF_Q11_CMD 0x42270
4359/* [ST 32] The number of commands received in queue 1 */
4360#define TSDM_REG_NUM_OF_Q1_CMD 0x4224c
4361/* [ST 32] The number of commands received in queue 3 */
4362#define TSDM_REG_NUM_OF_Q3_CMD 0x42250
4363/* [ST 32] The number of commands received in queue 4 */
4364#define TSDM_REG_NUM_OF_Q4_CMD 0x42254
4365/* [ST 32] The number of commands received in queue 5 */
4366#define TSDM_REG_NUM_OF_Q5_CMD 0x42258
4367/* [ST 32] The number of commands received in queue 6 */
4368#define TSDM_REG_NUM_OF_Q6_CMD 0x4225c
4369/* [ST 32] The number of commands received in queue 7 */
4370#define TSDM_REG_NUM_OF_Q7_CMD 0x42260
4371/* [ST 32] The number of commands received in queue 8 */
4372#define TSDM_REG_NUM_OF_Q8_CMD 0x42264
4373/* [ST 32] The number of commands received in queue 9 */
4374#define TSDM_REG_NUM_OF_Q9_CMD 0x42268
4375/* [RW 13] The start address in the internal RAM for the packet end message */
4376#define TSDM_REG_PCK_END_MSG_START_ADDR 0x42014
4377/* [RW 13] The start address in the internal RAM for queue counters */
4378#define TSDM_REG_Q_COUNTER_START_ADDR 0x42010
4379/* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
4380#define TSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0x42548
4381/* [R 1] parser fifo empty in sdm_sync block */
4382#define TSDM_REG_SYNC_PARSER_EMPTY 0x42550
4383/* [R 1] parser serial fifo empty in sdm_sync block */
4384#define TSDM_REG_SYNC_SYNC_EMPTY 0x42558
4385/* [RW 32] Tick for timer counter. Applicable only when
4386 ~tsdm_registers_timer_tick_enable.timer_tick_enable =1 */
4387#define TSDM_REG_TIMER_TICK 0x42000
4388/* [RW 32] Interrupt mask register #0 read/write */
4389#define TSDM_REG_TSDM_INT_MASK_0 0x4229c
4390#define TSDM_REG_TSDM_INT_MASK_1 0x422ac
4391/* [R 32] Interrupt register #0 read */
4392#define TSDM_REG_TSDM_INT_STS_0 0x42290
4393#define TSDM_REG_TSDM_INT_STS_1 0x422a0
4394/* [RW 11] Parity mask register #0 read/write */
4395#define TSDM_REG_TSDM_PRTY_MASK 0x422bc
4396/* [R 11] Parity register #0 read */
4397#define TSDM_REG_TSDM_PRTY_STS 0x422b0
4398/* [RC 11] Parity register #0 read clear */
4399#define TSDM_REG_TSDM_PRTY_STS_CLR 0x422b4
4400/* [RW 5] The number of time_slots in the arbitration cycle */
4401#define TSEM_REG_ARB_CYCLE_SIZE 0x180034
4402/* [RW 3] The source that is associated with arbitration element 0. Source
4403 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4404 sleeping thread with priority 1; 4- sleeping thread with priority 2 */
4405#define TSEM_REG_ARB_ELEMENT0 0x180020
4406/* [RW 3] The source that is associated with arbitration element 1. Source
4407 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4408 sleeping thread with priority 1; 4- sleeping thread with priority 2.
4409 Could not be equal to register ~tsem_registers_arb_element0.arb_element0 */
4410#define TSEM_REG_ARB_ELEMENT1 0x180024
4411/* [RW 3] The source that is associated with arbitration element 2. Source
4412 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4413 sleeping thread with priority 1; 4- sleeping thread with priority 2.
4414 Could not be equal to register ~tsem_registers_arb_element0.arb_element0
4415 and ~tsem_registers_arb_element1.arb_element1 */
4416#define TSEM_REG_ARB_ELEMENT2 0x180028
4417/* [RW 3] The source that is associated with arbitration element 3. Source
4418 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4419 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could
4420 not be equal to register ~tsem_registers_arb_element0.arb_element0 and
4421 ~tsem_registers_arb_element1.arb_element1 and
4422 ~tsem_registers_arb_element2.arb_element2 */
4423#define TSEM_REG_ARB_ELEMENT3 0x18002c
4424/* [RW 3] The source that is associated with arbitration element 4. Source
4425 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4426 sleeping thread with priority 1; 4- sleeping thread with priority 2.
4427 Could not be equal to register ~tsem_registers_arb_element0.arb_element0
4428 and ~tsem_registers_arb_element1.arb_element1 and
4429 ~tsem_registers_arb_element2.arb_element2 and
4430 ~tsem_registers_arb_element3.arb_element3 */
4431#define TSEM_REG_ARB_ELEMENT4 0x180030
4432#define TSEM_REG_ENABLE_IN 0x1800a4
4433#define TSEM_REG_ENABLE_OUT 0x1800a8
4434/* [RW 32] This address space contains all registers and memories that are
4435 placed in SEM_FAST block. The SEM_FAST registers are described in
4436 appendix B. In order to access the sem_fast registers the base address
4437 ~fast_memory.fast_memory should be added to eachsem_fast register offset. */
4438#define TSEM_REG_FAST_MEMORY 0x1a0000
4439/* [RW 1] Disables input messages from FIC0 May be updated during run_time
4440 by the microcode */
4441#define TSEM_REG_FIC0_DISABLE 0x180224
4442/* [RW 1] Disables input messages from FIC1 May be updated during run_time
4443 by the microcode */
4444#define TSEM_REG_FIC1_DISABLE 0x180234
4445/* [RW 15] Interrupt table Read and write access to it is not possible in
4446 the middle of the work */
4447#define TSEM_REG_INT_TABLE 0x180400
4448/* [ST 24] Statistics register. The number of messages that entered through
4449 FIC0 */
4450#define TSEM_REG_MSG_NUM_FIC0 0x180000
4451/* [ST 24] Statistics register. The number of messages that entered through
4452 FIC1 */
4453#define TSEM_REG_MSG_NUM_FIC1 0x180004
4454/* [ST 24] Statistics register. The number of messages that were sent to
4455 FOC0 */
4456#define TSEM_REG_MSG_NUM_FOC0 0x180008
4457/* [ST 24] Statistics register. The number of messages that were sent to
4458 FOC1 */
4459#define TSEM_REG_MSG_NUM_FOC1 0x18000c
4460/* [ST 24] Statistics register. The number of messages that were sent to
4461 FOC2 */
4462#define TSEM_REG_MSG_NUM_FOC2 0x180010
4463/* [ST 24] Statistics register. The number of messages that were sent to
4464 FOC3 */
4465#define TSEM_REG_MSG_NUM_FOC3 0x180014
4466/* [RW 1] Disables input messages from the passive buffer May be updated
4467 during run_time by the microcode */
4468#define TSEM_REG_PAS_DISABLE 0x18024c
4469/* [WB 128] Debug only. Passive buffer memory */
4470#define TSEM_REG_PASSIVE_BUFFER 0x181000
4471/* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
4472#define TSEM_REG_PRAM 0x1c0000
4473/* [R 8] Valid sleeping threads indication have bit per thread */
4474#define TSEM_REG_SLEEP_THREADS_VALID 0x18026c
4475/* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
4476#define TSEM_REG_SLOW_EXT_STORE_EMPTY 0x1802a0
4477/* [RW 8] List of free threads . There is a bit per thread. */
4478#define TSEM_REG_THREADS_LIST 0x1802e4
4479/* [RC 32] Parity register #0 read clear */
4480#define TSEM_REG_TSEM_PRTY_STS_CLR_0 0x180118
4481#define TSEM_REG_TSEM_PRTY_STS_CLR_1 0x180128
4482/* [RW 3] The arbitration scheme of time_slot 0 */
4483#define TSEM_REG_TS_0_AS 0x180038
4484/* [RW 3] The arbitration scheme of time_slot 10 */
4485#define TSEM_REG_TS_10_AS 0x180060
4486/* [RW 3] The arbitration scheme of time_slot 11 */
4487#define TSEM_REG_TS_11_AS 0x180064
4488/* [RW 3] The arbitration scheme of time_slot 12 */
4489#define TSEM_REG_TS_12_AS 0x180068
4490/* [RW 3] The arbitration scheme of time_slot 13 */
4491#define TSEM_REG_TS_13_AS 0x18006c
4492/* [RW 3] The arbitration scheme of time_slot 14 */
4493#define TSEM_REG_TS_14_AS 0x180070
4494/* [RW 3] The arbitration scheme of time_slot 15 */
4495#define TSEM_REG_TS_15_AS 0x180074
4496/* [RW 3] The arbitration scheme of time_slot 16 */
4497#define TSEM_REG_TS_16_AS 0x180078
4498/* [RW 3] The arbitration scheme of time_slot 17 */
4499#define TSEM_REG_TS_17_AS 0x18007c
4500/* [RW 3] The arbitration scheme of time_slot 18 */
4501#define TSEM_REG_TS_18_AS 0x180080
4502/* [RW 3] The arbitration scheme of time_slot 1 */
4503#define TSEM_REG_TS_1_AS 0x18003c
4504/* [RW 3] The arbitration scheme of time_slot 2 */
4505#define TSEM_REG_TS_2_AS 0x180040
4506/* [RW 3] The arbitration scheme of time_slot 3 */
4507#define TSEM_REG_TS_3_AS 0x180044
4508/* [RW 3] The arbitration scheme of time_slot 4 */
4509#define TSEM_REG_TS_4_AS 0x180048
4510/* [RW 3] The arbitration scheme of time_slot 5 */
4511#define TSEM_REG_TS_5_AS 0x18004c
4512/* [RW 3] The arbitration scheme of time_slot 6 */
4513#define TSEM_REG_TS_6_AS 0x180050
4514/* [RW 3] The arbitration scheme of time_slot 7 */
4515#define TSEM_REG_TS_7_AS 0x180054
4516/* [RW 3] The arbitration scheme of time_slot 8 */
4517#define TSEM_REG_TS_8_AS 0x180058
4518/* [RW 3] The arbitration scheme of time_slot 9 */
4519#define TSEM_REG_TS_9_AS 0x18005c
4520/* [RW 32] Interrupt mask register #0 read/write */
4521#define TSEM_REG_TSEM_INT_MASK_0 0x180100
4522#define TSEM_REG_TSEM_INT_MASK_1 0x180110
4523/* [R 32] Interrupt register #0 read */
4524#define TSEM_REG_TSEM_INT_STS_0 0x1800f4
4525#define TSEM_REG_TSEM_INT_STS_1 0x180104
4526/* [RW 32] Parity mask register #0 read/write */
4527#define TSEM_REG_TSEM_PRTY_MASK_0 0x180120
4528#define TSEM_REG_TSEM_PRTY_MASK_1 0x180130
4529/* [R 32] Parity register #0 read */
4530#define TSEM_REG_TSEM_PRTY_STS_0 0x180114
4531#define TSEM_REG_TSEM_PRTY_STS_1 0x180124
4532/* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 64
4533 * VF; values 64-67 reset error for 4 PF; values 68-127 are not valid. */
4534#define TSEM_REG_VFPF_ERR_NUM 0x180380
4535/* [RW 32] Indirect access to AG context with 32-bits granularity. The bits
4536 * [10:8] of the address should be the offset within the accessed LCID
4537 * context; the bits [7:0] are the accessed LCID.Example: to write to REG10
4538 * LCID100. The RBC address should be 12'ha64. */
4539#define UCM_REG_AG_CTX 0xe2000
4540/* [R 5] Used to read the XX protection CAM occupancy counter. */
4541#define UCM_REG_CAM_OCCUP 0xe0170
4542/* [RW 1] CDU AG read Interface enable. If 0 - the request input is
4543 disregarded; valid output is deasserted; all other signals are treated as
4544 usual; if 1 - normal activity. */
4545#define UCM_REG_CDU_AG_RD_IFEN 0xe0038
4546/* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
4547 are disregarded; all other signals are treated as usual; if 1 - normal
4548 activity. */
4549#define UCM_REG_CDU_AG_WR_IFEN 0xe0034
4550/* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
4551 disregarded; valid output is deasserted; all other signals are treated as
4552 usual; if 1 - normal activity. */
4553#define UCM_REG_CDU_SM_RD_IFEN 0xe0040
4554/* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
4555 input is disregarded; all other signals are treated as usual; if 1 -
4556 normal activity. */
4557#define UCM_REG_CDU_SM_WR_IFEN 0xe003c
4558/* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
4559 the initial credit value; read returns the current value of the credit
4560 counter. Must be initialized to 1 at start-up. */
4561#define UCM_REG_CFC_INIT_CRD 0xe0204
4562/* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for
4563 weight 8 (the most prioritised); 1 stands for weight 1(least
4564 prioritised); 2 stands for weight 2; tc. */
4565#define UCM_REG_CP_WEIGHT 0xe00c4
4566/* [RW 1] Input csem Interface enable. If 0 - the valid input is
4567 disregarded; acknowledge output is deasserted; all other signals are
4568 treated as usual; if 1 - normal activity. */
4569#define UCM_REG_CSEM_IFEN 0xe0028
4570/* [RC 1] Set when the message length mismatch (relative to last indication)
4571 at the csem interface is detected. */
4572#define UCM_REG_CSEM_LENGTH_MIS 0xe0160
4573/* [RW 3] The weight of the input csem in the WRR mechanism. 0 stands for
4574 weight 8 (the most prioritised); 1 stands for weight 1(least
4575 prioritised); 2 stands for weight 2; tc. */
4576#define UCM_REG_CSEM_WEIGHT 0xe00b8
4577/* [RW 1] Input dorq Interface enable. If 0 - the valid input is
4578 disregarded; acknowledge output is deasserted; all other signals are
4579 treated as usual; if 1 - normal activity. */
4580#define UCM_REG_DORQ_IFEN 0xe0030
4581/* [RC 1] Set when the message length mismatch (relative to last indication)
4582 at the dorq interface is detected. */
4583#define UCM_REG_DORQ_LENGTH_MIS 0xe0168
4584/* [RW 3] The weight of the input dorq in the WRR mechanism. 0 stands for
4585 weight 8 (the most prioritised); 1 stands for weight 1(least
4586 prioritised); 2 stands for weight 2; tc. */
4587#define UCM_REG_DORQ_WEIGHT 0xe00c0
4588/* [RW 8] The Event ID in case ErrorFlg input message bit is set. */
4589#define UCM_REG_ERR_EVNT_ID 0xe00a4
4590/* [RW 28] The CM erroneous header for QM and Timers formatting. */
4591#define UCM_REG_ERR_UCM_HDR 0xe00a0
4592/* [RW 8] The Event ID for Timers expiration. */
4593#define UCM_REG_EXPR_EVNT_ID 0xe00a8
4594/* [RW 8] FIC0 output initial credit. Max credit available - 255.Write
4595 writes the initial credit value; read returns the current value of the
4596 credit counter. Must be initialized to 64 at start-up. */
4597#define UCM_REG_FIC0_INIT_CRD 0xe020c
4598/* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
4599 writes the initial credit value; read returns the current value of the
4600 credit counter. Must be initialized to 64 at start-up. */
4601#define UCM_REG_FIC1_INIT_CRD 0xe0210
4602/* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1
4603 - strict priority defined by ~ucm_registers_gr_ag_pr.gr_ag_pr;
4604 ~ucm_registers_gr_ld0_pr.gr_ld0_pr and
4605 ~ucm_registers_gr_ld1_pr.gr_ld1_pr. */
4606#define UCM_REG_GR_ARB_TYPE 0xe0144
4607/* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
4608 highest priority is 3. It is supposed that the Store channel group is
4609 compliment to the others. */
4610#define UCM_REG_GR_LD0_PR 0xe014c
4611/* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
4612 highest priority is 3. It is supposed that the Store channel group is
4613 compliment to the others. */
4614#define UCM_REG_GR_LD1_PR 0xe0150
4615/* [RW 2] The queue index for invalidate counter flag decision. */
4616#define UCM_REG_INV_CFLG_Q 0xe00e4
4617/* [RW 5] The number of double REG-pairs; loaded from the STORM context and
4618 sent to STORM; for a specific connection type. the double REG-pairs are
4619 used in order to align to STORM context row size of 128 bits. The offset
4620 of these data in the STORM context is always 0. Index _i stands for the
4621 connection type (one of 16). */
4622#define UCM_REG_N_SM_CTX_LD_0 0xe0054
4623#define UCM_REG_N_SM_CTX_LD_1 0xe0058
4624#define UCM_REG_N_SM_CTX_LD_2 0xe005c
4625#define UCM_REG_N_SM_CTX_LD_3 0xe0060
4626#define UCM_REG_N_SM_CTX_LD_4 0xe0064
4627#define UCM_REG_N_SM_CTX_LD_5 0xe0068
4628#define UCM_REG_PHYS_QNUM0_0 0xe0110
4629#define UCM_REG_PHYS_QNUM0_1 0xe0114
4630#define UCM_REG_PHYS_QNUM1_0 0xe0118
4631#define UCM_REG_PHYS_QNUM1_1 0xe011c
4632#define UCM_REG_PHYS_QNUM2_0 0xe0120
4633#define UCM_REG_PHYS_QNUM2_1 0xe0124
4634#define UCM_REG_PHYS_QNUM3_0 0xe0128
4635#define UCM_REG_PHYS_QNUM3_1 0xe012c
4636/* [RW 8] The Event ID for Timers formatting in case of stop done. */
4637#define UCM_REG_STOP_EVNT_ID 0xe00ac
4638/* [RC 1] Set when the message length mismatch (relative to last indication)
4639 at the STORM interface is detected. */
4640#define UCM_REG_STORM_LENGTH_MIS 0xe0154
4641/* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
4642 disregarded; acknowledge output is deasserted; all other signals are
4643 treated as usual; if 1 - normal activity. */
4644#define UCM_REG_STORM_UCM_IFEN 0xe0010
4645/* [RW 3] The weight of the STORM input in the WRR mechanism. 0 stands for
4646 weight 8 (the most prioritised); 1 stands for weight 1(least
4647 prioritised); 2 stands for weight 2; tc. */
4648#define UCM_REG_STORM_WEIGHT 0xe00b0
4649/* [RW 4] Timers output initial credit. Max credit available - 15.Write
4650 writes the initial credit value; read returns the current value of the
4651 credit counter. Must be initialized to 4 at start-up. */
4652#define UCM_REG_TM_INIT_CRD 0xe021c
4653/* [RW 28] The CM header for Timers expiration command. */
4654#define UCM_REG_TM_UCM_HDR 0xe009c
4655/* [RW 1] Timers - CM Interface enable. If 0 - the valid input is
4656 disregarded; acknowledge output is deasserted; all other signals are
4657 treated as usual; if 1 - normal activity. */
4658#define UCM_REG_TM_UCM_IFEN 0xe001c
4659/* [RW 3] The weight of the Timers input in the WRR mechanism. 0 stands for
4660 weight 8 (the most prioritised); 1 stands for weight 1(least
4661 prioritised); 2 stands for weight 2; tc. */
4662#define UCM_REG_TM_WEIGHT 0xe00d4
4663/* [RW 1] Input tsem Interface enable. If 0 - the valid input is
4664 disregarded; acknowledge output is deasserted; all other signals are
4665 treated as usual; if 1 - normal activity. */
4666#define UCM_REG_TSEM_IFEN 0xe0024
4667/* [RC 1] Set when the message length mismatch (relative to last indication)
4668 at the tsem interface is detected. */
4669#define UCM_REG_TSEM_LENGTH_MIS 0xe015c
4670/* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for
4671 weight 8 (the most prioritised); 1 stands for weight 1(least
4672 prioritised); 2 stands for weight 2; tc. */
4673#define UCM_REG_TSEM_WEIGHT 0xe00b4
4674/* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
4675 acknowledge output is deasserted; all other signals are treated as usual;
4676 if 1 - normal activity. */
4677#define UCM_REG_UCM_CFC_IFEN 0xe0044
4678/* [RW 11] Interrupt mask register #0 read/write */
4679#define UCM_REG_UCM_INT_MASK 0xe01d4
4680/* [R 11] Interrupt register #0 read */
4681#define UCM_REG_UCM_INT_STS 0xe01c8
4682/* [RW 27] Parity mask register #0 read/write */
4683#define UCM_REG_UCM_PRTY_MASK 0xe01e4
4684/* [R 27] Parity register #0 read */
4685#define UCM_REG_UCM_PRTY_STS 0xe01d8
4686/* [RC 27] Parity register #0 read clear */
4687#define UCM_REG_UCM_PRTY_STS_CLR 0xe01dc
4688/* [RW 2] The size of AG context region 0 in REG-pairs. Designates the MS
4689 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
4690 Is used to determine the number of the AG context REG-pairs written back;
4691 when the Reg1WbFlg isn't set. */
4692#define UCM_REG_UCM_REG0_SZ 0xe00dc
4693/* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
4694 disregarded; valid is deasserted; all other signals are treated as usual;
4695 if 1 - normal activity. */
4696#define UCM_REG_UCM_STORM0_IFEN 0xe0004
4697/* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
4698 disregarded; valid is deasserted; all other signals are treated as usual;
4699 if 1 - normal activity. */
4700#define UCM_REG_UCM_STORM1_IFEN 0xe0008
4701/* [RW 1] CM - Timers Interface enable. If 0 - the valid input is
4702 disregarded; acknowledge output is deasserted; all other signals are
4703 treated as usual; if 1 - normal activity. */
4704#define UCM_REG_UCM_TM_IFEN 0xe0020
4705/* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
4706 disregarded; valid is deasserted; all other signals are treated as usual;
4707 if 1 - normal activity. */
4708#define UCM_REG_UCM_UQM_IFEN 0xe000c
4709/* [RW 1] If set the Q index; received from the QM is inserted to event ID. */
4710#define UCM_REG_UCM_UQM_USE_Q 0xe00d8
4711/* [RW 6] QM output initial credit. Max credit available - 32.Write writes
4712 the initial credit value; read returns the current value of the credit
4713 counter. Must be initialized to 32 at start-up. */
4714#define UCM_REG_UQM_INIT_CRD 0xe0220
4715/* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
4716 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
4717 prioritised); 2 stands for weight 2; tc. */
4718#define UCM_REG_UQM_P_WEIGHT 0xe00cc
4719/* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0
4720 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
4721 prioritised); 2 stands for weight 2; tc. */
4722#define UCM_REG_UQM_S_WEIGHT 0xe00d0
4723/* [RW 28] The CM header value for QM request (primary). */
4724#define UCM_REG_UQM_UCM_HDR_P 0xe0094
4725/* [RW 28] The CM header value for QM request (secondary). */
4726#define UCM_REG_UQM_UCM_HDR_S 0xe0098
4727/* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
4728 acknowledge output is deasserted; all other signals are treated as usual;
4729 if 1 - normal activity. */
4730#define UCM_REG_UQM_UCM_IFEN 0xe0014
4731/* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
4732 acknowledge output is deasserted; all other signals are treated as usual;
4733 if 1 - normal activity. */
4734#define UCM_REG_USDM_IFEN 0xe0018
4735/* [RC 1] Set when the message length mismatch (relative to last indication)
4736 at the SDM interface is detected. */
4737#define UCM_REG_USDM_LENGTH_MIS 0xe0158
4738/* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for
4739 weight 8 (the most prioritised); 1 stands for weight 1(least
4740 prioritised); 2 stands for weight 2; tc. */
4741#define UCM_REG_USDM_WEIGHT 0xe00c8
4742/* [RW 1] Input xsem Interface enable. If 0 - the valid input is
4743 disregarded; acknowledge output is deasserted; all other signals are
4744 treated as usual; if 1 - normal activity. */
4745#define UCM_REG_XSEM_IFEN 0xe002c
4746/* [RC 1] Set when the message length mismatch (relative to last indication)
4747 at the xsem interface isdetected. */
4748#define UCM_REG_XSEM_LENGTH_MIS 0xe0164
4749/* [RW 3] The weight of the input xsem in the WRR mechanism. 0 stands for
4750 weight 8 (the most prioritised); 1 stands for weight 1(least
4751 prioritised); 2 stands for weight 2; tc. */
4752#define UCM_REG_XSEM_WEIGHT 0xe00bc
4753/* [RW 20] Indirect access to the descriptor table of the XX protection
4754 mechanism. The fields are:[5:0] - message length; 14:6] - message
4755 pointer; 19:15] - next pointer. */
4756#define UCM_REG_XX_DESCR_TABLE 0xe0280
4757#define UCM_REG_XX_DESCR_TABLE_SIZE 27
4758/* [R 6] Use to read the XX protection Free counter. */
4759#define UCM_REG_XX_FREE 0xe016c
4760/* [RW 6] Initial value for the credit counter; responsible for fulfilling
4761 of the Input Stage XX protection buffer by the XX protection pending
4762 messages. Write writes the initial credit value; read returns the current
4763 value of the credit counter. Must be initialized to 12 at start-up. */
4764#define UCM_REG_XX_INIT_CRD 0xe0224
4765/* [RW 6] The maximum number of pending messages; which may be stored in XX
4766 protection. ~ucm_registers_xx_free.xx_free read on read. */
4767#define UCM_REG_XX_MSG_NUM 0xe0228
4768/* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
4769#define UCM_REG_XX_OVFL_EVNT_ID 0xe004c
4770/* [RW 16] Indirect access to the XX table of the XX protection mechanism.
4771 The fields are: [4:0] - tail pointer; 10:5] - Link List size; 15:11] -
4772 header pointer. */
4773#define UCM_REG_XX_TABLE 0xe0300
4774#define UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE (0x1<<28)
4775#define UMAC_COMMAND_CONFIG_REG_LOOP_ENA (0x1<<15)
4776#define UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK (0x1<<24)
4777#define UMAC_COMMAND_CONFIG_REG_PAD_EN (0x1<<5)
4778#define UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE (0x1<<8)
4779#define UMAC_COMMAND_CONFIG_REG_PROMIS_EN (0x1<<4)
4780#define UMAC_COMMAND_CONFIG_REG_RX_ENA (0x1<<1)
4781#define UMAC_COMMAND_CONFIG_REG_SW_RESET (0x1<<13)
4782#define UMAC_COMMAND_CONFIG_REG_TX_ENA (0x1<<0)
4783#define UMAC_REG_COMMAND_CONFIG 0x8
4784/* [RW 32] Register Bit 0 refers to Bit 16 of the MAC address; Bit 1 refers
4785 * to bit 17 of the MAC address etc. */
4786#define UMAC_REG_MAC_ADDR0 0xc
4787/* [RW 16] Register Bit 0 refers to Bit 0 of the MAC address; Register Bit 1
4788 * refers to Bit 1 of the MAC address etc. Bits 16 to 31 are reserved. */
4789#define UMAC_REG_MAC_ADDR1 0x10
4790/* [RW 14] Defines a 14-Bit maximum frame length used by the MAC receive
4791 * logic to check frames. */
4792#define UMAC_REG_MAXFR 0x14
4793/* [RW 8] The event id for aggregated interrupt 0 */
4794#define USDM_REG_AGG_INT_EVENT_0 0xc4038
4795#define USDM_REG_AGG_INT_EVENT_1 0xc403c
4796#define USDM_REG_AGG_INT_EVENT_2 0xc4040
4797#define USDM_REG_AGG_INT_EVENT_4 0xc4048
4798#define USDM_REG_AGG_INT_EVENT_5 0xc404c
4799#define USDM_REG_AGG_INT_EVENT_6 0xc4050
4800/* [RW 1] For each aggregated interrupt index whether the mode is normal (0)
4801 or auto-mask-mode (1) */
4802#define USDM_REG_AGG_INT_MODE_0 0xc41b8
4803#define USDM_REG_AGG_INT_MODE_1 0xc41bc
4804#define USDM_REG_AGG_INT_MODE_4 0xc41c8
4805#define USDM_REG_AGG_INT_MODE_5 0xc41cc
4806#define USDM_REG_AGG_INT_MODE_6 0xc41d0
4807/* [RW 1] The T bit for aggregated interrupt 5 */
4808#define USDM_REG_AGG_INT_T_5 0xc40cc
4809#define USDM_REG_AGG_INT_T_6 0xc40d0
4810/* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
4811#define USDM_REG_CFC_RSP_START_ADDR 0xc4008
4812/* [RW 16] The maximum value of the completion counter #0 */
4813#define USDM_REG_CMP_COUNTER_MAX0 0xc401c
4814/* [RW 16] The maximum value of the completion counter #1 */
4815#define USDM_REG_CMP_COUNTER_MAX1 0xc4020
4816/* [RW 16] The maximum value of the completion counter #2 */
4817#define USDM_REG_CMP_COUNTER_MAX2 0xc4024
4818/* [RW 16] The maximum value of the completion counter #3 */
4819#define USDM_REG_CMP_COUNTER_MAX3 0xc4028
4820/* [RW 13] The start address in the internal RAM for the completion
4821 counters. */
4822#define USDM_REG_CMP_COUNTER_START_ADDR 0xc400c
4823#define USDM_REG_ENABLE_IN1 0xc4238
4824#define USDM_REG_ENABLE_IN2 0xc423c
4825#define USDM_REG_ENABLE_OUT1 0xc4240
4826#define USDM_REG_ENABLE_OUT2 0xc4244
4827/* [RW 4] The initial number of messages that can be sent to the pxp control
4828 interface without receiving any ACK. */
4829#define USDM_REG_INIT_CREDIT_PXP_CTRL 0xc44c0
4830/* [ST 32] The number of ACK after placement messages received */
4831#define USDM_REG_NUM_OF_ACK_AFTER_PLACE 0xc4280
4832/* [ST 32] The number of packet end messages received from the parser */
4833#define USDM_REG_NUM_OF_PKT_END_MSG 0xc4278
4834/* [ST 32] The number of requests received from the pxp async if */
4835#define USDM_REG_NUM_OF_PXP_ASYNC_REQ 0xc427c
4836/* [ST 32] The number of commands received in queue 0 */
4837#define USDM_REG_NUM_OF_Q0_CMD 0xc4248
4838/* [ST 32] The number of commands received in queue 10 */
4839#define USDM_REG_NUM_OF_Q10_CMD 0xc4270
4840/* [ST 32] The number of commands received in queue 11 */
4841#define USDM_REG_NUM_OF_Q11_CMD 0xc4274
4842/* [ST 32] The number of commands received in queue 1 */
4843#define USDM_REG_NUM_OF_Q1_CMD 0xc424c
4844/* [ST 32] The number of commands received in queue 2 */
4845#define USDM_REG_NUM_OF_Q2_CMD 0xc4250
4846/* [ST 32] The number of commands received in queue 3 */
4847#define USDM_REG_NUM_OF_Q3_CMD 0xc4254
4848/* [ST 32] The number of commands received in queue 4 */
4849#define USDM_REG_NUM_OF_Q4_CMD 0xc4258
4850/* [ST 32] The number of commands received in queue 5 */
4851#define USDM_REG_NUM_OF_Q5_CMD 0xc425c
4852/* [ST 32] The number of commands received in queue 6 */
4853#define USDM_REG_NUM_OF_Q6_CMD 0xc4260
4854/* [ST 32] The number of commands received in queue 7 */
4855#define USDM_REG_NUM_OF_Q7_CMD 0xc4264
4856/* [ST 32] The number of commands received in queue 8 */
4857#define USDM_REG_NUM_OF_Q8_CMD 0xc4268
4858/* [ST 32] The number of commands received in queue 9 */
4859#define USDM_REG_NUM_OF_Q9_CMD 0xc426c
4860/* [RW 13] The start address in the internal RAM for the packet end message */
4861#define USDM_REG_PCK_END_MSG_START_ADDR 0xc4014
4862/* [RW 13] The start address in the internal RAM for queue counters */
4863#define USDM_REG_Q_COUNTER_START_ADDR 0xc4010
4864/* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
4865#define USDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0xc4550
4866/* [R 1] parser fifo empty in sdm_sync block */
4867#define USDM_REG_SYNC_PARSER_EMPTY 0xc4558
4868/* [R 1] parser serial fifo empty in sdm_sync block */
4869#define USDM_REG_SYNC_SYNC_EMPTY 0xc4560
4870/* [RW 32] Tick for timer counter. Applicable only when
4871 ~usdm_registers_timer_tick_enable.timer_tick_enable =1 */
4872#define USDM_REG_TIMER_TICK 0xc4000
4873/* [RW 32] Interrupt mask register #0 read/write */
4874#define USDM_REG_USDM_INT_MASK_0 0xc42a0
4875#define USDM_REG_USDM_INT_MASK_1 0xc42b0
4876/* [R 32] Interrupt register #0 read */
4877#define USDM_REG_USDM_INT_STS_0 0xc4294
4878#define USDM_REG_USDM_INT_STS_1 0xc42a4
4879/* [RW 11] Parity mask register #0 read/write */
4880#define USDM_REG_USDM_PRTY_MASK 0xc42c0
4881/* [R 11] Parity register #0 read */
4882#define USDM_REG_USDM_PRTY_STS 0xc42b4
4883/* [RC 11] Parity register #0 read clear */
4884#define USDM_REG_USDM_PRTY_STS_CLR 0xc42b8
4885/* [RW 5] The number of time_slots in the arbitration cycle */
4886#define USEM_REG_ARB_CYCLE_SIZE 0x300034
4887/* [RW 3] The source that is associated with arbitration element 0. Source
4888 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4889 sleeping thread with priority 1; 4- sleeping thread with priority 2 */
4890#define USEM_REG_ARB_ELEMENT0 0x300020
4891/* [RW 3] The source that is associated with arbitration element 1. Source
4892 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4893 sleeping thread with priority 1; 4- sleeping thread with priority 2.
4894 Could not be equal to register ~usem_registers_arb_element0.arb_element0 */
4895#define USEM_REG_ARB_ELEMENT1 0x300024
4896/* [RW 3] The source that is associated with arbitration element 2. Source
4897 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4898 sleeping thread with priority 1; 4- sleeping thread with priority 2.
4899 Could not be equal to register ~usem_registers_arb_element0.arb_element0
4900 and ~usem_registers_arb_element1.arb_element1 */
4901#define USEM_REG_ARB_ELEMENT2 0x300028
4902/* [RW 3] The source that is associated with arbitration element 3. Source
4903 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4904 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could
4905 not be equal to register ~usem_registers_arb_element0.arb_element0 and
4906 ~usem_registers_arb_element1.arb_element1 and
4907 ~usem_registers_arb_element2.arb_element2 */
4908#define USEM_REG_ARB_ELEMENT3 0x30002c
4909/* [RW 3] The source that is associated with arbitration element 4. Source
4910 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4911 sleeping thread with priority 1; 4- sleeping thread with priority 2.
4912 Could not be equal to register ~usem_registers_arb_element0.arb_element0
4913 and ~usem_registers_arb_element1.arb_element1 and
4914 ~usem_registers_arb_element2.arb_element2 and
4915 ~usem_registers_arb_element3.arb_element3 */
4916#define USEM_REG_ARB_ELEMENT4 0x300030
4917#define USEM_REG_ENABLE_IN 0x3000a4
4918#define USEM_REG_ENABLE_OUT 0x3000a8
4919/* [RW 32] This address space contains all registers and memories that are
4920 placed in SEM_FAST block. The SEM_FAST registers are described in
4921 appendix B. In order to access the sem_fast registers the base address
4922 ~fast_memory.fast_memory should be added to eachsem_fast register offset. */
4923#define USEM_REG_FAST_MEMORY 0x320000
4924/* [RW 1] Disables input messages from FIC0 May be updated during run_time
4925 by the microcode */
4926#define USEM_REG_FIC0_DISABLE 0x300224
4927/* [RW 1] Disables input messages from FIC1 May be updated during run_time
4928 by the microcode */
4929#define USEM_REG_FIC1_DISABLE 0x300234
4930/* [RW 15] Interrupt table Read and write access to it is not possible in
4931 the middle of the work */
4932#define USEM_REG_INT_TABLE 0x300400
4933/* [ST 24] Statistics register. The number of messages that entered through
4934 FIC0 */
4935#define USEM_REG_MSG_NUM_FIC0 0x300000
4936/* [ST 24] Statistics register. The number of messages that entered through
4937 FIC1 */
4938#define USEM_REG_MSG_NUM_FIC1 0x300004
4939/* [ST 24] Statistics register. The number of messages that were sent to
4940 FOC0 */
4941#define USEM_REG_MSG_NUM_FOC0 0x300008
4942/* [ST 24] Statistics register. The number of messages that were sent to
4943 FOC1 */
4944#define USEM_REG_MSG_NUM_FOC1 0x30000c
4945/* [ST 24] Statistics register. The number of messages that were sent to
4946 FOC2 */
4947#define USEM_REG_MSG_NUM_FOC2 0x300010
4948/* [ST 24] Statistics register. The number of messages that were sent to
4949 FOC3 */
4950#define USEM_REG_MSG_NUM_FOC3 0x300014
4951/* [RW 1] Disables input messages from the passive buffer May be updated
4952 during run_time by the microcode */
4953#define USEM_REG_PAS_DISABLE 0x30024c
4954/* [WB 128] Debug only. Passive buffer memory */
4955#define USEM_REG_PASSIVE_BUFFER 0x302000
4956/* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
4957#define USEM_REG_PRAM 0x340000
4958/* [R 16] Valid sleeping threads indication have bit per thread */
4959#define USEM_REG_SLEEP_THREADS_VALID 0x30026c
4960/* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
4961#define USEM_REG_SLOW_EXT_STORE_EMPTY 0x3002a0
4962/* [RW 16] List of free threads . There is a bit per thread. */
4963#define USEM_REG_THREADS_LIST 0x3002e4
4964/* [RW 3] The arbitration scheme of time_slot 0 */
4965#define USEM_REG_TS_0_AS 0x300038
4966/* [RW 3] The arbitration scheme of time_slot 10 */
4967#define USEM_REG_TS_10_AS 0x300060
4968/* [RW 3] The arbitration scheme of time_slot 11 */
4969#define USEM_REG_TS_11_AS 0x300064
4970/* [RW 3] The arbitration scheme of time_slot 12 */
4971#define USEM_REG_TS_12_AS 0x300068
4972/* [RW 3] The arbitration scheme of time_slot 13 */
4973#define USEM_REG_TS_13_AS 0x30006c
4974/* [RW 3] The arbitration scheme of time_slot 14 */
4975#define USEM_REG_TS_14_AS 0x300070
4976/* [RW 3] The arbitration scheme of time_slot 15 */
4977#define USEM_REG_TS_15_AS 0x300074
4978/* [RW 3] The arbitration scheme of time_slot 16 */
4979#define USEM_REG_TS_16_AS 0x300078
4980/* [RW 3] The arbitration scheme of time_slot 17 */
4981#define USEM_REG_TS_17_AS 0x30007c
4982/* [RW 3] The arbitration scheme of time_slot 18 */
4983#define USEM_REG_TS_18_AS 0x300080
4984/* [RW 3] The arbitration scheme of time_slot 1 */
4985#define USEM_REG_TS_1_AS 0x30003c
4986/* [RW 3] The arbitration scheme of time_slot 2 */
4987#define USEM_REG_TS_2_AS 0x300040
4988/* [RW 3] The arbitration scheme of time_slot 3 */
4989#define USEM_REG_TS_3_AS 0x300044
4990/* [RW 3] The arbitration scheme of time_slot 4 */
4991#define USEM_REG_TS_4_AS 0x300048
4992/* [RW 3] The arbitration scheme of time_slot 5 */
4993#define USEM_REG_TS_5_AS 0x30004c
4994/* [RW 3] The arbitration scheme of time_slot 6 */
4995#define USEM_REG_TS_6_AS 0x300050
4996/* [RW 3] The arbitration scheme of time_slot 7 */
4997#define USEM_REG_TS_7_AS 0x300054
4998/* [RW 3] The arbitration scheme of time_slot 8 */
4999#define USEM_REG_TS_8_AS 0x300058
5000/* [RW 3] The arbitration scheme of time_slot 9 */
5001#define USEM_REG_TS_9_AS 0x30005c
5002/* [RW 32] Interrupt mask register #0 read/write */
5003#define USEM_REG_USEM_INT_MASK_0 0x300110
5004#define USEM_REG_USEM_INT_MASK_1 0x300120
5005/* [R 32] Interrupt register #0 read */
5006#define USEM_REG_USEM_INT_STS_0 0x300104
5007#define USEM_REG_USEM_INT_STS_1 0x300114
5008/* [RW 32] Parity mask register #0 read/write */
5009#define USEM_REG_USEM_PRTY_MASK_0 0x300130
5010#define USEM_REG_USEM_PRTY_MASK_1 0x300140
5011/* [R 32] Parity register #0 read */
5012#define USEM_REG_USEM_PRTY_STS_0 0x300124
5013#define USEM_REG_USEM_PRTY_STS_1 0x300134
5014/* [RC 32] Parity register #0 read clear */
5015#define USEM_REG_USEM_PRTY_STS_CLR_0 0x300128
5016#define USEM_REG_USEM_PRTY_STS_CLR_1 0x300138
5017/* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 64
5018 * VF; values 64-67 reset error for 4 PF; values 68-127 are not valid. */
5019#define USEM_REG_VFPF_ERR_NUM 0x300380
5020#define VFC_MEMORIES_RST_REG_CAM_RST (0x1<<0)
5021#define VFC_MEMORIES_RST_REG_RAM_RST (0x1<<1)
5022#define VFC_REG_MEMORIES_RST 0x1943c
5023/* [RW 32] Indirect access to AG context with 32-bits granularity. The bits
5024 * [12:8] of the address should be the offset within the accessed LCID
5025 * context; the bits [7:0] are the accessed LCID.Example: to write to REG10
5026 * LCID100. The RBC address should be 13'ha64. */
5027#define XCM_REG_AG_CTX 0x28000
5028/* [RW 2] The queue index for registration on Aux1 counter flag. */
5029#define XCM_REG_AUX1_Q 0x20134
5030/* [RW 2] Per each decision rule the queue index to register to. */
5031#define XCM_REG_AUX_CNT_FLG_Q_19 0x201b0
5032/* [R 5] Used to read the XX protection CAM occupancy counter. */
5033#define XCM_REG_CAM_OCCUP 0x20244
5034/* [RW 1] CDU AG read Interface enable. If 0 - the request input is
5035 disregarded; valid output is deasserted; all other signals are treated as
5036 usual; if 1 - normal activity. */
5037#define XCM_REG_CDU_AG_RD_IFEN 0x20044
5038/* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
5039 are disregarded; all other signals are treated as usual; if 1 - normal
5040 activity. */
5041#define XCM_REG_CDU_AG_WR_IFEN 0x20040
5042/* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
5043 disregarded; valid output is deasserted; all other signals are treated as
5044 usual; if 1 - normal activity. */
5045#define XCM_REG_CDU_SM_RD_IFEN 0x2004c
5046/* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
5047 input is disregarded; all other signals are treated as usual; if 1 -
5048 normal activity. */
5049#define XCM_REG_CDU_SM_WR_IFEN 0x20048
5050/* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
5051 the initial credit value; read returns the current value of the credit
5052 counter. Must be initialized to 1 at start-up. */
5053#define XCM_REG_CFC_INIT_CRD 0x20404
5054/* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for
5055 weight 8 (the most prioritised); 1 stands for weight 1(least
5056 prioritised); 2 stands for weight 2; tc. */
5057#define XCM_REG_CP_WEIGHT 0x200dc
5058/* [RW 1] Input csem Interface enable. If 0 - the valid input is
5059 disregarded; acknowledge output is deasserted; all other signals are
5060 treated as usual; if 1 - normal activity. */
5061#define XCM_REG_CSEM_IFEN 0x20028
5062/* [RC 1] Set at message length mismatch (relative to last indication) at
5063 the csem interface. */
5064#define XCM_REG_CSEM_LENGTH_MIS 0x20228
5065/* [RW 3] The weight of the input csem in the WRR mechanism. 0 stands for
5066 weight 8 (the most prioritised); 1 stands for weight 1(least
5067 prioritised); 2 stands for weight 2; tc. */
5068#define XCM_REG_CSEM_WEIGHT 0x200c4
5069/* [RW 1] Input dorq Interface enable. If 0 - the valid input is
5070 disregarded; acknowledge output is deasserted; all other signals are
5071 treated as usual; if 1 - normal activity. */
5072#define XCM_REG_DORQ_IFEN 0x20030
5073/* [RC 1] Set at message length mismatch (relative to last indication) at
5074 the dorq interface. */
5075#define XCM_REG_DORQ_LENGTH_MIS 0x20230
5076/* [RW 3] The weight of the input dorq in the WRR mechanism. 0 stands for
5077 weight 8 (the most prioritised); 1 stands for weight 1(least
5078 prioritised); 2 stands for weight 2; tc. */
5079#define XCM_REG_DORQ_WEIGHT 0x200cc
5080/* [RW 8] The Event ID in case the ErrorFlg input message bit is set. */
5081#define XCM_REG_ERR_EVNT_ID 0x200b0
5082/* [RW 28] The CM erroneous header for QM and Timers formatting. */
5083#define XCM_REG_ERR_XCM_HDR 0x200ac
5084/* [RW 8] The Event ID for Timers expiration. */
5085#define XCM_REG_EXPR_EVNT_ID 0x200b4
5086/* [RW 8] FIC0 output initial credit. Max credit available - 255.Write
5087 writes the initial credit value; read returns the current value of the
5088 credit counter. Must be initialized to 64 at start-up. */
5089#define XCM_REG_FIC0_INIT_CRD 0x2040c
5090/* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
5091 writes the initial credit value; read returns the current value of the
5092 credit counter. Must be initialized to 64 at start-up. */
5093#define XCM_REG_FIC1_INIT_CRD 0x20410
5094#define XCM_REG_GLB_DEL_ACK_MAX_CNT_0 0x20118
5095#define XCM_REG_GLB_DEL_ACK_MAX_CNT_1 0x2011c
5096#define XCM_REG_GLB_DEL_ACK_TMR_VAL_0 0x20108
5097#define XCM_REG_GLB_DEL_ACK_TMR_VAL_1 0x2010c
5098/* [RW 1] Arbitratiojn between Input Arbiter groups: 0 - fair Round-Robin; 1
5099 - strict priority defined by ~xcm_registers_gr_ag_pr.gr_ag_pr;
5100 ~xcm_registers_gr_ld0_pr.gr_ld0_pr and
5101 ~xcm_registers_gr_ld1_pr.gr_ld1_pr. */
5102#define XCM_REG_GR_ARB_TYPE 0x2020c
5103/* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
5104 highest priority is 3. It is supposed that the Channel group is the
5105 compliment of the other 3 groups. */
5106#define XCM_REG_GR_LD0_PR 0x20214
5107/* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
5108 highest priority is 3. It is supposed that the Channel group is the
5109 compliment of the other 3 groups. */
5110#define XCM_REG_GR_LD1_PR 0x20218
5111/* [RW 1] Input nig0 Interface enable. If 0 - the valid input is
5112 disregarded; acknowledge output is deasserted; all other signals are
5113 treated as usual; if 1 - normal activity. */
5114#define XCM_REG_NIG0_IFEN 0x20038
5115/* [RC 1] Set at message length mismatch (relative to last indication) at
5116 the nig0 interface. */
5117#define XCM_REG_NIG0_LENGTH_MIS 0x20238
5118/* [RW 3] The weight of the input nig0 in the WRR mechanism. 0 stands for
5119 weight 8 (the most prioritised); 1 stands for weight 1(least
5120 prioritised); 2 stands for weight 2; tc. */
5121#define XCM_REG_NIG0_WEIGHT 0x200d4
5122/* [RW 1] Input nig1 Interface enable. If 0 - the valid input is
5123 disregarded; acknowledge output is deasserted; all other signals are
5124 treated as usual; if 1 - normal activity. */
5125#define XCM_REG_NIG1_IFEN 0x2003c
5126/* [RC 1] Set at message length mismatch (relative to last indication) at
5127 the nig1 interface. */
5128#define XCM_REG_NIG1_LENGTH_MIS 0x2023c
5129/* [RW 5] The number of double REG-pairs; loaded from the STORM context and
5130 sent to STORM; for a specific connection type. The double REG-pairs are
5131 used in order to align to STORM context row size of 128 bits. The offset
5132 of these data in the STORM context is always 0. Index _i stands for the
5133 connection type (one of 16). */
5134#define XCM_REG_N_SM_CTX_LD_0 0x20060
5135#define XCM_REG_N_SM_CTX_LD_1 0x20064
5136#define XCM_REG_N_SM_CTX_LD_2 0x20068
5137#define XCM_REG_N_SM_CTX_LD_3 0x2006c
5138#define XCM_REG_N_SM_CTX_LD_4 0x20070
5139#define XCM_REG_N_SM_CTX_LD_5 0x20074
5140/* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded;
5141 acknowledge output is deasserted; all other signals are treated as usual;
5142 if 1 - normal activity. */
5143#define XCM_REG_PBF_IFEN 0x20034
5144/* [RC 1] Set at message length mismatch (relative to last indication) at
5145 the pbf interface. */
5146#define XCM_REG_PBF_LENGTH_MIS 0x20234
5147/* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for
5148 weight 8 (the most prioritised); 1 stands for weight 1(least
5149 prioritised); 2 stands for weight 2; tc. */
5150#define XCM_REG_PBF_WEIGHT 0x200d0
5151#define XCM_REG_PHYS_QNUM3_0 0x20100
5152#define XCM_REG_PHYS_QNUM3_1 0x20104
5153/* [RW 8] The Event ID for Timers formatting in case of stop done. */
5154#define XCM_REG_STOP_EVNT_ID 0x200b8
5155/* [RC 1] Set at message length mismatch (relative to last indication) at
5156 the STORM interface. */
5157#define XCM_REG_STORM_LENGTH_MIS 0x2021c
5158/* [RW 3] The weight of the STORM input in the WRR mechanism. 0 stands for
5159 weight 8 (the most prioritised); 1 stands for weight 1(least
5160 prioritised); 2 stands for weight 2; tc. */
5161#define XCM_REG_STORM_WEIGHT 0x200bc
5162/* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
5163 disregarded; acknowledge output is deasserted; all other signals are
5164 treated as usual; if 1 - normal activity. */
5165#define XCM_REG_STORM_XCM_IFEN 0x20010
5166/* [RW 4] Timers output initial credit. Max credit available - 15.Write
5167 writes the initial credit value; read returns the current value of the
5168 credit counter. Must be initialized to 4 at start-up. */
5169#define XCM_REG_TM_INIT_CRD 0x2041c
5170/* [RW 3] The weight of the Timers input in the WRR mechanism. 0 stands for
5171 weight 8 (the most prioritised); 1 stands for weight 1(least
5172 prioritised); 2 stands for weight 2; tc. */
5173#define XCM_REG_TM_WEIGHT 0x200ec
5174/* [RW 28] The CM header for Timers expiration command. */
5175#define XCM_REG_TM_XCM_HDR 0x200a8
5176/* [RW 1] Timers - CM Interface enable. If 0 - the valid input is
5177 disregarded; acknowledge output is deasserted; all other signals are
5178 treated as usual; if 1 - normal activity. */
5179#define XCM_REG_TM_XCM_IFEN 0x2001c
5180/* [RW 1] Input tsem Interface enable. If 0 - the valid input is
5181 disregarded; acknowledge output is deasserted; all other signals are
5182 treated as usual; if 1 - normal activity. */
5183#define XCM_REG_TSEM_IFEN 0x20024
5184/* [RC 1] Set at message length mismatch (relative to last indication) at
5185 the tsem interface. */
5186#define XCM_REG_TSEM_LENGTH_MIS 0x20224
5187/* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for
5188 weight 8 (the most prioritised); 1 stands for weight 1(least
5189 prioritised); 2 stands for weight 2; tc. */
5190#define XCM_REG_TSEM_WEIGHT 0x200c0
5191/* [RW 2] The queue index for registration on UNA greater NXT decision rule. */
5192#define XCM_REG_UNA_GT_NXT_Q 0x20120
5193/* [RW 1] Input usem Interface enable. If 0 - the valid input is
5194 disregarded; acknowledge output is deasserted; all other signals are
5195 treated as usual; if 1 - normal activity. */
5196#define XCM_REG_USEM_IFEN 0x2002c
5197/* [RC 1] Message length mismatch (relative to last indication) at the usem
5198 interface. */
5199#define XCM_REG_USEM_LENGTH_MIS 0x2022c
5200/* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for
5201 weight 8 (the most prioritised); 1 stands for weight 1(least
5202 prioritised); 2 stands for weight 2; tc. */
5203#define XCM_REG_USEM_WEIGHT 0x200c8
5204#define XCM_REG_WU_DA_CNT_CMD00 0x201d4
5205#define XCM_REG_WU_DA_CNT_CMD01 0x201d8
5206#define XCM_REG_WU_DA_CNT_CMD10 0x201dc
5207#define XCM_REG_WU_DA_CNT_CMD11 0x201e0
5208#define XCM_REG_WU_DA_CNT_UPD_VAL00 0x201e4
5209#define XCM_REG_WU_DA_CNT_UPD_VAL01 0x201e8
5210#define XCM_REG_WU_DA_CNT_UPD_VAL10 0x201ec
5211#define XCM_REG_WU_DA_CNT_UPD_VAL11 0x201f0
5212#define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00 0x201c4
5213#define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01 0x201c8
5214#define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD10 0x201cc
5215#define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD11 0x201d0
5216/* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
5217 acknowledge output is deasserted; all other signals are treated as usual;
5218 if 1 - normal activity. */
5219#define XCM_REG_XCM_CFC_IFEN 0x20050
5220/* [RW 14] Interrupt mask register #0 read/write */
5221#define XCM_REG_XCM_INT_MASK 0x202b4
5222/* [R 14] Interrupt register #0 read */
5223#define XCM_REG_XCM_INT_STS 0x202a8
5224/* [RW 30] Parity mask register #0 read/write */
5225#define XCM_REG_XCM_PRTY_MASK 0x202c4
5226/* [R 30] Parity register #0 read */
5227#define XCM_REG_XCM_PRTY_STS 0x202b8
5228/* [RC 30] Parity register #0 read clear */
5229#define XCM_REG_XCM_PRTY_STS_CLR 0x202bc
5230
5231/* [RW 4] The size of AG context region 0 in REG-pairs. Designates the MS
5232 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
5233 Is used to determine the number of the AG context REG-pairs written back;
5234 when the Reg1WbFlg isn't set. */
5235#define XCM_REG_XCM_REG0_SZ 0x200f4
5236/* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
5237 disregarded; valid is deasserted; all other signals are treated as usual;
5238 if 1 - normal activity. */
5239#define XCM_REG_XCM_STORM0_IFEN 0x20004
5240/* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
5241 disregarded; valid is deasserted; all other signals are treated as usual;
5242 if 1 - normal activity. */
5243#define XCM_REG_XCM_STORM1_IFEN 0x20008
5244/* [RW 1] CM - Timers Interface enable. If 0 - the valid input is
5245 disregarded; acknowledge output is deasserted; all other signals are
5246 treated as usual; if 1 - normal activity. */
5247#define XCM_REG_XCM_TM_IFEN 0x20020
5248/* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
5249 disregarded; valid is deasserted; all other signals are treated as usual;
5250 if 1 - normal activity. */
5251#define XCM_REG_XCM_XQM_IFEN 0x2000c
5252/* [RW 1] If set the Q index; received from the QM is inserted to event ID. */
5253#define XCM_REG_XCM_XQM_USE_Q 0x200f0
5254/* [RW 4] The value by which CFC updates the activity counter at QM bypass. */
5255#define XCM_REG_XQM_BYP_ACT_UPD 0x200fc
5256/* [RW 6] QM output initial credit. Max credit available - 32.Write writes
5257 the initial credit value; read returns the current value of the credit
5258 counter. Must be initialized to 32 at start-up. */
5259#define XCM_REG_XQM_INIT_CRD 0x20420
5260/* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
5261 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
5262 prioritised); 2 stands for weight 2; tc. */
5263#define XCM_REG_XQM_P_WEIGHT 0x200e4
5264/* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0
5265 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
5266 prioritised); 2 stands for weight 2; tc. */
5267#define XCM_REG_XQM_S_WEIGHT 0x200e8
5268/* [RW 28] The CM header value for QM request (primary). */
5269#define XCM_REG_XQM_XCM_HDR_P 0x200a0
5270/* [RW 28] The CM header value for QM request (secondary). */
5271#define XCM_REG_XQM_XCM_HDR_S 0x200a4
5272/* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
5273 acknowledge output is deasserted; all other signals are treated as usual;
5274 if 1 - normal activity. */
5275#define XCM_REG_XQM_XCM_IFEN 0x20014
5276/* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
5277 acknowledge output is deasserted; all other signals are treated as usual;
5278 if 1 - normal activity. */
5279#define XCM_REG_XSDM_IFEN 0x20018
5280/* [RC 1] Set at message length mismatch (relative to last indication) at
5281 the SDM interface. */
5282#define XCM_REG_XSDM_LENGTH_MIS 0x20220
5283/* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for
5284 weight 8 (the most prioritised); 1 stands for weight 1(least
5285 prioritised); 2 stands for weight 2; tc. */
5286#define XCM_REG_XSDM_WEIGHT 0x200e0
5287/* [RW 17] Indirect access to the descriptor table of the XX protection
5288 mechanism. The fields are: [5:0] - message length; 11:6] - message
5289 pointer; 16:12] - next pointer. */
5290#define XCM_REG_XX_DESCR_TABLE 0x20480
5291#define XCM_REG_XX_DESCR_TABLE_SIZE 32
5292/* [R 6] Used to read the XX protection Free counter. */
5293#define XCM_REG_XX_FREE 0x20240
5294/* [RW 6] Initial value for the credit counter; responsible for fulfilling
5295 of the Input Stage XX protection buffer by the XX protection pending
5296 messages. Max credit available - 3.Write writes the initial credit value;
5297 read returns the current value of the credit counter. Must be initialized
5298 to 2 at start-up. */
5299#define XCM_REG_XX_INIT_CRD 0x20424
5300/* [RW 6] The maximum number of pending messages; which may be stored in XX
5301 protection. ~xcm_registers_xx_free.xx_free read on read. */
5302#define XCM_REG_XX_MSG_NUM 0x20428
5303/* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
5304#define XCM_REG_XX_OVFL_EVNT_ID 0x20058
5305#define XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS (0x1<<0)
5306#define XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS (0x1<<1)
5307#define XMAC_CTRL_REG_CORE_LOCAL_LPBK (0x1<<3)
5308#define XMAC_CTRL_REG_RX_EN (0x1<<1)
5309#define XMAC_CTRL_REG_SOFT_RESET (0x1<<6)
5310#define XMAC_CTRL_REG_TX_EN (0x1<<0)
5311#define XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN (0x1<<18)
5312#define XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN (0x1<<17)
5313#define XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN (0x1<<0)
5314#define XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN (0x1<<3)
5315#define XMAC_PFC_CTRL_HI_REG_RX_PFC_EN (0x1<<4)
5316#define XMAC_PFC_CTRL_HI_REG_TX_PFC_EN (0x1<<5)
5317#define XMAC_REG_CLEAR_RX_LSS_STATUS 0x60
5318#define XMAC_REG_CTRL 0
5319/* [RW 16] Upper 48 bits of ctrl_sa register. Used as the SA in PAUSE/PFC
5320 * packets transmitted by the MAC */
5321#define XMAC_REG_CTRL_SA_HI 0x2c
5322/* [RW 32] Lower 48 bits of ctrl_sa register. Used as the SA in PAUSE/PFC
5323 * packets transmitted by the MAC */
5324#define XMAC_REG_CTRL_SA_LO 0x28
5325#define XMAC_REG_PAUSE_CTRL 0x68
5326#define XMAC_REG_PFC_CTRL 0x70
5327#define XMAC_REG_PFC_CTRL_HI 0x74
5328#define XMAC_REG_RX_LSS_STATUS 0x58
5329/* [RW 14] Maximum packet size in receive direction; exclusive of preamble &
5330 * CRC in strip mode */
5331#define XMAC_REG_RX_MAX_SIZE 0x40
5332#define XMAC_REG_TX_CTRL 0x20
5333/* [RW 16] Indirect access to the XX table of the XX protection mechanism.
5334 The fields are:[4:0] - tail pointer; 9:5] - Link List size; 14:10] -
5335 header pointer. */
5336#define XCM_REG_XX_TABLE 0x20500
5337/* [RW 8] The event id for aggregated interrupt 0 */
5338#define XSDM_REG_AGG_INT_EVENT_0 0x166038
5339#define XSDM_REG_AGG_INT_EVENT_1 0x16603c
5340#define XSDM_REG_AGG_INT_EVENT_10 0x166060
5341#define XSDM_REG_AGG_INT_EVENT_11 0x166064
5342#define XSDM_REG_AGG_INT_EVENT_12 0x166068
5343#define XSDM_REG_AGG_INT_EVENT_13 0x16606c
5344#define XSDM_REG_AGG_INT_EVENT_14 0x166070
5345#define XSDM_REG_AGG_INT_EVENT_2 0x166040
5346#define XSDM_REG_AGG_INT_EVENT_3 0x166044
5347#define XSDM_REG_AGG_INT_EVENT_4 0x166048
5348#define XSDM_REG_AGG_INT_EVENT_5 0x16604c
5349#define XSDM_REG_AGG_INT_EVENT_6 0x166050
5350#define XSDM_REG_AGG_INT_EVENT_7 0x166054
5351#define XSDM_REG_AGG_INT_EVENT_8 0x166058
5352#define XSDM_REG_AGG_INT_EVENT_9 0x16605c
5353/* [RW 1] For each aggregated interrupt index whether the mode is normal (0)
5354 or auto-mask-mode (1) */
5355#define XSDM_REG_AGG_INT_MODE_0 0x1661b8
5356#define XSDM_REG_AGG_INT_MODE_1 0x1661bc
5357/* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
5358#define XSDM_REG_CFC_RSP_START_ADDR 0x166008
5359/* [RW 16] The maximum value of the completion counter #0 */
5360#define XSDM_REG_CMP_COUNTER_MAX0 0x16601c
5361/* [RW 16] The maximum value of the completion counter #1 */
5362#define XSDM_REG_CMP_COUNTER_MAX1 0x166020
5363/* [RW 16] The maximum value of the completion counter #2 */
5364#define XSDM_REG_CMP_COUNTER_MAX2 0x166024
5365/* [RW 16] The maximum value of the completion counter #3 */
5366#define XSDM_REG_CMP_COUNTER_MAX3 0x166028
5367/* [RW 13] The start address in the internal RAM for the completion
5368 counters. */
5369#define XSDM_REG_CMP_COUNTER_START_ADDR 0x16600c
5370#define XSDM_REG_ENABLE_IN1 0x166238
5371#define XSDM_REG_ENABLE_IN2 0x16623c
5372#define XSDM_REG_ENABLE_OUT1 0x166240
5373#define XSDM_REG_ENABLE_OUT2 0x166244
5374/* [RW 4] The initial number of messages that can be sent to the pxp control
5375 interface without receiving any ACK. */
5376#define XSDM_REG_INIT_CREDIT_PXP_CTRL 0x1664bc
5377/* [ST 32] The number of ACK after placement messages received */
5378#define XSDM_REG_NUM_OF_ACK_AFTER_PLACE 0x16627c
5379/* [ST 32] The number of packet end messages received from the parser */
5380#define XSDM_REG_NUM_OF_PKT_END_MSG 0x166274
5381/* [ST 32] The number of requests received from the pxp async if */
5382#define XSDM_REG_NUM_OF_PXP_ASYNC_REQ 0x166278
5383/* [ST 32] The number of commands received in queue 0 */
5384#define XSDM_REG_NUM_OF_Q0_CMD 0x166248
5385/* [ST 32] The number of commands received in queue 10 */
5386#define XSDM_REG_NUM_OF_Q10_CMD 0x16626c
5387/* [ST 32] The number of commands received in queue 11 */
5388#define XSDM_REG_NUM_OF_Q11_CMD 0x166270
5389/* [ST 32] The number of commands received in queue 1 */
5390#define XSDM_REG_NUM_OF_Q1_CMD 0x16624c
5391/* [ST 32] The number of commands received in queue 3 */
5392#define XSDM_REG_NUM_OF_Q3_CMD 0x166250
5393/* [ST 32] The number of commands received in queue 4 */
5394#define XSDM_REG_NUM_OF_Q4_CMD 0x166254
5395/* [ST 32] The number of commands received in queue 5 */
5396#define XSDM_REG_NUM_OF_Q5_CMD 0x166258
5397/* [ST 32] The number of commands received in queue 6 */
5398#define XSDM_REG_NUM_OF_Q6_CMD 0x16625c
5399/* [ST 32] The number of commands received in queue 7 */
5400#define XSDM_REG_NUM_OF_Q7_CMD 0x166260
5401/* [ST 32] The number of commands received in queue 8 */
5402#define XSDM_REG_NUM_OF_Q8_CMD 0x166264
5403/* [ST 32] The number of commands received in queue 9 */
5404#define XSDM_REG_NUM_OF_Q9_CMD 0x166268
5405/* [RW 13] The start address in the internal RAM for queue counters */
5406#define XSDM_REG_Q_COUNTER_START_ADDR 0x166010
5407/* [W 17] Generate an operation after completion; bit-16 is
5408 * AggVectIdx_valid; bits 15:8 are AggVectIdx; bits 7:5 are the TRIG and
5409 * bits 4:0 are the T124Param[4:0] */
5410#define XSDM_REG_OPERATION_GEN 0x1664c4
5411/* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
5412#define XSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0x166548
5413/* [R 1] parser fifo empty in sdm_sync block */
5414#define XSDM_REG_SYNC_PARSER_EMPTY 0x166550
5415/* [R 1] parser serial fifo empty in sdm_sync block */
5416#define XSDM_REG_SYNC_SYNC_EMPTY 0x166558
5417/* [RW 32] Tick for timer counter. Applicable only when
5418 ~xsdm_registers_timer_tick_enable.timer_tick_enable =1 */
5419#define XSDM_REG_TIMER_TICK 0x166000
5420/* [RW 32] Interrupt mask register #0 read/write */
5421#define XSDM_REG_XSDM_INT_MASK_0 0x16629c
5422#define XSDM_REG_XSDM_INT_MASK_1 0x1662ac
5423/* [R 32] Interrupt register #0 read */
5424#define XSDM_REG_XSDM_INT_STS_0 0x166290
5425#define XSDM_REG_XSDM_INT_STS_1 0x1662a0
5426/* [RW 11] Parity mask register #0 read/write */
5427#define XSDM_REG_XSDM_PRTY_MASK 0x1662bc
5428/* [R 11] Parity register #0 read */
5429#define XSDM_REG_XSDM_PRTY_STS 0x1662b0
5430/* [RC 11] Parity register #0 read clear */
5431#define XSDM_REG_XSDM_PRTY_STS_CLR 0x1662b4
5432/* [RW 5] The number of time_slots in the arbitration cycle */
5433#define XSEM_REG_ARB_CYCLE_SIZE 0x280034
5434/* [RW 3] The source that is associated with arbitration element 0. Source
5435 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
5436 sleeping thread with priority 1; 4- sleeping thread with priority 2 */
5437#define XSEM_REG_ARB_ELEMENT0 0x280020
5438/* [RW 3] The source that is associated with arbitration element 1. Source
5439 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
5440 sleeping thread with priority 1; 4- sleeping thread with priority 2.
5441 Could not be equal to register ~xsem_registers_arb_element0.arb_element0 */
5442#define XSEM_REG_ARB_ELEMENT1 0x280024
5443/* [RW 3] The source that is associated with arbitration element 2. Source
5444 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
5445 sleeping thread with priority 1; 4- sleeping thread with priority 2.
5446 Could not be equal to register ~xsem_registers_arb_element0.arb_element0
5447 and ~xsem_registers_arb_element1.arb_element1 */
5448#define XSEM_REG_ARB_ELEMENT2 0x280028
5449/* [RW 3] The source that is associated with arbitration element 3. Source
5450 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
5451 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could
5452 not be equal to register ~xsem_registers_arb_element0.arb_element0 and
5453 ~xsem_registers_arb_element1.arb_element1 and
5454 ~xsem_registers_arb_element2.arb_element2 */
5455#define XSEM_REG_ARB_ELEMENT3 0x28002c
5456/* [RW 3] The source that is associated with arbitration element 4. Source
5457 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
5458 sleeping thread with priority 1; 4- sleeping thread with priority 2.
5459 Could not be equal to register ~xsem_registers_arb_element0.arb_element0
5460 and ~xsem_registers_arb_element1.arb_element1 and
5461 ~xsem_registers_arb_element2.arb_element2 and
5462 ~xsem_registers_arb_element3.arb_element3 */
5463#define XSEM_REG_ARB_ELEMENT4 0x280030
5464#define XSEM_REG_ENABLE_IN 0x2800a4
5465#define XSEM_REG_ENABLE_OUT 0x2800a8
5466/* [RW 32] This address space contains all registers and memories that are
5467 placed in SEM_FAST block. The SEM_FAST registers are described in
5468 appendix B. In order to access the sem_fast registers the base address
5469 ~fast_memory.fast_memory should be added to eachsem_fast register offset. */
5470#define XSEM_REG_FAST_MEMORY 0x2a0000
5471/* [RW 1] Disables input messages from FIC0 May be updated during run_time
5472 by the microcode */
5473#define XSEM_REG_FIC0_DISABLE 0x280224
5474/* [RW 1] Disables input messages from FIC1 May be updated during run_time
5475 by the microcode */
5476#define XSEM_REG_FIC1_DISABLE 0x280234
5477/* [RW 15] Interrupt table Read and write access to it is not possible in
5478 the middle of the work */
5479#define XSEM_REG_INT_TABLE 0x280400
5480/* [ST 24] Statistics register. The number of messages that entered through
5481 FIC0 */
5482#define XSEM_REG_MSG_NUM_FIC0 0x280000
5483/* [ST 24] Statistics register. The number of messages that entered through
5484 FIC1 */
5485#define XSEM_REG_MSG_NUM_FIC1 0x280004
5486/* [ST 24] Statistics register. The number of messages that were sent to
5487 FOC0 */
5488#define XSEM_REG_MSG_NUM_FOC0 0x280008
5489/* [ST 24] Statistics register. The number of messages that were sent to
5490 FOC1 */
5491#define XSEM_REG_MSG_NUM_FOC1 0x28000c
5492/* [ST 24] Statistics register. The number of messages that were sent to
5493 FOC2 */
5494#define XSEM_REG_MSG_NUM_FOC2 0x280010
5495/* [ST 24] Statistics register. The number of messages that were sent to
5496 FOC3 */
5497#define XSEM_REG_MSG_NUM_FOC3 0x280014
5498/* [RW 1] Disables input messages from the passive buffer May be updated
5499 during run_time by the microcode */
5500#define XSEM_REG_PAS_DISABLE 0x28024c
5501/* [WB 128] Debug only. Passive buffer memory */
5502#define XSEM_REG_PASSIVE_BUFFER 0x282000
5503/* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
5504#define XSEM_REG_PRAM 0x2c0000
5505/* [R 16] Valid sleeping threads indication have bit per thread */
5506#define XSEM_REG_SLEEP_THREADS_VALID 0x28026c
5507/* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
5508#define XSEM_REG_SLOW_EXT_STORE_EMPTY 0x2802a0
5509/* [RW 16] List of free threads . There is a bit per thread. */
5510#define XSEM_REG_THREADS_LIST 0x2802e4
5511/* [RW 3] The arbitration scheme of time_slot 0 */
5512#define XSEM_REG_TS_0_AS 0x280038
5513/* [RW 3] The arbitration scheme of time_slot 10 */
5514#define XSEM_REG_TS_10_AS 0x280060
5515/* [RW 3] The arbitration scheme of time_slot 11 */
5516#define XSEM_REG_TS_11_AS 0x280064
5517/* [RW 3] The arbitration scheme of time_slot 12 */
5518#define XSEM_REG_TS_12_AS 0x280068
5519/* [RW 3] The arbitration scheme of time_slot 13 */
5520#define XSEM_REG_TS_13_AS 0x28006c
5521/* [RW 3] The arbitration scheme of time_slot 14 */
5522#define XSEM_REG_TS_14_AS 0x280070
5523/* [RW 3] The arbitration scheme of time_slot 15 */
5524#define XSEM_REG_TS_15_AS 0x280074
5525/* [RW 3] The arbitration scheme of time_slot 16 */
5526#define XSEM_REG_TS_16_AS 0x280078
5527/* [RW 3] The arbitration scheme of time_slot 17 */
5528#define XSEM_REG_TS_17_AS 0x28007c
5529/* [RW 3] The arbitration scheme of time_slot 18 */
5530#define XSEM_REG_TS_18_AS 0x280080
5531/* [RW 3] The arbitration scheme of time_slot 1 */
5532#define XSEM_REG_TS_1_AS 0x28003c
5533/* [RW 3] The arbitration scheme of time_slot 2 */
5534#define XSEM_REG_TS_2_AS 0x280040
5535/* [RW 3] The arbitration scheme of time_slot 3 */
5536#define XSEM_REG_TS_3_AS 0x280044
5537/* [RW 3] The arbitration scheme of time_slot 4 */
5538#define XSEM_REG_TS_4_AS 0x280048
5539/* [RW 3] The arbitration scheme of time_slot 5 */
5540#define XSEM_REG_TS_5_AS 0x28004c
5541/* [RW 3] The arbitration scheme of time_slot 6 */
5542#define XSEM_REG_TS_6_AS 0x280050
5543/* [RW 3] The arbitration scheme of time_slot 7 */
5544#define XSEM_REG_TS_7_AS 0x280054
5545/* [RW 3] The arbitration scheme of time_slot 8 */
5546#define XSEM_REG_TS_8_AS 0x280058
5547/* [RW 3] The arbitration scheme of time_slot 9 */
5548#define XSEM_REG_TS_9_AS 0x28005c
5549/* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 64
5550 * VF; values 64-67 reset error for 4 PF; values 68-127 are not valid. */
5551#define XSEM_REG_VFPF_ERR_NUM 0x280380
5552/* [RW 32] Interrupt mask register #0 read/write */
5553#define XSEM_REG_XSEM_INT_MASK_0 0x280110
5554#define XSEM_REG_XSEM_INT_MASK_1 0x280120
5555/* [R 32] Interrupt register #0 read */
5556#define XSEM_REG_XSEM_INT_STS_0 0x280104
5557#define XSEM_REG_XSEM_INT_STS_1 0x280114
5558/* [RW 32] Parity mask register #0 read/write */
5559#define XSEM_REG_XSEM_PRTY_MASK_0 0x280130
5560#define XSEM_REG_XSEM_PRTY_MASK_1 0x280140
5561/* [R 32] Parity register #0 read */
5562#define XSEM_REG_XSEM_PRTY_STS_0 0x280124
5563#define XSEM_REG_XSEM_PRTY_STS_1 0x280134
5564/* [RC 32] Parity register #0 read clear */
5565#define XSEM_REG_XSEM_PRTY_STS_CLR_0 0x280128
5566#define XSEM_REG_XSEM_PRTY_STS_CLR_1 0x280138
5567#define MCPR_NVM_ACCESS_ENABLE_EN (1L<<0)
5568#define MCPR_NVM_ACCESS_ENABLE_WR_EN (1L<<1)
5569#define MCPR_NVM_ADDR_NVM_ADDR_VALUE (0xffffffL<<0)
5570#define MCPR_NVM_CFG4_FLASH_SIZE (0x7L<<0)
5571#define MCPR_NVM_COMMAND_DOIT (1L<<4)
5572#define MCPR_NVM_COMMAND_DONE (1L<<3)
5573#define MCPR_NVM_COMMAND_FIRST (1L<<7)
5574#define MCPR_NVM_COMMAND_LAST (1L<<8)
5575#define MCPR_NVM_COMMAND_WR (1L<<5)
5576#define MCPR_NVM_SW_ARB_ARB_ARB1 (1L<<9)
5577#define MCPR_NVM_SW_ARB_ARB_REQ_CLR1 (1L<<5)
5578#define MCPR_NVM_SW_ARB_ARB_REQ_SET1 (1L<<1)
5579#define BIGMAC_REGISTER_BMAC_CONTROL (0x00<<3)
5580#define BIGMAC_REGISTER_BMAC_XGXS_CONTROL (0x01<<3)
5581#define BIGMAC_REGISTER_CNT_MAX_SIZE (0x05<<3)
5582#define BIGMAC_REGISTER_RX_CONTROL (0x21<<3)
5583#define BIGMAC_REGISTER_RX_LLFC_MSG_FLDS (0x46<<3)
5584#define BIGMAC_REGISTER_RX_LSS_STATUS (0x43<<3)
5585#define BIGMAC_REGISTER_RX_MAX_SIZE (0x23<<3)
5586#define BIGMAC_REGISTER_RX_STAT_GR64 (0x26<<3)
5587#define BIGMAC_REGISTER_RX_STAT_GRIPJ (0x42<<3)
5588#define BIGMAC_REGISTER_TX_CONTROL (0x07<<3)
5589#define BIGMAC_REGISTER_TX_MAX_SIZE (0x09<<3)
5590#define BIGMAC_REGISTER_TX_PAUSE_THRESHOLD (0x0A<<3)
5591#define BIGMAC_REGISTER_TX_SOURCE_ADDR (0x08<<3)
5592#define BIGMAC_REGISTER_TX_STAT_GTBYT (0x20<<3)
5593#define BIGMAC_REGISTER_TX_STAT_GTPKT (0x0C<<3)
5594#define BIGMAC2_REGISTER_BMAC_CONTROL (0x00<<3)
5595#define BIGMAC2_REGISTER_BMAC_XGXS_CONTROL (0x01<<3)
5596#define BIGMAC2_REGISTER_CNT_MAX_SIZE (0x05<<3)
5597#define BIGMAC2_REGISTER_PFC_CONTROL (0x06<<3)
5598#define BIGMAC2_REGISTER_RX_CONTROL (0x3A<<3)
5599#define BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS (0x62<<3)
5600#define BIGMAC2_REGISTER_RX_LSS_STAT (0x3E<<3)
5601#define BIGMAC2_REGISTER_RX_MAX_SIZE (0x3C<<3)
5602#define BIGMAC2_REGISTER_RX_STAT_GR64 (0x40<<3)
5603#define BIGMAC2_REGISTER_RX_STAT_GRIPJ (0x5f<<3)
5604#define BIGMAC2_REGISTER_RX_STAT_GRPP (0x51<<3)
5605#define BIGMAC2_REGISTER_TX_CONTROL (0x1C<<3)
5606#define BIGMAC2_REGISTER_TX_MAX_SIZE (0x1E<<3)
5607#define BIGMAC2_REGISTER_TX_PAUSE_CONTROL (0x20<<3)
5608#define BIGMAC2_REGISTER_TX_SOURCE_ADDR (0x1D<<3)
5609#define BIGMAC2_REGISTER_TX_STAT_GTBYT (0x39<<3)
5610#define BIGMAC2_REGISTER_TX_STAT_GTPOK (0x22<<3)
5611#define BIGMAC2_REGISTER_TX_STAT_GTPP (0x24<<3)
5612#define EMAC_LED_1000MB_OVERRIDE (1L<<1)
5613#define EMAC_LED_100MB_OVERRIDE (1L<<2)
5614#define EMAC_LED_10MB_OVERRIDE (1L<<3)
5615#define EMAC_LED_2500MB_OVERRIDE (1L<<12)
5616#define EMAC_LED_OVERRIDE (1L<<0)
5617#define EMAC_LED_TRAFFIC (1L<<6)
5618#define EMAC_MDIO_COMM_COMMAND_ADDRESS (0L<<26)
5619#define EMAC_MDIO_COMM_COMMAND_READ_22 (2L<<26)
5620#define EMAC_MDIO_COMM_COMMAND_READ_45 (3L<<26)
5621#define EMAC_MDIO_COMM_COMMAND_WRITE_22 (1L<<26)
5622#define EMAC_MDIO_COMM_COMMAND_WRITE_45 (1L<<26)
5623#define EMAC_MDIO_COMM_DATA (0xffffL<<0)
5624#define EMAC_MDIO_COMM_START_BUSY (1L<<29)
5625#define EMAC_MDIO_MODE_AUTO_POLL (1L<<4)
5626#define EMAC_MDIO_MODE_CLAUSE_45 (1L<<31)
5627#define EMAC_MDIO_MODE_CLOCK_CNT (0x3ffL<<16)
5628#define EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT 16
5629#define EMAC_MDIO_STATUS_10MB (1L<<1)
5630#define EMAC_MODE_25G_MODE (1L<<5)
5631#define EMAC_MODE_HALF_DUPLEX (1L<<1)
5632#define EMAC_MODE_PORT_GMII (2L<<2)
5633#define EMAC_MODE_PORT_MII (1L<<2)
5634#define EMAC_MODE_PORT_MII_10M (3L<<2)
5635#define EMAC_MODE_RESET (1L<<0)
5636#define EMAC_REG_EMAC_LED 0xc
5637#define EMAC_REG_EMAC_MAC_MATCH 0x10
5638#define EMAC_REG_EMAC_MDIO_COMM 0xac
5639#define EMAC_REG_EMAC_MDIO_MODE 0xb4
5640#define EMAC_REG_EMAC_MDIO_STATUS 0xb0
5641#define EMAC_REG_EMAC_MODE 0x0
5642#define EMAC_REG_EMAC_RX_MODE 0xc8
5643#define EMAC_REG_EMAC_RX_MTU_SIZE 0x9c
5644#define EMAC_REG_EMAC_RX_STAT_AC 0x180
5645#define EMAC_REG_EMAC_RX_STAT_AC_28 0x1f4
5646#define EMAC_REG_EMAC_RX_STAT_AC_COUNT 23
5647#define EMAC_REG_EMAC_TX_MODE 0xbc
5648#define EMAC_REG_EMAC_TX_STAT_AC 0x280
5649#define EMAC_REG_EMAC_TX_STAT_AC_COUNT 22
5650#define EMAC_REG_RX_PFC_MODE 0x320
5651#define EMAC_REG_RX_PFC_MODE_PRIORITIES (1L<<2)
5652#define EMAC_REG_RX_PFC_MODE_RX_EN (1L<<1)
5653#define EMAC_REG_RX_PFC_MODE_TX_EN (1L<<0)
5654#define EMAC_REG_RX_PFC_PARAM 0x324
5655#define EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT 0
5656#define EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT 16
5657#define EMAC_REG_RX_PFC_STATS_XOFF_RCVD 0x328
5658#define EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT (0xffff<<0)
5659#define EMAC_REG_RX_PFC_STATS_XOFF_SENT 0x330
5660#define EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT (0xffff<<0)
5661#define EMAC_REG_RX_PFC_STATS_XON_RCVD 0x32c
5662#define EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT (0xffff<<0)
5663#define EMAC_REG_RX_PFC_STATS_XON_SENT 0x334
5664#define EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT (0xffff<<0)
5665#define EMAC_RX_MODE_FLOW_EN (1L<<2)
5666#define EMAC_RX_MODE_KEEP_MAC_CONTROL (1L<<3)
5667#define EMAC_RX_MODE_KEEP_VLAN_TAG (1L<<10)
5668#define EMAC_RX_MODE_PROMISCUOUS (1L<<8)
5669#define EMAC_RX_MODE_RESET (1L<<0)
5670#define EMAC_RX_MTU_SIZE_JUMBO_ENA (1L<<31)
5671#define EMAC_TX_MODE_EXT_PAUSE_EN (1L<<3)
5672#define EMAC_TX_MODE_FLOW_EN (1L<<4)
5673#define EMAC_TX_MODE_RESET (1L<<0)
5674#define MISC_REGISTERS_GPIO_0 0
5675#define MISC_REGISTERS_GPIO_1 1
5676#define MISC_REGISTERS_GPIO_2 2
5677#define MISC_REGISTERS_GPIO_3 3
5678#define MISC_REGISTERS_GPIO_CLR_POS 16
5679#define MISC_REGISTERS_GPIO_FLOAT (0xffL<<24)
5680#define MISC_REGISTERS_GPIO_FLOAT_POS 24
5681#define MISC_REGISTERS_GPIO_HIGH 1
5682#define MISC_REGISTERS_GPIO_INPUT_HI_Z 2
5683#define MISC_REGISTERS_GPIO_INT_CLR_POS 24
5684#define MISC_REGISTERS_GPIO_INT_OUTPUT_CLR 0
5685#define MISC_REGISTERS_GPIO_INT_OUTPUT_SET 1
5686#define MISC_REGISTERS_GPIO_INT_SET_POS 16
5687#define MISC_REGISTERS_GPIO_LOW 0
5688#define MISC_REGISTERS_GPIO_OUTPUT_HIGH 1
5689#define MISC_REGISTERS_GPIO_OUTPUT_LOW 0
5690#define MISC_REGISTERS_GPIO_PORT_SHIFT 4
5691#define MISC_REGISTERS_GPIO_SET_POS 8
5692#define MISC_REGISTERS_RESET_REG_1_CLEAR 0x588
5693#define MISC_REGISTERS_RESET_REG_1_RST_HC (0x1<<29)
5694#define MISC_REGISTERS_RESET_REG_1_RST_NIG (0x1<<7)
5695#define MISC_REGISTERS_RESET_REG_1_RST_PXP (0x1<<26)
5696#define MISC_REGISTERS_RESET_REG_1_RST_PXPV (0x1<<27)
5697#define MISC_REGISTERS_RESET_REG_1_SET 0x584
5698#define MISC_REGISTERS_RESET_REG_2_CLEAR 0x598
5699#define MISC_REGISTERS_RESET_REG_2_MSTAT0 (0x1<<24)
5700#define MISC_REGISTERS_RESET_REG_2_MSTAT1 (0x1<<25)
5701#define MISC_REGISTERS_RESET_REG_2_PGLC (0x1<<19)
5702#define MISC_REGISTERS_RESET_REG_2_RST_ATC (0x1<<17)
5703#define MISC_REGISTERS_RESET_REG_2_RST_BMAC0 (0x1<<0)
5704#define MISC_REGISTERS_RESET_REG_2_RST_BMAC1 (0x1<<1)
5705#define MISC_REGISTERS_RESET_REG_2_RST_EMAC0 (0x1<<2)
5706#define MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE (0x1<<14)
5707#define MISC_REGISTERS_RESET_REG_2_RST_EMAC1 (0x1<<3)
5708#define MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE (0x1<<15)
5709#define MISC_REGISTERS_RESET_REG_2_RST_GRC (0x1<<4)
5710#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B (0x1<<6)
5711#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE (0x1<<8)
5712#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU (0x1<<7)
5713#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE (0x1<<5)
5714#define MISC_REGISTERS_RESET_REG_2_RST_MDIO (0x1<<13)
5715#define MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE (0x1<<11)
5716#define MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO (0x1<<13)
5717#define MISC_REGISTERS_RESET_REG_2_RST_RBCN (0x1<<9)
5718#define MISC_REGISTERS_RESET_REG_2_SET 0x594
5719#define MISC_REGISTERS_RESET_REG_2_UMAC0 (0x1<<20)
5720#define MISC_REGISTERS_RESET_REG_2_UMAC1 (0x1<<21)
5721#define MISC_REGISTERS_RESET_REG_2_XMAC (0x1<<22)
5722#define MISC_REGISTERS_RESET_REG_2_XMAC_SOFT (0x1<<23)
5723#define MISC_REGISTERS_RESET_REG_3_CLEAR 0x5a8
5724#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ (0x1<<1)
5725#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN (0x1<<2)
5726#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD (0x1<<3)
5727#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW (0x1<<0)
5728#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ (0x1<<5)
5729#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN (0x1<<6)
5730#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD (0x1<<7)
5731#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW (0x1<<4)
5732#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB (0x1<<8)
5733#define MISC_REGISTERS_RESET_REG_3_SET 0x5a4
5734#define MISC_REGISTERS_SPIO_4 4
5735#define MISC_REGISTERS_SPIO_5 5
5736#define MISC_REGISTERS_SPIO_7 7
5737#define MISC_REGISTERS_SPIO_CLR_POS 16
5738#define MISC_REGISTERS_SPIO_FLOAT (0xffL<<24)
5739#define MISC_REGISTERS_SPIO_FLOAT_POS 24
5740#define MISC_REGISTERS_SPIO_INPUT_HI_Z 2
5741#define MISC_REGISTERS_SPIO_INT_OLD_SET_POS 16
5742#define MISC_REGISTERS_SPIO_OUTPUT_HIGH 1
5743#define MISC_REGISTERS_SPIO_OUTPUT_LOW 0
5744#define MISC_REGISTERS_SPIO_SET_POS 8
5745#define HW_LOCK_DRV_FLAGS 10
5746#define HW_LOCK_MAX_RESOURCE_VALUE 31
5747#define HW_LOCK_RESOURCE_GPIO 1
5748#define HW_LOCK_RESOURCE_MDIO 0
5749#define HW_LOCK_RESOURCE_PORT0_ATT_MASK 3
5750#define HW_LOCK_RESOURCE_RECOVERY_LEADER_0 8
5751#define HW_LOCK_RESOURCE_RECOVERY_LEADER_1 9
5752#define HW_LOCK_RESOURCE_SPIO 2
5753#define HW_LOCK_RESOURCE_UNDI 5
5754#define AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT (0x1<<4)
5755#define AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR (0x1<<5)
5756#define AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR (0x1<<18)
5757#define AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT (0x1<<31)
5758#define AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR (0x1<<30)
5759#define AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT (0x1<<9)
5760#define AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR (0x1<<8)
5761#define AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT (0x1<<7)
5762#define AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR (0x1<<6)
5763#define AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT (0x1<<29)
5764#define AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR (0x1<<28)
5765#define AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT (0x1<<1)
5766#define AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR (0x1<<0)
5767#define AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR (0x1<<18)
5768#define AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT (0x1<<11)
5769#define AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR (0x1<<10)
5770#define AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT (0x1<<13)
5771#define AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR (0x1<<12)
5772#define AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 (0x1<<2)
5773#define AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR (0x1<<12)
5774#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY (0x1<<28)
5775#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY (0x1<<31)
5776#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY (0x1<<29)
5777#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY (0x1<<30)
5778#define AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT (0x1<<15)
5779#define AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR (0x1<<14)
5780#define AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR (0x1<<14)
5781#define AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR (0x1<<20)
5782#define AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT (0x1<<31)
5783#define AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR (0x1<<30)
5784#define AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR (0x1<<0)
5785#define AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT (0x1<<2)
5786#define AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR (0x1<<3)
5787#define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT (0x1<<5)
5788#define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR (0x1<<4)
5789#define AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT (0x1<<3)
5790#define AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR (0x1<<2)
5791#define AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT (0x1<<3)
5792#define AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR (0x1<<2)
5793#define AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR (0x1<<22)
5794#define AEU_INPUTS_ATTN_BITS_SPIO5 (0x1<<15)
5795#define AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT (0x1<<27)
5796#define AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR (0x1<<26)
5797#define AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT (0x1<<5)
5798#define AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR (0x1<<4)
5799#define AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT (0x1<<25)
5800#define AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR (0x1<<24)
5801#define AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT (0x1<<29)
5802#define AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR (0x1<<28)
5803#define AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT (0x1<<23)
5804#define AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR (0x1<<22)
5805#define AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT (0x1<<27)
5806#define AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR (0x1<<26)
5807#define AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT (0x1<<21)
5808#define AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR (0x1<<20)
5809#define AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT (0x1<<25)
5810#define AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR (0x1<<24)
5811#define AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR (0x1<<16)
5812#define AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT (0x1<<9)
5813#define AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR (0x1<<8)
5814#define AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT (0x1<<7)
5815#define AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR (0x1<<6)
5816#define AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT (0x1<<11)
5817#define AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR (0x1<<10)
5818
5819#define AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0 (0x1<<5)
5820#define AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1 (0x1<<9)
5821
5822#define RESERVED_GENERAL_ATTENTION_BIT_0 0
5823
5824#define EVEREST_GEN_ATTN_IN_USE_MASK 0x7ffe0
5825#define EVEREST_LATCHED_ATTN_IN_USE_MASK 0xffe00000
5826
5827#define RESERVED_GENERAL_ATTENTION_BIT_6 6
5828#define RESERVED_GENERAL_ATTENTION_BIT_7 7
5829#define RESERVED_GENERAL_ATTENTION_BIT_8 8
5830#define RESERVED_GENERAL_ATTENTION_BIT_9 9
5831#define RESERVED_GENERAL_ATTENTION_BIT_10 10
5832#define RESERVED_GENERAL_ATTENTION_BIT_11 11
5833#define RESERVED_GENERAL_ATTENTION_BIT_12 12
5834#define RESERVED_GENERAL_ATTENTION_BIT_13 13
5835#define RESERVED_GENERAL_ATTENTION_BIT_14 14
5836#define RESERVED_GENERAL_ATTENTION_BIT_15 15
5837#define RESERVED_GENERAL_ATTENTION_BIT_16 16
5838#define RESERVED_GENERAL_ATTENTION_BIT_17 17
5839#define RESERVED_GENERAL_ATTENTION_BIT_18 18
5840#define RESERVED_GENERAL_ATTENTION_BIT_19 19
5841#define RESERVED_GENERAL_ATTENTION_BIT_20 20
5842#define RESERVED_GENERAL_ATTENTION_BIT_21 21
5843
5844/* storm asserts attention bits */
5845#define TSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_7
5846#define USTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_8
5847#define CSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_9
5848#define XSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_10
5849
5850/* mcp error attention bit */
5851#define MCP_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_11
5852
5853/*E1H NIG status sync attention mapped to group 4-7*/
5854#define LINK_SYNC_ATTENTION_BIT_FUNC_0 RESERVED_GENERAL_ATTENTION_BIT_12
5855#define LINK_SYNC_ATTENTION_BIT_FUNC_1 RESERVED_GENERAL_ATTENTION_BIT_13
5856#define LINK_SYNC_ATTENTION_BIT_FUNC_2 RESERVED_GENERAL_ATTENTION_BIT_14
5857#define LINK_SYNC_ATTENTION_BIT_FUNC_3 RESERVED_GENERAL_ATTENTION_BIT_15
5858#define LINK_SYNC_ATTENTION_BIT_FUNC_4 RESERVED_GENERAL_ATTENTION_BIT_16
5859#define LINK_SYNC_ATTENTION_BIT_FUNC_5 RESERVED_GENERAL_ATTENTION_BIT_17
5860#define LINK_SYNC_ATTENTION_BIT_FUNC_6 RESERVED_GENERAL_ATTENTION_BIT_18
5861#define LINK_SYNC_ATTENTION_BIT_FUNC_7 RESERVED_GENERAL_ATTENTION_BIT_19
5862
5863
5864#define LATCHED_ATTN_RBCR 23
5865#define LATCHED_ATTN_RBCT 24
5866#define LATCHED_ATTN_RBCN 25
5867#define LATCHED_ATTN_RBCU 26
5868#define LATCHED_ATTN_RBCP 27
5869#define LATCHED_ATTN_TIMEOUT_GRC 28
5870#define LATCHED_ATTN_RSVD_GRC 29
5871#define LATCHED_ATTN_ROM_PARITY_MCP 30
5872#define LATCHED_ATTN_UM_RX_PARITY_MCP 31
5873#define LATCHED_ATTN_UM_TX_PARITY_MCP 32
5874#define LATCHED_ATTN_SCPAD_PARITY_MCP 33
5875
5876#define GENERAL_ATTEN_WORD(atten_name) ((94 + atten_name) / 32)
5877#define GENERAL_ATTEN_OFFSET(atten_name)\
5878 (1UL << ((94 + atten_name) % 32))
5879/*
5880 * This file defines GRC base address for every block.
5881 * This file is included by chipsim, asm microcode and cpp microcode.
5882 * These values are used in Design.xml on regBase attribute
5883 * Use the base with the generated offsets of specific registers.
5884 */
5885
5886#define GRCBASE_PXPCS 0x000000
5887#define GRCBASE_PCICONFIG 0x002000
5888#define GRCBASE_PCIREG 0x002400
5889#define GRCBASE_EMAC0 0x008000
5890#define GRCBASE_EMAC1 0x008400
5891#define GRCBASE_DBU 0x008800
5892#define GRCBASE_MISC 0x00A000
5893#define GRCBASE_DBG 0x00C000
5894#define GRCBASE_NIG 0x010000
5895#define GRCBASE_XCM 0x020000
5896#define GRCBASE_PRS 0x040000
5897#define GRCBASE_SRCH 0x040400
5898#define GRCBASE_TSDM 0x042000
5899#define GRCBASE_TCM 0x050000
5900#define GRCBASE_BRB1 0x060000
5901#define GRCBASE_MCP 0x080000
5902#define GRCBASE_UPB 0x0C1000
5903#define GRCBASE_CSDM 0x0C2000
5904#define GRCBASE_USDM 0x0C4000
5905#define GRCBASE_CCM 0x0D0000
5906#define GRCBASE_UCM 0x0E0000
5907#define GRCBASE_CDU 0x101000
5908#define GRCBASE_DMAE 0x102000
5909#define GRCBASE_PXP 0x103000
5910#define GRCBASE_CFC 0x104000
5911#define GRCBASE_HC 0x108000
5912#define GRCBASE_PXP2 0x120000
5913#define GRCBASE_PBF 0x140000
5914#define GRCBASE_UMAC0 0x160000
5915#define GRCBASE_UMAC1 0x160400
5916#define GRCBASE_XPB 0x161000
5917#define GRCBASE_MSTAT0 0x162000
5918#define GRCBASE_MSTAT1 0x162800
5919#define GRCBASE_XMAC0 0x163000
5920#define GRCBASE_XMAC1 0x163800
5921#define GRCBASE_TIMERS 0x164000
5922#define GRCBASE_XSDM 0x166000
5923#define GRCBASE_QM 0x168000
5924#define GRCBASE_DQ 0x170000
5925#define GRCBASE_TSEM 0x180000
5926#define GRCBASE_CSEM 0x200000
5927#define GRCBASE_XSEM 0x280000
5928#define GRCBASE_USEM 0x300000
5929#define GRCBASE_MISC_AEU GRCBASE_MISC
5930
5931
5932/* offset of configuration space in the pci core register */
5933#define PCICFG_OFFSET 0x2000
5934#define PCICFG_VENDOR_ID_OFFSET 0x00
5935#define PCICFG_DEVICE_ID_OFFSET 0x02
5936#define PCICFG_COMMAND_OFFSET 0x04
5937#define PCICFG_COMMAND_IO_SPACE (1<<0)
5938#define PCICFG_COMMAND_MEM_SPACE (1<<1)
5939#define PCICFG_COMMAND_BUS_MASTER (1<<2)
5940#define PCICFG_COMMAND_SPECIAL_CYCLES (1<<3)
5941#define PCICFG_COMMAND_MWI_CYCLES (1<<4)
5942#define PCICFG_COMMAND_VGA_SNOOP (1<<5)
5943#define PCICFG_COMMAND_PERR_ENA (1<<6)
5944#define PCICFG_COMMAND_STEPPING (1<<7)
5945#define PCICFG_COMMAND_SERR_ENA (1<<8)
5946#define PCICFG_COMMAND_FAST_B2B (1<<9)
5947#define PCICFG_COMMAND_INT_DISABLE (1<<10)
5948#define PCICFG_COMMAND_RESERVED (0x1f<<11)
5949#define PCICFG_STATUS_OFFSET 0x06
5950#define PCICFG_REVESION_ID_OFFSET 0x08
5951#define PCICFG_CACHE_LINE_SIZE 0x0c
5952#define PCICFG_LATENCY_TIMER 0x0d
5953#define PCICFG_BAR_1_LOW 0x10
5954#define PCICFG_BAR_1_HIGH 0x14
5955#define PCICFG_BAR_2_LOW 0x18
5956#define PCICFG_BAR_2_HIGH 0x1c
5957#define PCICFG_SUBSYSTEM_VENDOR_ID_OFFSET 0x2c
5958#define PCICFG_SUBSYSTEM_ID_OFFSET 0x2e
5959#define PCICFG_INT_LINE 0x3c
5960#define PCICFG_INT_PIN 0x3d
5961#define PCICFG_PM_CAPABILITY 0x48
5962#define PCICFG_PM_CAPABILITY_VERSION (0x3<<16)
5963#define PCICFG_PM_CAPABILITY_CLOCK (1<<19)
5964#define PCICFG_PM_CAPABILITY_RESERVED (1<<20)
5965#define PCICFG_PM_CAPABILITY_DSI (1<<21)
5966#define PCICFG_PM_CAPABILITY_AUX_CURRENT (0x7<<22)
5967#define PCICFG_PM_CAPABILITY_D1_SUPPORT (1<<25)
5968#define PCICFG_PM_CAPABILITY_D2_SUPPORT (1<<26)
5969#define PCICFG_PM_CAPABILITY_PME_IN_D0 (1<<27)
5970#define PCICFG_PM_CAPABILITY_PME_IN_D1 (1<<28)
5971#define PCICFG_PM_CAPABILITY_PME_IN_D2 (1<<29)
5972#define PCICFG_PM_CAPABILITY_PME_IN_D3_HOT (1<<30)
5973#define PCICFG_PM_CAPABILITY_PME_IN_D3_COLD (1<<31)
5974#define PCICFG_PM_CSR_OFFSET 0x4c
5975#define PCICFG_PM_CSR_STATE (0x3<<0)
5976#define PCICFG_PM_CSR_PME_ENABLE (1<<8)
5977#define PCICFG_PM_CSR_PME_STATUS (1<<15)
5978#define PCICFG_MSI_CAP_ID_OFFSET 0x58
5979#define PCICFG_MSI_CONTROL_ENABLE (0x1<<16)
5980#define PCICFG_MSI_CONTROL_MCAP (0x7<<17)
5981#define PCICFG_MSI_CONTROL_MENA (0x7<<20)
5982#define PCICFG_MSI_CONTROL_64_BIT_ADDR_CAP (0x1<<23)
5983#define PCICFG_MSI_CONTROL_MSI_PVMASK_CAPABLE (0x1<<24)
5984#define PCICFG_GRC_ADDRESS 0x78
5985#define PCICFG_GRC_DATA 0x80
5986#define PCICFG_MSIX_CAP_ID_OFFSET 0xa0
5987#define PCICFG_MSIX_CONTROL_TABLE_SIZE (0x7ff<<16)
5988#define PCICFG_MSIX_CONTROL_RESERVED (0x7<<27)
5989#define PCICFG_MSIX_CONTROL_FUNC_MASK (0x1<<30)
5990#define PCICFG_MSIX_CONTROL_MSIX_ENABLE (0x1<<31)
5991
5992#define PCICFG_DEVICE_CONTROL 0xb4
5993#define PCICFG_DEVICE_STATUS 0xb6
5994#define PCICFG_DEVICE_STATUS_CORR_ERR_DET (1<<0)
5995#define PCICFG_DEVICE_STATUS_NON_FATAL_ERR_DET (1<<1)
5996#define PCICFG_DEVICE_STATUS_FATAL_ERR_DET (1<<2)
5997#define PCICFG_DEVICE_STATUS_UNSUP_REQ_DET (1<<3)
5998#define PCICFG_DEVICE_STATUS_AUX_PWR_DET (1<<4)
5999#define PCICFG_DEVICE_STATUS_NO_PEND (1<<5)
6000#define PCICFG_LINK_CONTROL 0xbc
6001
6002
6003#define BAR_USTRORM_INTMEM 0x400000
6004#define BAR_CSTRORM_INTMEM 0x410000
6005#define BAR_XSTRORM_INTMEM 0x420000
6006#define BAR_TSTRORM_INTMEM 0x430000
6007
6008/* for accessing the IGU in case of status block ACK */
6009#define BAR_IGU_INTMEM 0x440000
6010
6011#define BAR_DOORBELL_OFFSET 0x800000
6012
6013#define BAR_ME_REGISTER 0x450000
6014
6015/* config_2 offset */
6016#define GRC_CONFIG_2_SIZE_REG 0x408
6017#define PCI_CONFIG_2_BAR1_SIZE (0xfL<<0)
6018#define PCI_CONFIG_2_BAR1_SIZE_DISABLED (0L<<0)
6019#define PCI_CONFIG_2_BAR1_SIZE_64K (1L<<0)
6020#define PCI_CONFIG_2_BAR1_SIZE_128K (2L<<0)
6021#define PCI_CONFIG_2_BAR1_SIZE_256K (3L<<0)
6022#define PCI_CONFIG_2_BAR1_SIZE_512K (4L<<0)
6023#define PCI_CONFIG_2_BAR1_SIZE_1M (5L<<0)
6024#define PCI_CONFIG_2_BAR1_SIZE_2M (6L<<0)
6025#define PCI_CONFIG_2_BAR1_SIZE_4M (7L<<0)
6026#define PCI_CONFIG_2_BAR1_SIZE_8M (8L<<0)
6027#define PCI_CONFIG_2_BAR1_SIZE_16M (9L<<0)
6028#define PCI_CONFIG_2_BAR1_SIZE_32M (10L<<0)
6029#define PCI_CONFIG_2_BAR1_SIZE_64M (11L<<0)
6030#define PCI_CONFIG_2_BAR1_SIZE_128M (12L<<0)
6031#define PCI_CONFIG_2_BAR1_SIZE_256M (13L<<0)
6032#define PCI_CONFIG_2_BAR1_SIZE_512M (14L<<0)
6033#define PCI_CONFIG_2_BAR1_SIZE_1G (15L<<0)
6034#define PCI_CONFIG_2_BAR1_64ENA (1L<<4)
6035#define PCI_CONFIG_2_EXP_ROM_RETRY (1L<<5)
6036#define PCI_CONFIG_2_CFG_CYCLE_RETRY (1L<<6)
6037#define PCI_CONFIG_2_FIRST_CFG_DONE (1L<<7)
6038#define PCI_CONFIG_2_EXP_ROM_SIZE (0xffL<<8)
6039#define PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED (0L<<8)
6040#define PCI_CONFIG_2_EXP_ROM_SIZE_2K (1L<<8)
6041#define PCI_CONFIG_2_EXP_ROM_SIZE_4K (2L<<8)
6042#define PCI_CONFIG_2_EXP_ROM_SIZE_8K (3L<<8)
6043#define PCI_CONFIG_2_EXP_ROM_SIZE_16K (4L<<8)
6044#define PCI_CONFIG_2_EXP_ROM_SIZE_32K (5L<<8)
6045#define PCI_CONFIG_2_EXP_ROM_SIZE_64K (6L<<8)
6046#define PCI_CONFIG_2_EXP_ROM_SIZE_128K (7L<<8)
6047#define PCI_CONFIG_2_EXP_ROM_SIZE_256K (8L<<8)
6048#define PCI_CONFIG_2_EXP_ROM_SIZE_512K (9L<<8)
6049#define PCI_CONFIG_2_EXP_ROM_SIZE_1M (10L<<8)
6050#define PCI_CONFIG_2_EXP_ROM_SIZE_2M (11L<<8)
6051#define PCI_CONFIG_2_EXP_ROM_SIZE_4M (12L<<8)
6052#define PCI_CONFIG_2_EXP_ROM_SIZE_8M (13L<<8)
6053#define PCI_CONFIG_2_EXP_ROM_SIZE_16M (14L<<8)
6054#define PCI_CONFIG_2_EXP_ROM_SIZE_32M (15L<<8)
6055#define PCI_CONFIG_2_BAR_PREFETCH (1L<<16)
6056#define PCI_CONFIG_2_RESERVED0 (0x7fffL<<17)
6057
6058/* config_3 offset */
6059#define GRC_CONFIG_3_SIZE_REG 0x40c
6060#define PCI_CONFIG_3_STICKY_BYTE (0xffL<<0)
6061#define PCI_CONFIG_3_FORCE_PME (1L<<24)
6062#define PCI_CONFIG_3_PME_STATUS (1L<<25)
6063#define PCI_CONFIG_3_PME_ENABLE (1L<<26)
6064#define PCI_CONFIG_3_PM_STATE (0x3L<<27)
6065#define PCI_CONFIG_3_VAUX_PRESET (1L<<30)
6066#define PCI_CONFIG_3_PCI_POWER (1L<<31)
6067
6068#define GRC_BAR2_CONFIG 0x4e0
6069#define PCI_CONFIG_2_BAR2_SIZE (0xfL<<0)
6070#define PCI_CONFIG_2_BAR2_SIZE_DISABLED (0L<<0)
6071#define PCI_CONFIG_2_BAR2_SIZE_64K (1L<<0)
6072#define PCI_CONFIG_2_BAR2_SIZE_128K (2L<<0)
6073#define PCI_CONFIG_2_BAR2_SIZE_256K (3L<<0)
6074#define PCI_CONFIG_2_BAR2_SIZE_512K (4L<<0)
6075#define PCI_CONFIG_2_BAR2_SIZE_1M (5L<<0)
6076#define PCI_CONFIG_2_BAR2_SIZE_2M (6L<<0)
6077#define PCI_CONFIG_2_BAR2_SIZE_4M (7L<<0)
6078#define PCI_CONFIG_2_BAR2_SIZE_8M (8L<<0)
6079#define PCI_CONFIG_2_BAR2_SIZE_16M (9L<<0)
6080#define PCI_CONFIG_2_BAR2_SIZE_32M (10L<<0)
6081#define PCI_CONFIG_2_BAR2_SIZE_64M (11L<<0)
6082#define PCI_CONFIG_2_BAR2_SIZE_128M (12L<<0)
6083#define PCI_CONFIG_2_BAR2_SIZE_256M (13L<<0)
6084#define PCI_CONFIG_2_BAR2_SIZE_512M (14L<<0)
6085#define PCI_CONFIG_2_BAR2_SIZE_1G (15L<<0)
6086#define PCI_CONFIG_2_BAR2_64ENA (1L<<4)
6087
6088#define PCI_PM_DATA_A 0x410
6089#define PCI_PM_DATA_B 0x414
6090#define PCI_ID_VAL1 0x434
6091#define PCI_ID_VAL2 0x438
6092
6093#define PXPCS_TL_CONTROL_5 0x814
6094#define PXPCS_TL_CONTROL_5_UNKNOWNTYPE_ERR_ATTN (1 << 29) /*WC*/
6095#define PXPCS_TL_CONTROL_5_BOUNDARY4K_ERR_ATTN (1 << 28) /*WC*/
6096#define PXPCS_TL_CONTROL_5_MRRS_ERR_ATTN (1 << 27) /*WC*/
6097#define PXPCS_TL_CONTROL_5_MPS_ERR_ATTN (1 << 26) /*WC*/
6098#define PXPCS_TL_CONTROL_5_TTX_BRIDGE_FORWARD_ERR (1 << 25) /*WC*/
6099#define PXPCS_TL_CONTROL_5_TTX_TXINTF_OVERFLOW (1 << 24) /*WC*/
6100#define PXPCS_TL_CONTROL_5_PHY_ERR_ATTN (1 << 23) /*RO*/
6101#define PXPCS_TL_CONTROL_5_DL_ERR_ATTN (1 << 22) /*RO*/
6102#define PXPCS_TL_CONTROL_5_TTX_ERR_NP_TAG_IN_USE (1 << 21) /*WC*/
6103#define PXPCS_TL_CONTROL_5_TRX_ERR_UNEXP_RTAG (1 << 20) /*WC*/
6104#define PXPCS_TL_CONTROL_5_PRI_SIG_TARGET_ABORT1 (1 << 19) /*WC*/
6105#define PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 (1 << 18) /*WC*/
6106#define PXPCS_TL_CONTROL_5_ERR_ECRC1 (1 << 17) /*WC*/
6107#define PXPCS_TL_CONTROL_5_ERR_MALF_TLP1 (1 << 16) /*WC*/
6108#define PXPCS_TL_CONTROL_5_ERR_RX_OFLOW1 (1 << 15) /*WC*/
6109#define PXPCS_TL_CONTROL_5_ERR_UNEXP_CPL1 (1 << 14) /*WC*/
6110#define PXPCS_TL_CONTROL_5_ERR_MASTER_ABRT1 (1 << 13) /*WC*/
6111#define PXPCS_TL_CONTROL_5_ERR_CPL_TIMEOUT1 (1 << 12) /*WC*/
6112#define PXPCS_TL_CONTROL_5_ERR_FC_PRTL1 (1 << 11) /*WC*/
6113#define PXPCS_TL_CONTROL_5_ERR_PSND_TLP1 (1 << 10) /*WC*/
6114#define PXPCS_TL_CONTROL_5_PRI_SIG_TARGET_ABORT (1 << 9) /*WC*/
6115#define PXPCS_TL_CONTROL_5_ERR_UNSPPORT (1 << 8) /*WC*/
6116#define PXPCS_TL_CONTROL_5_ERR_ECRC (1 << 7) /*WC*/
6117#define PXPCS_TL_CONTROL_5_ERR_MALF_TLP (1 << 6) /*WC*/
6118#define PXPCS_TL_CONTROL_5_ERR_RX_OFLOW (1 << 5) /*WC*/
6119#define PXPCS_TL_CONTROL_5_ERR_UNEXP_CPL (1 << 4) /*WC*/
6120#define PXPCS_TL_CONTROL_5_ERR_MASTER_ABRT (1 << 3) /*WC*/
6121#define PXPCS_TL_CONTROL_5_ERR_CPL_TIMEOUT (1 << 2) /*WC*/
6122#define PXPCS_TL_CONTROL_5_ERR_FC_PRTL (1 << 1) /*WC*/
6123#define PXPCS_TL_CONTROL_5_ERR_PSND_TLP (1 << 0) /*WC*/
6124
6125
6126#define PXPCS_TL_FUNC345_STAT 0x854
6127#define PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT4 (1 << 29) /* WC */
6128#define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4\
6129 (1 << 28) /* Unsupported Request Error Status in function4, if \
6130 set, generate pcie_err_attn output when this error is seen. WC */
6131#define PXPCS_TL_FUNC345_STAT_ERR_ECRC4\
6132 (1 << 27) /* ECRC Error TLP Status Status in function 4, if set, \
6133 generate pcie_err_attn output when this error is seen.. WC */
6134#define PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP4\
6135 (1 << 26) /* Malformed TLP Status Status in function 4, if set, \
6136 generate pcie_err_attn output when this error is seen.. WC */
6137#define PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW4\
6138 (1 << 25) /* Receiver Overflow Status Status in function 4, if \
6139 set, generate pcie_err_attn output when this error is seen.. WC \
6140 */
6141#define PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL4\
6142 (1 << 24) /* Unexpected Completion Status Status in function 4, \
6143 if set, generate pcie_err_attn output when this error is seen. WC \
6144 */
6145#define PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT4\
6146 (1 << 23) /* Receive UR Statusin function 4. If set, generate \
6147 pcie_err_attn output when this error is seen. WC */
6148#define PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT4\
6149 (1 << 22) /* Completer Timeout Status Status in function 4, if \
6150 set, generate pcie_err_attn output when this error is seen. WC */
6151#define PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL4\
6152 (1 << 21) /* Flow Control Protocol Error Status Status in \
6153 function 4, if set, generate pcie_err_attn output when this error \
6154 is seen. WC */
6155#define PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP4\
6156 (1 << 20) /* Poisoned Error Status Status in function 4, if set, \
6157 generate pcie_err_attn output when this error is seen.. WC */
6158#define PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT3 (1 << 19) /* WC */
6159#define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3\
6160 (1 << 18) /* Unsupported Request Error Status in function3, if \
6161 set, generate pcie_err_attn output when this error is seen. WC */
6162#define PXPCS_TL_FUNC345_STAT_ERR_ECRC3\
6163 (1 << 17) /* ECRC Error TLP Status Status in function 3, if set, \
6164 generate pcie_err_attn output when this error is seen.. WC */
6165#define PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP3\
6166 (1 << 16) /* Malformed TLP Status Status in function 3, if set, \
6167 generate pcie_err_attn output when this error is seen.. WC */
6168#define PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW3\
6169 (1 << 15) /* Receiver Overflow Status Status in function 3, if \
6170 set, generate pcie_err_attn output when this error is seen.. WC \
6171 */
6172#define PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL3\
6173 (1 << 14) /* Unexpected Completion Status Status in function 3, \
6174 if set, generate pcie_err_attn output when this error is seen. WC \
6175 */
6176#define PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT3\
6177 (1 << 13) /* Receive UR Statusin function 3. If set, generate \
6178 pcie_err_attn output when this error is seen. WC */
6179#define PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT3\
6180 (1 << 12) /* Completer Timeout Status Status in function 3, if \
6181 set, generate pcie_err_attn output when this error is seen. WC */
6182#define PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL3\
6183 (1 << 11) /* Flow Control Protocol Error Status Status in \
6184 function 3, if set, generate pcie_err_attn output when this error \
6185 is seen. WC */
6186#define PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP3\
6187 (1 << 10) /* Poisoned Error Status Status in function 3, if set, \
6188 generate pcie_err_attn output when this error is seen.. WC */
6189#define PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT2 (1 << 9) /* WC */
6190#define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2\
6191 (1 << 8) /* Unsupported Request Error Status for Function 2, if \
6192 set, generate pcie_err_attn output when this error is seen. WC */
6193#define PXPCS_TL_FUNC345_STAT_ERR_ECRC2\
6194 (1 << 7) /* ECRC Error TLP Status Status for Function 2, if set, \
6195 generate pcie_err_attn output when this error is seen.. WC */
6196#define PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP2\
6197 (1 << 6) /* Malformed TLP Status Status for Function 2, if set, \
6198 generate pcie_err_attn output when this error is seen.. WC */
6199#define PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW2\
6200 (1 << 5) /* Receiver Overflow Status Status for Function 2, if \
6201 set, generate pcie_err_attn output when this error is seen.. WC \
6202 */
6203#define PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL2\
6204 (1 << 4) /* Unexpected Completion Status Status for Function 2, \
6205 if set, generate pcie_err_attn output when this error is seen. WC \
6206 */
6207#define PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT2\
6208 (1 << 3) /* Receive UR Statusfor Function 2. If set, generate \
6209 pcie_err_attn output when this error is seen. WC */
6210#define PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT2\
6211 (1 << 2) /* Completer Timeout Status Status for Function 2, if \
6212 set, generate pcie_err_attn output when this error is seen. WC */
6213#define PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL2\
6214 (1 << 1) /* Flow Control Protocol Error Status Status for \
6215 Function 2, if set, generate pcie_err_attn output when this error \
6216 is seen. WC */
6217#define PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP2\
6218 (1 << 0) /* Poisoned Error Status Status for Function 2, if set, \
6219 generate pcie_err_attn output when this error is seen.. WC */
6220
6221
6222#define PXPCS_TL_FUNC678_STAT 0x85C
6223#define PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT7 (1 << 29) /* WC */
6224#define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7\
6225 (1 << 28) /* Unsupported Request Error Status in function7, if \
6226 set, generate pcie_err_attn output when this error is seen. WC */
6227#define PXPCS_TL_FUNC678_STAT_ERR_ECRC7\
6228 (1 << 27) /* ECRC Error TLP Status Status in function 7, if set, \
6229 generate pcie_err_attn output when this error is seen.. WC */
6230#define PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP7\
6231 (1 << 26) /* Malformed TLP Status Status in function 7, if set, \
6232 generate pcie_err_attn output when this error is seen.. WC */
6233#define PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW7\
6234 (1 << 25) /* Receiver Overflow Status Status in function 7, if \
6235 set, generate pcie_err_attn output when this error is seen.. WC \
6236 */
6237#define PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL7\
6238 (1 << 24) /* Unexpected Completion Status Status in function 7, \
6239 if set, generate pcie_err_attn output when this error is seen. WC \
6240 */
6241#define PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT7\
6242 (1 << 23) /* Receive UR Statusin function 7. If set, generate \
6243 pcie_err_attn output when this error is seen. WC */
6244#define PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT7\
6245 (1 << 22) /* Completer Timeout Status Status in function 7, if \
6246 set, generate pcie_err_attn output when this error is seen. WC */
6247#define PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL7\
6248 (1 << 21) /* Flow Control Protocol Error Status Status in \
6249 function 7, if set, generate pcie_err_attn output when this error \
6250 is seen. WC */
6251#define PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP7\
6252 (1 << 20) /* Poisoned Error Status Status in function 7, if set, \
6253 generate pcie_err_attn output when this error is seen.. WC */
6254#define PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT6 (1 << 19) /* WC */
6255#define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6\
6256 (1 << 18) /* Unsupported Request Error Status in function6, if \
6257 set, generate pcie_err_attn output when this error is seen. WC */
6258#define PXPCS_TL_FUNC678_STAT_ERR_ECRC6\
6259 (1 << 17) /* ECRC Error TLP Status Status in function 6, if set, \
6260 generate pcie_err_attn output when this error is seen.. WC */
6261#define PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP6\
6262 (1 << 16) /* Malformed TLP Status Status in function 6, if set, \
6263 generate pcie_err_attn output when this error is seen.. WC */
6264#define PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW6\
6265 (1 << 15) /* Receiver Overflow Status Status in function 6, if \
6266 set, generate pcie_err_attn output when this error is seen.. WC \
6267 */
6268#define PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL6\
6269 (1 << 14) /* Unexpected Completion Status Status in function 6, \
6270 if set, generate pcie_err_attn output when this error is seen. WC \
6271 */
6272#define PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT6\
6273 (1 << 13) /* Receive UR Statusin function 6. If set, generate \
6274 pcie_err_attn output when this error is seen. WC */
6275#define PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT6\
6276 (1 << 12) /* Completer Timeout Status Status in function 6, if \
6277 set, generate pcie_err_attn output when this error is seen. WC */
6278#define PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL6\
6279 (1 << 11) /* Flow Control Protocol Error Status Status in \
6280 function 6, if set, generate pcie_err_attn output when this error \
6281 is seen. WC */
6282#define PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP6\
6283 (1 << 10) /* Poisoned Error Status Status in function 6, if set, \
6284 generate pcie_err_attn output when this error is seen.. WC */
6285#define PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT5 (1 << 9) /* WC */
6286#define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5\
6287 (1 << 8) /* Unsupported Request Error Status for Function 5, if \
6288 set, generate pcie_err_attn output when this error is seen. WC */
6289#define PXPCS_TL_FUNC678_STAT_ERR_ECRC5\
6290 (1 << 7) /* ECRC Error TLP Status Status for Function 5, if set, \
6291 generate pcie_err_attn output when this error is seen.. WC */
6292#define PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP5\
6293 (1 << 6) /* Malformed TLP Status Status for Function 5, if set, \
6294 generate pcie_err_attn output when this error is seen.. WC */
6295#define PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW5\
6296 (1 << 5) /* Receiver Overflow Status Status for Function 5, if \
6297 set, generate pcie_err_attn output when this error is seen.. WC \
6298 */
6299#define PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL5\
6300 (1 << 4) /* Unexpected Completion Status Status for Function 5, \
6301 if set, generate pcie_err_attn output when this error is seen. WC \
6302 */
6303#define PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT5\
6304 (1 << 3) /* Receive UR Statusfor Function 5. If set, generate \
6305 pcie_err_attn output when this error is seen. WC */
6306#define PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT5\
6307 (1 << 2) /* Completer Timeout Status Status for Function 5, if \
6308 set, generate pcie_err_attn output when this error is seen. WC */
6309#define PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL5\
6310 (1 << 1) /* Flow Control Protocol Error Status Status for \
6311 Function 5, if set, generate pcie_err_attn output when this error \
6312 is seen. WC */
6313#define PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP5\
6314 (1 << 0) /* Poisoned Error Status Status for Function 5, if set, \
6315 generate pcie_err_attn output when this error is seen.. WC */
6316
6317
6318#define BAR_USTRORM_INTMEM 0x400000
6319#define BAR_CSTRORM_INTMEM 0x410000
6320#define BAR_XSTRORM_INTMEM 0x420000
6321#define BAR_TSTRORM_INTMEM 0x430000
6322
6323/* for accessing the IGU in case of status block ACK */
6324#define BAR_IGU_INTMEM 0x440000
6325
6326#define BAR_DOORBELL_OFFSET 0x800000
6327
6328#define BAR_ME_REGISTER 0x450000
6329#define ME_REG_PF_NUM_SHIFT 0
6330#define ME_REG_PF_NUM\
6331 (7L<<ME_REG_PF_NUM_SHIFT) /* Relative PF Num */
6332#define ME_REG_VF_VALID (1<<8)
6333#define ME_REG_VF_NUM_SHIFT 9
6334#define ME_REG_VF_NUM_MASK (0x3f<<ME_REG_VF_NUM_SHIFT)
6335#define ME_REG_VF_ERR (0x1<<3)
6336#define ME_REG_ABS_PF_NUM_SHIFT 16
6337#define ME_REG_ABS_PF_NUM\
6338 (7L<<ME_REG_ABS_PF_NUM_SHIFT) /* Absolute PF Num */
6339
6340
6341#define MDIO_REG_BANK_CL73_IEEEB0 0x0
6342#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL 0x0
6343#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN 0x0200
6344#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN 0x1000
6345#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_MAIN_RST 0x8000
6346
6347#define MDIO_REG_BANK_CL73_IEEEB1 0x10
6348#define MDIO_CL73_IEEEB1_AN_ADV1 0x00
6349#define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE 0x0400
6350#define MDIO_CL73_IEEEB1_AN_ADV1_ASYMMETRIC 0x0800
6351#define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH 0x0C00
6352#define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK 0x0C00
6353#define MDIO_CL73_IEEEB1_AN_ADV2 0x01
6354#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M 0x0000
6355#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX 0x0020
6356#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 0x0040
6357#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR 0x0080
6358#define MDIO_CL73_IEEEB1_AN_LP_ADV1 0x03
6359#define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE 0x0400
6360#define MDIO_CL73_IEEEB1_AN_LP_ADV1_ASYMMETRIC 0x0800
6361#define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_BOTH 0x0C00
6362#define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK 0x0C00
6363
6364#define MDIO_REG_BANK_RX0 0x80b0
6365#define MDIO_RX0_RX_STATUS 0x10
6366#define MDIO_RX0_RX_STATUS_SIGDET 0x8000
6367#define MDIO_RX0_RX_STATUS_RX_SEQ_DONE 0x1000
6368#define MDIO_RX0_RX_EQ_BOOST 0x1c
6369#define MDIO_RX0_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
6370#define MDIO_RX0_RX_EQ_BOOST_OFFSET_CTRL 0x10
6371
6372#define MDIO_REG_BANK_RX1 0x80c0
6373#define MDIO_RX1_RX_EQ_BOOST 0x1c
6374#define MDIO_RX1_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
6375#define MDIO_RX1_RX_EQ_BOOST_OFFSET_CTRL 0x10
6376
6377#define MDIO_REG_BANK_RX2 0x80d0
6378#define MDIO_RX2_RX_EQ_BOOST 0x1c
6379#define MDIO_RX2_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
6380#define MDIO_RX2_RX_EQ_BOOST_OFFSET_CTRL 0x10
6381
6382#define MDIO_REG_BANK_RX3 0x80e0
6383#define MDIO_RX3_RX_EQ_BOOST 0x1c
6384#define MDIO_RX3_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
6385#define MDIO_RX3_RX_EQ_BOOST_OFFSET_CTRL 0x10
6386
6387#define MDIO_REG_BANK_RX_ALL 0x80f0
6388#define MDIO_RX_ALL_RX_EQ_BOOST 0x1c
6389#define MDIO_RX_ALL_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
6390#define MDIO_RX_ALL_RX_EQ_BOOST_OFFSET_CTRL 0x10
6391
6392#define MDIO_REG_BANK_TX0 0x8060
6393#define MDIO_TX0_TX_DRIVER 0x17
6394#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
6395#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
6396#define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
6397#define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
6398#define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
6399#define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
6400#define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
6401#define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
6402#define MDIO_TX0_TX_DRIVER_ICBUF1T 1
6403
6404#define MDIO_REG_BANK_TX1 0x8070
6405#define MDIO_TX1_TX_DRIVER 0x17
6406#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
6407#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
6408#define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
6409#define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
6410#define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
6411#define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
6412#define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
6413#define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
6414#define MDIO_TX0_TX_DRIVER_ICBUF1T 1
6415
6416#define MDIO_REG_BANK_TX2 0x8080
6417#define MDIO_TX2_TX_DRIVER 0x17
6418#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
6419#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
6420#define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
6421#define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
6422#define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
6423#define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
6424#define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
6425#define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
6426#define MDIO_TX0_TX_DRIVER_ICBUF1T 1
6427
6428#define MDIO_REG_BANK_TX3 0x8090
6429#define MDIO_TX3_TX_DRIVER 0x17
6430#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
6431#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
6432#define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
6433#define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
6434#define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
6435#define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
6436#define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
6437#define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
6438#define MDIO_TX0_TX_DRIVER_ICBUF1T 1
6439
6440#define MDIO_REG_BANK_XGXS_BLOCK0 0x8000
6441#define MDIO_BLOCK0_XGXS_CONTROL 0x10
6442
6443#define MDIO_REG_BANK_XGXS_BLOCK1 0x8010
6444#define MDIO_BLOCK1_LANE_CTRL0 0x15
6445#define MDIO_BLOCK1_LANE_CTRL1 0x16
6446#define MDIO_BLOCK1_LANE_CTRL2 0x17
6447#define MDIO_BLOCK1_LANE_PRBS 0x19
6448
6449#define MDIO_REG_BANK_XGXS_BLOCK2 0x8100
6450#define MDIO_XGXS_BLOCK2_RX_LN_SWAP 0x10
6451#define MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE 0x8000
6452#define MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE 0x4000
6453#define MDIO_XGXS_BLOCK2_TX_LN_SWAP 0x11
6454#define MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE 0x8000
6455#define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G 0x14
6456#define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS 0x0001
6457#define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS 0x0010
6458#define MDIO_XGXS_BLOCK2_TEST_MODE_LANE 0x15
6459
6460#define MDIO_REG_BANK_GP_STATUS 0x8120
6461#define MDIO_GP_STATUS_TOP_AN_STATUS1 0x1B
6462#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE 0x0001
6463#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE 0x0002
6464#define MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS 0x0004
6465#define MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS 0x0008
6466#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE 0x0010
6467#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_LP_NP_BAM_ABLE 0x0020
6468#define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE 0x0040
6469#define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE 0x0080
6470#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK 0x3f00
6471#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M 0x0000
6472#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M 0x0100
6473#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G 0x0200
6474#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G 0x0300
6475#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G 0x0400
6476#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G 0x0500
6477#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG 0x0600
6478#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4 0x0700
6479#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG 0x0800
6480#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G 0x0900
6481#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G 0x0A00
6482#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G 0x0B00
6483#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G 0x0C00
6484#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX 0x0D00
6485#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4 0x0E00
6486#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR 0x0F00
6487#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI 0x1B00
6488#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS 0x1E00
6489#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI 0x1F00
6490
6491
6492#define MDIO_REG_BANK_10G_PARALLEL_DETECT 0x8130
6493#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS 0x10
6494#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK 0x8000
6495#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL 0x11
6496#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN 0x1
6497#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK 0x13
6498#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT (0xb71<<1)
6499
6500#define MDIO_REG_BANK_SERDES_DIGITAL 0x8300
6501#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1 0x10
6502#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE 0x0001
6503#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_TBI_IF 0x0002
6504#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN 0x0004
6505#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT 0x0008
6506#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET 0x0010
6507#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE 0x0020
6508#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2 0x11
6509#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN 0x0001
6510#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_AN_FST_TMR 0x0040
6511#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1 0x14
6512#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SGMII 0x0001
6513#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_LINK 0x0002
6514#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_DUPLEX 0x0004
6515#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_MASK 0x0018
6516#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_SHIFT 3
6517#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_2_5G 0x0018
6518#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_1G 0x0010
6519#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_100M 0x0008
6520#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_10M 0x0000
6521#define MDIO_SERDES_DIGITAL_A_1000X_STATUS2 0x15
6522#define MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED 0x0002
6523#define MDIO_SERDES_DIGITAL_MISC1 0x18
6524#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_MASK 0xE000
6525#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_25M 0x0000
6526#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_100M 0x2000
6527#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_125M 0x4000
6528#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M 0x6000
6529#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_187_5M 0x8000
6530#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL 0x0010
6531#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK 0x000f
6532#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_2_5G 0x0000
6533#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_5G 0x0001
6534#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_6G 0x0002
6535#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_HIG 0x0003
6536#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4 0x0004
6537#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12G 0x0005
6538#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12_5G 0x0006
6539#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G 0x0007
6540#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_15G 0x0008
6541#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_16G 0x0009
6542
6543#define MDIO_REG_BANK_OVER_1G 0x8320
6544#define MDIO_OVER_1G_DIGCTL_3_4 0x14
6545#define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_MASK 0xffe0
6546#define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_SHIFT 5
6547#define MDIO_OVER_1G_UP1 0x19
6548#define MDIO_OVER_1G_UP1_2_5G 0x0001
6549#define MDIO_OVER_1G_UP1_5G 0x0002
6550#define MDIO_OVER_1G_UP1_6G 0x0004
6551#define MDIO_OVER_1G_UP1_10G 0x0010
6552#define MDIO_OVER_1G_UP1_10GH 0x0008
6553#define MDIO_OVER_1G_UP1_12G 0x0020
6554#define MDIO_OVER_1G_UP1_12_5G 0x0040
6555#define MDIO_OVER_1G_UP1_13G 0x0080
6556#define MDIO_OVER_1G_UP1_15G 0x0100
6557#define MDIO_OVER_1G_UP1_16G 0x0200
6558#define MDIO_OVER_1G_UP2 0x1A
6559#define MDIO_OVER_1G_UP2_IPREDRIVER_MASK 0x0007
6560#define MDIO_OVER_1G_UP2_IDRIVER_MASK 0x0038
6561#define MDIO_OVER_1G_UP2_PREEMPHASIS_MASK 0x03C0
6562#define MDIO_OVER_1G_UP3 0x1B
6563#define MDIO_OVER_1G_UP3_HIGIG2 0x0001
6564#define MDIO_OVER_1G_LP_UP1 0x1C
6565#define MDIO_OVER_1G_LP_UP2 0x1D
6566#define MDIO_OVER_1G_LP_UP2_MR_ADV_OVER_1G_MASK 0x03ff
6567#define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK 0x0780
6568#define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT 7
6569#define MDIO_OVER_1G_LP_UP3 0x1E
6570
6571#define MDIO_REG_BANK_REMOTE_PHY 0x8330
6572#define MDIO_REMOTE_PHY_MISC_RX_STATUS 0x10
6573#define MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG 0x0010
6574#define MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG 0x0600
6575
6576#define MDIO_REG_BANK_BAM_NEXT_PAGE 0x8350
6577#define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL 0x10
6578#define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE 0x0001
6579#define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN 0x0002
6580
6581#define MDIO_REG_BANK_CL73_USERB0 0x8370
6582#define MDIO_CL73_USERB0_CL73_UCTRL 0x10
6583#define MDIO_CL73_USERB0_CL73_UCTRL_USTAT1_MUXSEL 0x0002
6584#define MDIO_CL73_USERB0_CL73_USTAT1 0x11
6585#define MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK 0x0100
6586#define MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37 0x0400
6587#define MDIO_CL73_USERB0_CL73_BAM_CTRL1 0x12
6588#define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN 0x8000
6589#define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN 0x4000
6590#define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN 0x2000
6591#define MDIO_CL73_USERB0_CL73_BAM_CTRL3 0x14
6592#define MDIO_CL73_USERB0_CL73_BAM_CTRL3_USE_CL73_HCD_MR 0x0001
6593
6594#define MDIO_REG_BANK_AER_BLOCK 0xFFD0
6595#define MDIO_AER_BLOCK_AER_REG 0x1E
6596
6597#define MDIO_REG_BANK_COMBO_IEEE0 0xFFE0
6598#define MDIO_COMBO_IEEE0_MII_CONTROL 0x10
6599#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK 0x2040
6600#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_10 0x0000
6601#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100 0x2000
6602#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000 0x0040
6603#define MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX 0x0100
6604#define MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN 0x0200
6605#define MDIO_COMBO_IEEO_MII_CONTROL_AN_EN 0x1000
6606#define MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK 0x4000
6607#define MDIO_COMBO_IEEO_MII_CONTROL_RESET 0x8000
6608#define MDIO_COMBO_IEEE0_MII_STATUS 0x11
6609#define MDIO_COMBO_IEEE0_MII_STATUS_LINK_PASS 0x0004
6610#define MDIO_COMBO_IEEE0_MII_STATUS_AUTONEG_COMPLETE 0x0020
6611#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV 0x14
6612#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX 0x0020
6613#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_HALF_DUPLEX 0x0040
6614#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK 0x0180
6615#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE 0x0000
6616#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC 0x0080
6617#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC 0x0100
6618#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH 0x0180
6619#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_NEXT_PAGE 0x8000
6620#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1 0x15
6621#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_NEXT_PAGE 0x8000
6622#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_ACK 0x4000
6623#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_MASK 0x0180
6624#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_NONE 0x0000
6625#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_BOTH 0x0180
6626#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_HALF_DUP_CAP 0x0040
6627#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_FULL_DUP_CAP 0x0020
6628/*WhenthelinkpartnerisinSGMIImode(bit0=1),then
6629bit15=link,bit12=duplex,bits11:10=speed,bit14=acknowledge.
6630Theotherbitsarereservedandshouldbezero*/
6631#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_SGMII_MODE 0x0001
6632
6633
6634#define MDIO_PMA_DEVAD 0x1
6635/*ieee*/
6636#define MDIO_PMA_REG_CTRL 0x0
6637#define MDIO_PMA_REG_STATUS 0x1
6638#define MDIO_PMA_REG_10G_CTRL2 0x7
6639#define MDIO_PMA_REG_TX_DISABLE 0x0009
6640#define MDIO_PMA_REG_RX_SD 0xa
6641/*bcm*/
6642#define MDIO_PMA_REG_BCM_CTRL 0x0096
6643#define MDIO_PMA_REG_FEC_CTRL 0x00ab
6644#define MDIO_PMA_REG_PHY_IDENTIFIER 0xc800
6645#define MDIO_PMA_REG_DIGITAL_CTRL 0xc808
6646#define MDIO_PMA_REG_DIGITAL_STATUS 0xc809
6647#define MDIO_PMA_REG_TX_POWER_DOWN 0xca02
6648#define MDIO_PMA_REG_CMU_PLL_BYPASS 0xca09
6649#define MDIO_PMA_REG_MISC_CTRL 0xca0a
6650#define MDIO_PMA_REG_GEN_CTRL 0xca10
6651#define MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP 0x0188
6652#define MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET 0x018a
6653#define MDIO_PMA_REG_M8051_MSGIN_REG 0xca12
6654#define MDIO_PMA_REG_M8051_MSGOUT_REG 0xca13
6655#define MDIO_PMA_REG_ROM_VER1 0xca19
6656#define MDIO_PMA_REG_ROM_VER2 0xca1a
6657#define MDIO_PMA_REG_EDC_FFE_MAIN 0xca1b
6658#define MDIO_PMA_REG_PLL_BANDWIDTH 0xca1d
6659#define MDIO_PMA_REG_PLL_CTRL 0xca1e
6660#define MDIO_PMA_REG_MISC_CTRL0 0xca23
6661#define MDIO_PMA_REG_LRM_MODE 0xca3f
6662#define MDIO_PMA_REG_CDR_BANDWIDTH 0xca46
6663#define MDIO_PMA_REG_MISC_CTRL1 0xca85
6664
6665#define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL 0x8000
6666#define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK 0x000c
6667#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE 0x0000
6668#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE 0x0004
6669#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IN_PROGRESS 0x0008
6670#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_FAILED 0x000c
6671#define MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT 0x8002
6672#define MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR 0x8003
6673#define MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF 0xc820
6674#define MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK 0xff
6675#define MDIO_PMA_REG_8726_TX_CTRL1 0xca01
6676#define MDIO_PMA_REG_8726_TX_CTRL2 0xca05
6677
6678#define MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR 0x8005
6679#define MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF 0x8007
6680#define MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK 0xff
6681#define MDIO_PMA_REG_8727_TX_CTRL1 0xca02
6682#define MDIO_PMA_REG_8727_TX_CTRL2 0xca05
6683#define MDIO_PMA_REG_8727_PCS_OPT_CTRL 0xc808
6684#define MDIO_PMA_REG_8727_GPIO_CTRL 0xc80e
6685#define MDIO_PMA_REG_8727_PCS_GP 0xc842
6686#define MDIO_PMA_REG_8727_OPT_CFG_REG 0xc8e4
6687
6688#define MDIO_AN_REG_8727_MISC_CTRL 0x8309
6689
6690#define MDIO_PMA_REG_8073_CHIP_REV 0xc801
6691#define MDIO_PMA_REG_8073_SPEED_LINK_STATUS 0xc820
6692#define MDIO_PMA_REG_8073_XAUI_WA 0xc841
6693#define MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL 0xcd08
6694
6695#define MDIO_PMA_REG_7101_RESET 0xc000
6696#define MDIO_PMA_REG_7107_LED_CNTL 0xc007
6697#define MDIO_PMA_REG_7107_LINK_LED_CNTL 0xc009
6698#define MDIO_PMA_REG_7101_VER1 0xc026
6699#define MDIO_PMA_REG_7101_VER2 0xc027
6700
6701#define MDIO_PMA_REG_8481_PMD_SIGNAL 0xa811
6702#define MDIO_PMA_REG_8481_LED1_MASK 0xa82c
6703#define MDIO_PMA_REG_8481_LED2_MASK 0xa82f
6704#define MDIO_PMA_REG_8481_LED3_MASK 0xa832
6705#define MDIO_PMA_REG_8481_LED3_BLINK 0xa834
6706#define MDIO_PMA_REG_8481_LED5_MASK 0xa838
6707#define MDIO_PMA_REG_8481_SIGNAL_MASK 0xa835
6708#define MDIO_PMA_REG_8481_LINK_SIGNAL 0xa83b
6709#define MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK 0x800
6710#define MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT 11
6711
6712
6713#define MDIO_WIS_DEVAD 0x2
6714/*bcm*/
6715#define MDIO_WIS_REG_LASI_CNTL 0x9002
6716#define MDIO_WIS_REG_LASI_STATUS 0x9005
6717
6718#define MDIO_PCS_DEVAD 0x3
6719#define MDIO_PCS_REG_STATUS 0x0020
6720#define MDIO_PCS_REG_LASI_STATUS 0x9005
6721#define MDIO_PCS_REG_7101_DSP_ACCESS 0xD000
6722#define MDIO_PCS_REG_7101_SPI_MUX 0xD008
6723#define MDIO_PCS_REG_7101_SPI_CTRL_ADDR 0xE12A
6724#define MDIO_PCS_REG_7101_SPI_RESET_BIT (5)
6725#define MDIO_PCS_REG_7101_SPI_FIFO_ADDR 0xE02A
6726#define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_WRITE_ENABLE_CMD (6)
6727#define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_BULK_ERASE_CMD (0xC7)
6728#define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_PAGE_PROGRAM_CMD (2)
6729#define MDIO_PCS_REG_7101_SPI_BYTES_TO_TRANSFER_ADDR 0xE028
6730
6731
6732#define MDIO_XS_DEVAD 0x4
6733#define MDIO_XS_PLL_SEQUENCER 0x8000
6734#define MDIO_XS_SFX7101_XGXS_TEST1 0xc00a
6735
6736#define MDIO_XS_8706_REG_BANK_RX0 0x80bc
6737#define MDIO_XS_8706_REG_BANK_RX1 0x80cc
6738#define MDIO_XS_8706_REG_BANK_RX2 0x80dc
6739#define MDIO_XS_8706_REG_BANK_RX3 0x80ec
6740#define MDIO_XS_8706_REG_BANK_RXA 0x80fc
6741
6742#define MDIO_XS_REG_8073_RX_CTRL_PCIE 0x80FA
6743
6744#define MDIO_AN_DEVAD 0x7
6745/*ieee*/
6746#define MDIO_AN_REG_CTRL 0x0000
6747#define MDIO_AN_REG_STATUS 0x0001
6748#define MDIO_AN_REG_STATUS_AN_COMPLETE 0x0020
6749#define MDIO_AN_REG_ADV_PAUSE 0x0010
6750#define MDIO_AN_REG_ADV_PAUSE_PAUSE 0x0400
6751#define MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC 0x0800
6752#define MDIO_AN_REG_ADV_PAUSE_BOTH 0x0C00
6753#define MDIO_AN_REG_ADV_PAUSE_MASK 0x0C00
6754#define MDIO_AN_REG_ADV 0x0011
6755#define MDIO_AN_REG_ADV2 0x0012
6756#define MDIO_AN_REG_LP_AUTO_NEG 0x0013
6757#define MDIO_AN_REG_MASTER_STATUS 0x0021
6758/*bcm*/
6759#define MDIO_AN_REG_LINK_STATUS 0x8304
6760#define MDIO_AN_REG_CL37_CL73 0x8370
6761#define MDIO_AN_REG_CL37_AN 0xffe0
6762#define MDIO_AN_REG_CL37_FC_LD 0xffe4
6763#define MDIO_AN_REG_CL37_FC_LP 0xffe5
6764
6765#define MDIO_AN_REG_8073_2_5G 0x8329
6766#define MDIO_AN_REG_8073_BAM 0x8350
6767
6768#define MDIO_AN_REG_8481_10GBASE_T_AN_CTRL 0x0020
6769#define MDIO_AN_REG_8481_LEGACY_MII_CTRL 0xffe0
6770#define MDIO_AN_REG_8481_LEGACY_MII_STATUS 0xffe1
6771#define MDIO_AN_REG_8481_LEGACY_AN_ADV 0xffe4
6772#define MDIO_AN_REG_8481_LEGACY_AN_EXPANSION 0xffe6
6773#define MDIO_AN_REG_8481_1000T_CTRL 0xffe9
6774#define MDIO_AN_REG_8481_EXPANSION_REG_RD_RW 0xfff5
6775#define MDIO_AN_REG_8481_EXPANSION_REG_ACCESS 0xfff7
6776#define MDIO_AN_REG_8481_AUX_CTRL 0xfff8
6777#define MDIO_AN_REG_8481_LEGACY_SHADOW 0xfffc
6778
6779/* BCM84823 only */
6780#define MDIO_CTL_DEVAD 0x1e
6781#define MDIO_CTL_REG_84823_MEDIA 0x401a
6782#define MDIO_CTL_REG_84823_MEDIA_MAC_MASK 0x0018
6783 /* These pins configure the BCM84823 interface to MAC after reset. */
6784#define MDIO_CTL_REG_84823_CTRL_MAC_XFI 0x0008
6785#define MDIO_CTL_REG_84823_MEDIA_MAC_XAUI_M 0x0010
6786 /* These pins configure the BCM84823 interface to Line after reset. */
6787#define MDIO_CTL_REG_84823_MEDIA_LINE_MASK 0x0060
6788#define MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L 0x0020
6789#define MDIO_CTL_REG_84823_MEDIA_LINE_XFI 0x0040
6790 /* When this pin is active high during reset, 10GBASE-T core is power
6791 * down, When it is active low the 10GBASE-T is power up
6792 */
6793#define MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN 0x0080
6794#define MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK 0x0100
6795#define MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER 0x0000
6796#define MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER 0x0100
6797#define MDIO_CTL_REG_84823_MEDIA_FIBER_1G 0x1000
6798#define MDIO_CTL_REG_84823_USER_CTRL_REG 0x4005
6799#define MDIO_CTL_REG_84823_USER_CTRL_CMS 0x0080
6800
6801#define MDIO_PMA_REG_84823_CTL_LED_CTL_1 0xa8e3
6802#define MDIO_PMA_REG_84823_LED3_STRETCH_EN 0x0080
6803
6804/* BCM84833 only */
6805#define MDIO_84833_TOP_CFG_XGPHY_STRAP1 0x401a
6806#define MDIO_84833_SUPER_ISOLATE 0x8000
6807/* These are mailbox register set used by 84833. */
6808#define MDIO_84833_TOP_CFG_SCRATCH_REG0 0x4005
6809#define MDIO_84833_TOP_CFG_SCRATCH_REG1 0x4006
6810#define MDIO_84833_TOP_CFG_SCRATCH_REG2 0x4007
6811#define MDIO_84833_TOP_CFG_SCRATCH_REG3 0x4008
6812#define MDIO_84833_TOP_CFG_SCRATCH_REG4 0x4009
6813#define MDIO_84833_TOP_CFG_DATA3_REG 0x4011
6814#define MDIO_84833_TOP_CFG_DATA4_REG 0x4012
6815
6816/* Mailbox command set used by 84833. */
6817#define PHY84833_DIAG_CMD_PAIR_SWAP_CHANGE 0x2
6818/* Mailbox status set used by 84833. */
6819#define PHY84833_CMD_RECEIVED 0x0001
6820#define PHY84833_CMD_IN_PROGRESS 0x0002
6821#define PHY84833_CMD_COMPLETE_PASS 0x0004
6822#define PHY84833_CMD_COMPLETE_ERROR 0x0008
6823#define PHY84833_CMD_OPEN_FOR_CMDS 0x0010
6824#define PHY84833_CMD_SYSTEM_BOOT 0x0020
6825#define PHY84833_CMD_NOT_OPEN_FOR_CMDS 0x0040
6826#define PHY84833_CMD_CLEAR_COMPLETE 0x0080
6827#define PHY84833_CMD_OPEN_OVERRIDE 0xa5a5
6828
6829
6830/* 84833 F/W Feature Commands */
6831#define PHY84833_DIAG_CMD_GET_EEE_MODE 0x27
6832#define PHY84833_DIAG_CMD_SET_EEE_MODE 0x28
6833
6834/* Warpcore clause 45 addressing */
6835#define MDIO_WC_DEVAD 0x3
6836#define MDIO_WC_REG_IEEE0BLK_MIICNTL 0x0
6837#define MDIO_WC_REG_IEEE0BLK_AUTONEGNP 0x7
6838#define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT0 0x10
6839#define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1 0x11
6840#define MDIO_WC_REG_PMD_IEEE9BLK_TENGBASE_KR_PMD_CONTROL_REGISTER_150 0x96
6841#define MDIO_WC_REG_XGXSBLK0_XGXSCONTROL 0x8000
6842#define MDIO_WC_REG_XGXSBLK0_MISCCONTROL1 0x800e
6843#define MDIO_WC_REG_XGXSBLK1_DESKEW 0x8010
6844#define MDIO_WC_REG_XGXSBLK1_LANECTRL0 0x8015
6845#define MDIO_WC_REG_XGXSBLK1_LANECTRL1 0x8016
6846#define MDIO_WC_REG_XGXSBLK1_LANECTRL2 0x8017
6847#define MDIO_WC_REG_TX0_ANA_CTRL0 0x8061
6848#define MDIO_WC_REG_TX1_ANA_CTRL0 0x8071
6849#define MDIO_WC_REG_TX2_ANA_CTRL0 0x8081
6850#define MDIO_WC_REG_TX3_ANA_CTRL0 0x8091
6851#define MDIO_WC_REG_TX0_TX_DRIVER 0x8067
6852#define MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET 0x04
6853#define MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_MASK 0x00f0
6854#define MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET 0x08
6855#define MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
6856#define MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET 0x0c
6857#define MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_MASK 0x7000
6858#define MDIO_WC_REG_TX1_TX_DRIVER 0x8077
6859#define MDIO_WC_REG_TX2_TX_DRIVER 0x8087
6860#define MDIO_WC_REG_TX3_TX_DRIVER 0x8097
6861#define MDIO_WC_REG_RX0_ANARXCONTROL1G 0x80b9
6862#define MDIO_WC_REG_RX2_ANARXCONTROL1G 0x80d9
6863#define MDIO_WC_REG_RX0_PCI_CTRL 0x80ba
6864#define MDIO_WC_REG_RX1_PCI_CTRL 0x80ca
6865#define MDIO_WC_REG_RX2_PCI_CTRL 0x80da
6866#define MDIO_WC_REG_RX3_PCI_CTRL 0x80ea
6867#define MDIO_WC_REG_XGXSBLK2_UNICORE_MODE_10G 0x8104
6868#define MDIO_WC_REG_XGXS_STATUS3 0x8129
6869#define MDIO_WC_REG_PAR_DET_10G_STATUS 0x8130
6870#define MDIO_WC_REG_PAR_DET_10G_CTRL 0x8131
6871#define MDIO_WC_REG_XGXS_X2_CONTROL2 0x8141
6872#define MDIO_WC_REG_XGXS_RX_LN_SWAP1 0x816B
6873#define MDIO_WC_REG_XGXS_TX_LN_SWAP1 0x8169
6874#define MDIO_WC_REG_GP2_STATUS_GP_2_0 0x81d0
6875#define MDIO_WC_REG_GP2_STATUS_GP_2_1 0x81d1
6876#define MDIO_WC_REG_GP2_STATUS_GP_2_2 0x81d2
6877#define MDIO_WC_REG_GP2_STATUS_GP_2_3 0x81d3
6878#define MDIO_WC_REG_GP2_STATUS_GP_2_4 0x81d4
6879#define MDIO_WC_REG_UC_INFO_B0_DEAD_TRAP 0x81EE
6880#define MDIO_WC_REG_UC_INFO_B1_VERSION 0x81F0
6881#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE 0x81F2
6882#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE0_OFFSET 0x0
6883#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT 0x0
6884#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_OPT_LR 0x1
6885#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC 0x2
6886#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_XLAUI 0x3
6887#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_LONG_CH_6G 0x4
6888#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE1_OFFSET 0x4
6889#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE2_OFFSET 0x8
6890#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE3_OFFSET 0xc
6891#define MDIO_WC_REG_UC_INFO_B1_CRC 0x81FE
6892#define MDIO_WC_REG_DSC_SMC 0x8213
6893#define MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0 0x821e
6894#define MDIO_WC_REG_TX_FIR_TAP 0x82e2
6895#define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET 0x00
6896#define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_MASK 0x000f
6897#define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET 0x04
6898#define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_MASK 0x03f0
6899#define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET 0x0a
6900#define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_MASK 0x7c00
6901#define MDIO_WC_REG_TX_FIR_TAP_ENABLE 0x8000
6902#define MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL 0x82e3
6903#define MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL 0x82e6
6904#define MDIO_WC_REG_CL72_USERB0_CL72_BR_DEF_CTRL 0x82e7
6905#define MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL 0x82e8
6906#define MDIO_WC_REG_CL72_USERB0_CL72_MISC4_CONTROL 0x82ec
6907#define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1 0x8300
6908#define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2 0x8301
6909#define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3 0x8302
6910#define MDIO_WC_REG_SERDESDIGITAL_STATUS1000X1 0x8304
6911#define MDIO_WC_REG_SERDESDIGITAL_MISC1 0x8308
6912#define MDIO_WC_REG_SERDESDIGITAL_MISC2 0x8309
6913#define MDIO_WC_REG_DIGITAL3_UP1 0x8329
6914#define MDIO_WC_REG_DIGITAL4_MISC3 0x833c
6915#define MDIO_WC_REG_DIGITAL5_MISC6 0x8345
6916#define MDIO_WC_REG_DIGITAL5_MISC7 0x8349
6917#define MDIO_WC_REG_DIGITAL5_ACTUAL_SPEED 0x834e
6918#define MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL 0x8350
6919#define MDIO_WC_REG_CL49_USERB0_CTRL 0x8368
6920#define MDIO_WC_REG_TX66_CONTROL 0x83b0
6921#define MDIO_WC_REG_RX66_CONTROL 0x83c0
6922#define MDIO_WC_REG_RX66_SCW0 0x83c2
6923#define MDIO_WC_REG_RX66_SCW1 0x83c3
6924#define MDIO_WC_REG_RX66_SCW2 0x83c4
6925#define MDIO_WC_REG_RX66_SCW3 0x83c5
6926#define MDIO_WC_REG_RX66_SCW0_MASK 0x83c6
6927#define MDIO_WC_REG_RX66_SCW1_MASK 0x83c7
6928#define MDIO_WC_REG_RX66_SCW2_MASK 0x83c8
6929#define MDIO_WC_REG_RX66_SCW3_MASK 0x83c9
6930#define MDIO_WC_REG_FX100_CTRL1 0x8400
6931#define MDIO_WC_REG_FX100_CTRL3 0x8402
6932
6933#define MDIO_WC_REG_MICROBLK_CMD 0xffc2
6934#define MDIO_WC_REG_MICROBLK_DL_STATUS 0xffc5
6935#define MDIO_WC_REG_MICROBLK_CMD3 0xffcc
6936
6937#define MDIO_WC_REG_AERBLK_AER 0xffde
6938#define MDIO_WC_REG_COMBO_IEEE0_MIICTRL 0xffe0
6939#define MDIO_WC_REG_COMBO_IEEE0_MIIISTAT 0xffe1
6940
6941#define MDIO_WC0_XGXS_BLK2_LANE_RESET 0x810A
6942#define MDIO_WC0_XGXS_BLK2_LANE_RESET_RX_BITSHIFT 0
6943#define MDIO_WC0_XGXS_BLK2_LANE_RESET_TX_BITSHIFT 4
6944
6945#define MDIO_WC0_XGXS_BLK6_XGXS_X2_CONTROL2 0x8141
6946
6947#define DIGITAL5_ACTUAL_SPEED_TX_MASK 0x003f
6948
6949/* 54618se */
6950#define MDIO_REG_GPHY_PHYID_LSB 0x3
6951#define MDIO_REG_GPHY_ID_54618SE 0x5cd5
6952#define MDIO_REG_GPHY_CL45_ADDR_REG 0xd
6953#define MDIO_REG_GPHY_CL45_DATA_REG 0xe
6954#define MDIO_REG_GPHY_EEE_ADV 0x3c
6955#define MDIO_REG_GPHY_EEE_1G (0x1 << 2)
6956#define MDIO_REG_GPHY_EEE_100 (0x1 << 1)
6957#define MDIO_REG_GPHY_EEE_RESOLVED 0x803e
6958#define MDIO_REG_INTR_STATUS 0x1a
6959#define MDIO_REG_INTR_MASK 0x1b
6960#define MDIO_REG_INTR_MASK_LINK_STATUS (0x1 << 1)
6961#define MDIO_REG_GPHY_SHADOW 0x1c
6962#define MDIO_REG_GPHY_SHADOW_LED_SEL2 (0x0e << 10)
6963#define MDIO_REG_GPHY_SHADOW_WR_ENA (0x1 << 15)
6964#define MDIO_REG_GPHY_SHADOW_AUTO_DET_MED (0x1e << 10)
6965#define MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD (0x1 << 8)
6966
6967#define IGU_FUNC_BASE 0x0400
6968
6969#define IGU_ADDR_MSIX 0x0000
6970#define IGU_ADDR_INT_ACK 0x0200
6971#define IGU_ADDR_PROD_UPD 0x0201
6972#define IGU_ADDR_ATTN_BITS_UPD 0x0202
6973#define IGU_ADDR_ATTN_BITS_SET 0x0203
6974#define IGU_ADDR_ATTN_BITS_CLR 0x0204
6975#define IGU_ADDR_COALESCE_NOW 0x0205
6976#define IGU_ADDR_SIMD_MASK 0x0206
6977#define IGU_ADDR_SIMD_NOMASK 0x0207
6978#define IGU_ADDR_MSI_CTL 0x0210
6979#define IGU_ADDR_MSI_ADDR_LO 0x0211
6980#define IGU_ADDR_MSI_ADDR_HI 0x0212
6981#define IGU_ADDR_MSI_DATA 0x0213
6982
6983#define IGU_USE_REGISTER_ustorm_type_0_sb_cleanup 0
6984#define IGU_USE_REGISTER_ustorm_type_1_sb_cleanup 1
6985#define IGU_USE_REGISTER_cstorm_type_0_sb_cleanup 2
6986#define IGU_USE_REGISTER_cstorm_type_1_sb_cleanup 3
6987
6988#define COMMAND_REG_INT_ACK 0x0
6989#define COMMAND_REG_PROD_UPD 0x4
6990#define COMMAND_REG_ATTN_BITS_UPD 0x8
6991#define COMMAND_REG_ATTN_BITS_SET 0xc
6992#define COMMAND_REG_ATTN_BITS_CLR 0x10
6993#define COMMAND_REG_COALESCE_NOW 0x14
6994#define COMMAND_REG_SIMD_MASK 0x18
6995#define COMMAND_REG_SIMD_NOMASK 0x1c
6996
6997
6998#define IGU_MEM_BASE 0x0000
6999
7000#define IGU_MEM_MSIX_BASE 0x0000
7001#define IGU_MEM_MSIX_UPPER 0x007f
7002#define IGU_MEM_MSIX_RESERVED_UPPER 0x01ff
7003
7004#define IGU_MEM_PBA_MSIX_BASE 0x0200
7005#define IGU_MEM_PBA_MSIX_UPPER 0x0200
7006
7007#define IGU_CMD_BACKWARD_COMP_PROD_UPD 0x0201
7008#define IGU_MEM_PBA_MSIX_RESERVED_UPPER 0x03ff
7009
7010#define IGU_CMD_INT_ACK_BASE 0x0400
7011#define IGU_CMD_INT_ACK_UPPER\
7012 (IGU_CMD_INT_ACK_BASE + MAX_SB_PER_PORT * NUM_OF_PORTS_PER_PATH - 1)
7013#define IGU_CMD_INT_ACK_RESERVED_UPPER 0x04ff
7014
7015#define IGU_CMD_E2_PROD_UPD_BASE 0x0500
7016#define IGU_CMD_E2_PROD_UPD_UPPER\
7017 (IGU_CMD_E2_PROD_UPD_BASE + MAX_SB_PER_PORT * NUM_OF_PORTS_PER_PATH - 1)
7018#define IGU_CMD_E2_PROD_UPD_RESERVED_UPPER 0x059f
7019
7020#define IGU_CMD_ATTN_BIT_UPD_UPPER 0x05a0
7021#define IGU_CMD_ATTN_BIT_SET_UPPER 0x05a1
7022#define IGU_CMD_ATTN_BIT_CLR_UPPER 0x05a2
7023
7024#define IGU_REG_SISR_MDPC_WMASK_UPPER 0x05a3
7025#define IGU_REG_SISR_MDPC_WMASK_LSB_UPPER 0x05a4
7026#define IGU_REG_SISR_MDPC_WMASK_MSB_UPPER 0x05a5
7027#define IGU_REG_SISR_MDPC_WOMASK_UPPER 0x05a6
7028
7029#define IGU_REG_RESERVED_UPPER 0x05ff
7030/* Fields of IGU PF CONFIGRATION REGISTER */
7031#define IGU_PF_CONF_FUNC_EN (0x1<<0) /* function enable */
7032#define IGU_PF_CONF_MSI_MSIX_EN (0x1<<1) /* MSI/MSIX enable */
7033#define IGU_PF_CONF_INT_LINE_EN (0x1<<2) /* INT enable */
7034#define IGU_PF_CONF_ATTN_BIT_EN (0x1<<3) /* attention enable */
7035#define IGU_PF_CONF_SINGLE_ISR_EN (0x1<<4) /* single ISR mode enable */
7036#define IGU_PF_CONF_SIMD_MODE (0x1<<5) /* simd all ones mode */
7037
7038/* Fields of IGU VF CONFIGRATION REGISTER */
7039#define IGU_VF_CONF_FUNC_EN (0x1<<0) /* function enable */
7040#define IGU_VF_CONF_MSI_MSIX_EN (0x1<<1) /* MSI/MSIX enable */
7041#define IGU_VF_CONF_PARENT_MASK (0x3<<2) /* Parent PF */
7042#define IGU_VF_CONF_PARENT_SHIFT 2 /* Parent PF */
7043#define IGU_VF_CONF_SINGLE_ISR_EN (0x1<<4) /* single ISR mode enable */
7044
7045
7046#define IGU_BC_DSB_NUM_SEGS 5
7047#define IGU_BC_NDSB_NUM_SEGS 2
7048#define IGU_NORM_DSB_NUM_SEGS 2
7049#define IGU_NORM_NDSB_NUM_SEGS 1
7050#define IGU_BC_BASE_DSB_PROD 128
7051#define IGU_NORM_BASE_DSB_PROD 136
7052
7053 /* FID (if VF - [6] = 0; [5:0] = VF number; if PF - [6] = 1; \
7054 [5:2] = 0; [1:0] = PF number) */
7055#define IGU_FID_ENCODE_IS_PF (0x1<<6)
7056#define IGU_FID_ENCODE_IS_PF_SHIFT 6
7057#define IGU_FID_VF_NUM_MASK (0x3f)
7058#define IGU_FID_PF_NUM_MASK (0x7)
7059
7060#define IGU_REG_MAPPING_MEMORY_VALID (1<<0)
7061#define IGU_REG_MAPPING_MEMORY_VECTOR_MASK (0x3F<<1)
7062#define IGU_REG_MAPPING_MEMORY_VECTOR_SHIFT 1
7063#define IGU_REG_MAPPING_MEMORY_FID_MASK (0x7F<<7)
7064#define IGU_REG_MAPPING_MEMORY_FID_SHIFT 7
7065
7066
7067#define CDU_REGION_NUMBER_XCM_AG 2
7068#define CDU_REGION_NUMBER_UCM_AG 4
7069
7070
7071/**
7072 * String-to-compress [31:8] = CID (all 24 bits)
7073 * String-to-compress [7:4] = Region
7074 * String-to-compress [3:0] = Type
7075 */
7076#define CDU_VALID_DATA(_cid, _region, _type)\
7077 (((_cid) << 8) | (((_region)&0xf)<<4) | (((_type)&0xf)))
7078#define CDU_CRC8(_cid, _region, _type)\
7079 (calc_crc8(CDU_VALID_DATA(_cid, _region, _type), 0xff))
7080#define CDU_RSRVD_VALUE_TYPE_A(_cid, _region, _type)\
7081 (0x80 | ((CDU_CRC8(_cid, _region, _type)) & 0x7f))
7082#define CDU_RSRVD_VALUE_TYPE_B(_crc, _type)\
7083 (0x80 | ((_type)&0xf << 3) | ((CDU_CRC8(_cid, _region, _type)) & 0x7))
7084#define CDU_RSRVD_INVALIDATE_CONTEXT_VALUE(_val) ((_val) & ~0x80)
7085
7086/******************************************************************************
7087 * Description:
7088 * Calculates crc 8 on a word value: polynomial 0-1-2-8
7089 * Code was translated from Verilog.
7090 * Return:
7091 *****************************************************************************/
7092static inline u8 calc_crc8(u32 data, u8 crc)
7093{
7094 u8 D[32];
7095 u8 NewCRC[8];
7096 u8 C[8];
7097 u8 crc_res;
7098 u8 i;
7099
7100 /* split the data into 31 bits */
7101 for (i = 0; i < 32; i++) {
7102 D[i] = (u8)(data & 1);
7103 data = data >> 1;
7104 }
7105
7106 /* split the crc into 8 bits */
7107 for (i = 0; i < 8; i++) {
7108 C[i] = crc & 1;
7109 crc = crc >> 1;
7110 }
7111
7112 NewCRC[0] = D[31] ^ D[30] ^ D[28] ^ D[23] ^ D[21] ^ D[19] ^ D[18] ^
7113 D[16] ^ D[14] ^ D[12] ^ D[8] ^ D[7] ^ D[6] ^ D[0] ^ C[4] ^
7114 C[6] ^ C[7];
7115 NewCRC[1] = D[30] ^ D[29] ^ D[28] ^ D[24] ^ D[23] ^ D[22] ^ D[21] ^
7116 D[20] ^ D[18] ^ D[17] ^ D[16] ^ D[15] ^ D[14] ^ D[13] ^
7117 D[12] ^ D[9] ^ D[6] ^ D[1] ^ D[0] ^ C[0] ^ C[4] ^ C[5] ^
7118 C[6];
7119 NewCRC[2] = D[29] ^ D[28] ^ D[25] ^ D[24] ^ D[22] ^ D[17] ^ D[15] ^
7120 D[13] ^ D[12] ^ D[10] ^ D[8] ^ D[6] ^ D[2] ^ D[1] ^ D[0] ^
7121 C[0] ^ C[1] ^ C[4] ^ C[5];
7122 NewCRC[3] = D[30] ^ D[29] ^ D[26] ^ D[25] ^ D[23] ^ D[18] ^ D[16] ^
7123 D[14] ^ D[13] ^ D[11] ^ D[9] ^ D[7] ^ D[3] ^ D[2] ^ D[1] ^
7124 C[1] ^ C[2] ^ C[5] ^ C[6];
7125 NewCRC[4] = D[31] ^ D[30] ^ D[27] ^ D[26] ^ D[24] ^ D[19] ^ D[17] ^
7126 D[15] ^ D[14] ^ D[12] ^ D[10] ^ D[8] ^ D[4] ^ D[3] ^ D[2] ^
7127 C[0] ^ C[2] ^ C[3] ^ C[6] ^ C[7];
7128 NewCRC[5] = D[31] ^ D[28] ^ D[27] ^ D[25] ^ D[20] ^ D[18] ^ D[16] ^
7129 D[15] ^ D[13] ^ D[11] ^ D[9] ^ D[5] ^ D[4] ^ D[3] ^ C[1] ^
7130 C[3] ^ C[4] ^ C[7];
7131 NewCRC[6] = D[29] ^ D[28] ^ D[26] ^ D[21] ^ D[19] ^ D[17] ^ D[16] ^
7132 D[14] ^ D[12] ^ D[10] ^ D[6] ^ D[5] ^ D[4] ^ C[2] ^ C[4] ^
7133 C[5];
7134 NewCRC[7] = D[30] ^ D[29] ^ D[27] ^ D[22] ^ D[20] ^ D[18] ^ D[17] ^
7135 D[15] ^ D[13] ^ D[11] ^ D[7] ^ D[6] ^ D[5] ^ C[3] ^ C[5] ^
7136 C[6];
7137
7138 crc_res = 0;
7139 for (i = 0; i < 8; i++)
7140 crc_res |= (NewCRC[i] << i);
7141
7142 return crc_res;
7143}
7144
7145
7146#endif /* BNX2X_REG_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-18 22:57:54 -0500