New 7.0 FW: bnx2x, cnic, bnx2i, bnx2fc

New FW/HSI (7.0):
 - Added support to 578xx chips
 - Improved HSI - much less driver's direct access to the FW internal
   memory needed.

New implementation of the HSI handling layer in the bnx2x (bnx2x_sp.c):
 - Introduced chip dependent objects that have chip independent interfaces
   for configuration of MACs, multicast addresses, Rx mode, indirection table,
   fast path queues and function initialization/cleanup.
 - Objects functionality is based on the private function pointers, which
   allows not only a per-chip but also PF/VF differentiation while still
   preserving the same interface towards the driver.
 - Objects interface is not influenced by the HSI changes which do not require
   providing new parameters keeping the code outside the bnx2x_sp.c invariant
   with regard to such HSI chnages.

Changes in a CNIC, bnx2fc and bnx2i modules due to the new HSI.

Signed-off-by: Vladislav Zolotarov <vladz@broadcom.com>
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: Bhanu Prakash Gollapudi <bprakash@broadcom.com>
Signed-off-by: Eilon Greenstein <eilong@broadcom.com>
Signed-off-by: David S. Miller <davem@conan.davemloft.net>

1 files changed, 489 insertions, 381 deletions

diff --git a/drivers/net/bnx2x/bnx2x.h b/drivers/net/bnx2x/bnx2x.h
index 6d4d6d4e53c6..b4b3abe9e7c4 100644
--- a/drivers/net/bnx2x/bnx2x.h
+++ b/drivers/net/bnx2x/bnx2x.h
@@ -47,11 +47,12 @@
 #endif
 
 #include <linux/mdio.h>
-#include <linux/pci.h>
+
 #include "bnx2x_reg.h"
 #include "bnx2x_fw_defs.h"
 #include "bnx2x_hsi.h"
 #include "bnx2x_link.h"
+#include "bnx2x_sp.h"
 #include "bnx2x_dcb.h"
 #include "bnx2x_stats.h"
 
@@ -80,6 +81,12 @@ do {								\
                        ##__args);                               \
 } while (0)
 
+#define DP_CONT(__mask, __fmt, __args...)                       \
+do {                                                            \
+        if (bp->msg_enable & (__mask))                          \
+                pr_cont(__fmt, ##__args);                       \
+} while (0)
+
 /* errors debug print */
 #define BNX2X_DBG_ERR(__fmt, __args...)                         \
 do {                                                            \
@@ -111,7 +118,9 @@ do {								 \
                 dev_info(&bp->pdev->dev, __fmt, ##__args);       \
 } while (0)
 
-void bnx2x_panic_dump(struct bnx2x *bp);
+#define BNX2X_MAC_FMT           "%pM"
+#define BNX2X_MAC_PRN_LIST(mac) (mac)
+
 
 #ifdef BNX2X_STOP_ON_ERROR
 #define bnx2x_panic() do { \
@@ -233,11 +242,11 @@ void bnx2x_panic_dump(struct bnx2x *bp);
  *
  */
 /* iSCSI L2 */
-#define BNX2X_ISCSI_ETH_CL_ID           17
+#define BNX2X_ISCSI_ETH_CL_ID_IDX       1
 #define BNX2X_ISCSI_ETH_CID             17
 
 /* FCoE L2 */
-#define BNX2X_FCOE_ETH_CL_ID            18
+#define BNX2X_FCOE_ETH_CL_ID_IDX        2
 #define BNX2X_FCOE_ETH_CID              18
 
 /** Additional rings budgeting */
@@ -283,44 +292,73 @@ union db_prod {
 
 
 /* MC hsi */
-#define BCM_PAGE_SHIFT                  12
-#define BCM_PAGE_SIZE                   (1 << BCM_PAGE_SHIFT)
-#define BCM_PAGE_MASK                   (~(BCM_PAGE_SIZE - 1))
+#define BCM_PAGE_SHIFT          12
+#define BCM_PAGE_SIZE           (1 << BCM_PAGE_SHIFT)
+#define BCM_PAGE_MASK           (~(BCM_PAGE_SIZE - 1))
 #define BCM_PAGE_ALIGN(addr)    (((addr) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK)
 
-#define PAGES_PER_SGE_SHIFT             0
-#define PAGES_PER_SGE                   (1 << PAGES_PER_SGE_SHIFT)
-#define SGE_PAGE_SIZE                   PAGE_SIZE
-#define SGE_PAGE_SHIFT                  PAGE_SHIFT
-#define SGE_PAGE_ALIGN(addr)            PAGE_ALIGN((typeof(PAGE_SIZE))(addr))
+#define PAGES_PER_SGE_SHIFT     0
+#define PAGES_PER_SGE           (1 << PAGES_PER_SGE_SHIFT)
+#define SGE_PAGE_SIZE           PAGE_SIZE
+#define SGE_PAGE_SHIFT          PAGE_SHIFT
+#define SGE_PAGE_ALIGN(addr)    PAGE_ALIGN((typeof(PAGE_SIZE))(addr))
 
 /* SGE ring related macros */
-#define NUM_RX_SGE_PAGES                2
+#define NUM_RX_SGE_PAGES        2
 #define RX_SGE_CNT              (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge))
-#define MAX_RX_SGE_CNT                  (RX_SGE_CNT - 2)
+#define MAX_RX_SGE_CNT          (RX_SGE_CNT - 2)
 /* RX_SGE_CNT is promised to be a power of 2 */
-#define RX_SGE_MASK                     (RX_SGE_CNT - 1)
-#define NUM_RX_SGE                      (RX_SGE_CNT * NUM_RX_SGE_PAGES)
-#define MAX_RX_SGE                      (NUM_RX_SGE - 1)
+#define RX_SGE_MASK             (RX_SGE_CNT - 1)
+#define NUM_RX_SGE              (RX_SGE_CNT * NUM_RX_SGE_PAGES)
+#define MAX_RX_SGE              (NUM_RX_SGE - 1)
 #define NEXT_SGE_IDX(x)         ((((x) & RX_SGE_MASK) == \
                                   (MAX_RX_SGE_CNT - 1)) ? (x) + 3 : (x) + 1)
-#define RX_SGE(x)                       ((x) & MAX_RX_SGE)
+#define RX_SGE(x)               ((x) & MAX_RX_SGE)
+
+/* Manipulate a bit vector defined as an array of u64 */
 
-/* SGE producer mask related macros */
 /* Number of bits in one sge_mask array element */
-#define RX_SGE_MASK_ELEM_SZ             64
-#define RX_SGE_MASK_ELEM_SHIFT          6
-#define RX_SGE_MASK_ELEM_MASK           ((u64)RX_SGE_MASK_ELEM_SZ - 1)
+#define BIT_VEC64_ELEM_SZ               64
+#define BIT_VEC64_ELEM_SHIFT            6
+#define BIT_VEC64_ELEM_MASK             ((u64)BIT_VEC64_ELEM_SZ - 1)
+
+
+#define __BIT_VEC64_SET_BIT(el, bit) \
+        do { \
+                el = ((el) | ((u64)0x1 << (bit))); \
+        } while (0)
+
+#define __BIT_VEC64_CLEAR_BIT(el, bit) \
+        do { \
+                el = ((el) & (~((u64)0x1 << (bit)))); \
+        } while (0)
+
+
+#define BIT_VEC64_SET_BIT(vec64, idx) \
+        __BIT_VEC64_SET_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \
+                           (idx) & BIT_VEC64_ELEM_MASK)
+
+#define BIT_VEC64_CLEAR_BIT(vec64, idx) \
+        __BIT_VEC64_CLEAR_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \
+                             (idx) & BIT_VEC64_ELEM_MASK)
+
+#define BIT_VEC64_TEST_BIT(vec64, idx) \
+        (((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT] >> \
+        ((idx) & BIT_VEC64_ELEM_MASK)) & 0x1)
 
 /* Creates a bitmask of all ones in less significant bits.
    idx - index of the most significant bit in the created mask */
-#define RX_SGE_ONES_MASK(idx) \
-                (((u64)0x1 << (((idx) & RX_SGE_MASK_ELEM_MASK) + 1)) - 1)
-#define RX_SGE_MASK_ELEM_ONE_MASK       ((u64)(~0))
+#define BIT_VEC64_ONES_MASK(idx) \
+                (((u64)0x1 << (((idx) & BIT_VEC64_ELEM_MASK) + 1)) - 1)
+#define BIT_VEC64_ELEM_ONE_MASK ((u64)(~0))
+
+/*******************************************************/
+
+
 
 /* Number of u64 elements in SGE mask array */
 #define RX_SGE_MASK_LEN                 ((NUM_RX_SGE_PAGES * RX_SGE_CNT) / \
-                                         RX_SGE_MASK_ELEM_SZ)
+                                         BIT_VEC64_ELEM_SZ)
 #define RX_SGE_MASK_LEN_MASK            (RX_SGE_MASK_LEN - 1)
 #define NEXT_SGE_MASK_ELEM(el)          (((el) + 1) & RX_SGE_MASK_LEN_MASK)
 
@@ -331,7 +369,30 @@ union host_hc_status_block {
         struct host_hc_status_block_e2  *e2_sb;
 };
 
+struct bnx2x_agg_info {
+        /*
+         * First aggregation buffer is an skb, the following - are pages.
+         * We will preallocate the skbs for each aggregation when
+         * we open the interface and will replace the BD at the consumer
+         * with this one when we receive the TPA_START CQE in order to
+         * keep the Rx BD ring consistent.
+         */
+        struct sw_rx_bd         first_buf;
+        u8                      tpa_state;
+#define BNX2X_TPA_START                 1
+#define BNX2X_TPA_STOP                  2
+#define BNX2X_TPA_ERROR                 3
+        u8                      placement_offset;
+        u16                     parsing_flags;
+        u16                     vlan_tag;
+        u16                     len_on_bd;
+};
+
+#define Q_STATS_OFFSET32(stat_name) \
+                        (offsetof(struct bnx2x_eth_q_stats, stat_name) / 4)
+
 struct bnx2x_fastpath {
+        struct bnx2x            *bp; /* parent */
 
 #define BNX2X_NAPI_WEIGHT       128
         struct napi_struct      napi;
@@ -366,23 +427,13 @@ struct bnx2x_fastpath {
 
         u64                     sge_mask[RX_SGE_MASK_LEN];
 
-        int                     state;
-#define BNX2X_FP_STATE_CLOSED           0
-#define BNX2X_FP_STATE_IRQ              0x80000
-#define BNX2X_FP_STATE_OPENING          0x90000
-#define BNX2X_FP_STATE_OPEN             0xa0000
-#define BNX2X_FP_STATE_HALTING          0xb0000
-#define BNX2X_FP_STATE_HALTED           0xc0000
-#define BNX2X_FP_STATE_TERMINATING      0xd0000
-#define BNX2X_FP_STATE_TERMINATED       0xe0000
+        u32                     cid;
 
         u8                      index;          /* number in fp array */
         u8                      cl_id;          /* eth client id */
         u8                      cl_qzone_id;
         u8                      fw_sb_id;       /* status block number in FW */
         u8                      igu_sb_id;      /* status block number in HW */
-        u32                     cid;
-
         union db_prod           tx_db;
 
         u16                     tx_pkt_prod;
@@ -401,24 +452,20 @@ struct bnx2x_fastpath {
         /* The last maximal completed SGE */
         u16                     last_max_sge;
         __le16                  *rx_cons_sb;
-
         unsigned long           tx_pkt,
                                 rx_pkt,
                                 rx_calls;
 
         /* TPA related */
-        struct sw_rx_bd         tpa_pool[ETH_MAX_AGGREGATION_QUEUES_E1H];
-        u8                      tpa_state[ETH_MAX_AGGREGATION_QUEUES_E1H];
-#define BNX2X_TPA_START                 1
-#define BNX2X_TPA_STOP                  2
+        struct bnx2x_agg_info   tpa_info[ETH_MAX_AGGREGATION_QUEUES_E1H_E2];
         u8                      disable_tpa;
 #ifdef BNX2X_STOP_ON_ERROR
         u64                     tpa_queue_used;
 #endif
 
-        struct tstorm_per_client_stats old_tclient;
-        struct ustorm_per_client_stats old_uclient;
-        struct xstorm_per_client_stats old_xclient;
+        struct tstorm_per_queue_stats old_tclient;
+        struct ustorm_per_queue_stats old_uclient;
+        struct xstorm_per_queue_stats old_xclient;
         struct bnx2x_eth_q_stats eth_q_stats;
 
         /* The size is calculated using the following:
@@ -427,7 +474,13 @@ struct bnx2x_fastpath {
              4 (for the digits and to make it DWORD aligned) */
 #define FP_NAME_SIZE            (sizeof(((struct net_device *)0)->name) + 8)
         char                    name[FP_NAME_SIZE];
-        struct bnx2x            *bp; /* parent */
+
+        /* MACs object */
+        struct bnx2x_vlan_mac_obj mac_obj;
+
+        /* Queue State object */
+        struct bnx2x_queue_sp_obj q_obj;
+
 };
 
 #define bnx2x_fp(bp, nr, var)           (bp->fp[nr].var)
@@ -435,11 +488,13 @@ struct bnx2x_fastpath {
 /* Use 2500 as a mini-jumbo MTU for FCoE */
 #define BNX2X_FCOE_MINI_JUMBO_MTU       2500
 
-#ifdef BCM_CNIC
-/* FCoE L2 `fastpath' is right after the eth entries */
+/* FCoE L2 `fastpath' entry is right after the eth entries */
 #define FCOE_IDX                        BNX2X_NUM_ETH_QUEUES(bp)
 #define bnx2x_fcoe_fp(bp)               (&bp->fp[FCOE_IDX])
 #define bnx2x_fcoe(bp, var)             (bnx2x_fcoe_fp(bp)->var)
+
+
+#ifdef BCM_CNIC
 #define IS_FCOE_FP(fp)                  (fp->index == FCOE_IDX)
 #define IS_FCOE_IDX(idx)                ((idx) == FCOE_IDX)
 #else
@@ -449,77 +504,68 @@ struct bnx2x_fastpath {
 
 
 /* MC hsi */
-#define MAX_FETCH_BD                    13      /* HW max BDs per packet */
-#define RX_COPY_THRESH                  92
+#define MAX_FETCH_BD            13      /* HW max BDs per packet */
+#define RX_COPY_THRESH          92
 
-#define NUM_TX_RINGS                    16
+#define NUM_TX_RINGS            16
 #define TX_DESC_CNT             (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types))
-#define MAX_TX_DESC_CNT                 (TX_DESC_CNT - 1)
-#define NUM_TX_BD                       (TX_DESC_CNT * NUM_TX_RINGS)
-#define MAX_TX_BD                       (NUM_TX_BD - 1)
-#define MAX_TX_AVAIL                    (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2)
-#define INIT_JUMBO_TX_RING_SIZE         MAX_TX_AVAIL
-#define INIT_TX_RING_SIZE               MAX_TX_AVAIL
+#define MAX_TX_DESC_CNT         (TX_DESC_CNT - 1)
+#define NUM_TX_BD               (TX_DESC_CNT * NUM_TX_RINGS)
+#define MAX_TX_BD               (NUM_TX_BD - 1)
+#define MAX_TX_AVAIL            (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2)
 #define NEXT_TX_IDX(x)          ((((x) & MAX_TX_DESC_CNT) == \
                                   (MAX_TX_DESC_CNT - 1)) ? (x) + 2 : (x) + 1)
-#define TX_BD(x)                        ((x) & MAX_TX_BD)
-#define TX_BD_POFF(x)                   ((x) & MAX_TX_DESC_CNT)
+#define TX_BD(x)                ((x) & MAX_TX_BD)
+#define TX_BD_POFF(x)           ((x) & MAX_TX_DESC_CNT)
 
 /* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */
-#define NUM_RX_RINGS                    8
+#define NUM_RX_RINGS            8
 #define RX_DESC_CNT             (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd))
-#define MAX_RX_DESC_CNT                 (RX_DESC_CNT - 2)
-#define RX_DESC_MASK                    (RX_DESC_CNT - 1)
-#define NUM_RX_BD                       (RX_DESC_CNT * NUM_RX_RINGS)
-#define MAX_RX_BD                       (NUM_RX_BD - 1)
-#define MAX_RX_AVAIL                    (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2)
-#define MIN_RX_SIZE_TPA                 72
-#define MIN_RX_SIZE_NONTPA              10
-#define INIT_JUMBO_RX_RING_SIZE         MAX_RX_AVAIL
-#define INIT_RX_RING_SIZE               MAX_RX_AVAIL
+#define MAX_RX_DESC_CNT         (RX_DESC_CNT - 2)
+#define RX_DESC_MASK            (RX_DESC_CNT - 1)
+#define NUM_RX_BD               (RX_DESC_CNT * NUM_RX_RINGS)
+#define MAX_RX_BD               (NUM_RX_BD - 1)
+#define MAX_RX_AVAIL            (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2)
+#define MIN_RX_AVAIL            128
+
+#define MIN_RX_SIZE_TPA_HW      (CHIP_IS_E1(bp) ? \
+                                        ETH_MIN_RX_CQES_WITH_TPA_E1 : \
+                                        ETH_MIN_RX_CQES_WITH_TPA_E1H_E2)
+#define MIN_RX_SIZE_NONTPA_HW   ETH_MIN_RX_CQES_WITHOUT_TPA
+#define MIN_RX_SIZE_TPA         (max_t(u32, MIN_RX_SIZE_TPA_HW, MIN_RX_AVAIL))
+#define MIN_RX_SIZE_NONTPA      (max_t(u32, MIN_RX_SIZE_NONTPA_HW,\
+                                                                MIN_RX_AVAIL))
+
 #define NEXT_RX_IDX(x)          ((((x) & RX_DESC_MASK) == \
                                   (MAX_RX_DESC_CNT - 1)) ? (x) + 3 : (x) + 1)
-#define RX_BD(x)                        ((x) & MAX_RX_BD)
+#define RX_BD(x)                ((x) & MAX_RX_BD)
 
-/* As long as CQE is 4 times bigger than BD entry we have to allocate
-   4 times more pages for CQ ring in order to keep it balanced with
-   BD ring */
-#define NUM_RCQ_RINGS                   (NUM_RX_RINGS * 4)
+/*
+ * As long as CQE is X times bigger than BD entry we have to allocate X times
+ * more pages for CQ ring in order to keep it balanced with BD ring
+ */
+#define CQE_BD_REL      (sizeof(union eth_rx_cqe) / sizeof(struct eth_rx_bd))
+#define NUM_RCQ_RINGS           (NUM_RX_RINGS * CQE_BD_REL)
 #define RCQ_DESC_CNT            (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe))
-#define MAX_RCQ_DESC_CNT                (RCQ_DESC_CNT - 1)
-#define NUM_RCQ_BD                      (RCQ_DESC_CNT * NUM_RCQ_RINGS)
-#define MAX_RCQ_BD                      (NUM_RCQ_BD - 1)
-#define MAX_RCQ_AVAIL                   (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2)
+#define MAX_RCQ_DESC_CNT        (RCQ_DESC_CNT - 1)
+#define NUM_RCQ_BD              (RCQ_DESC_CNT * NUM_RCQ_RINGS)
+#define MAX_RCQ_BD              (NUM_RCQ_BD - 1)
+#define MAX_RCQ_AVAIL           (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2)
 #define NEXT_RCQ_IDX(x)         ((((x) & MAX_RCQ_DESC_CNT) == \
                                   (MAX_RCQ_DESC_CNT - 1)) ? (x) + 2 : (x) + 1)
-#define RCQ_BD(x)                       ((x) & MAX_RCQ_BD)
+#define RCQ_BD(x)               ((x) & MAX_RCQ_BD)
 
 
 /* This is needed for determining of last_max */
-#define SUB_S16(a, b)                   (s16)((s16)(a) - (s16)(b))
-
-#define __SGE_MASK_SET_BIT(el, bit) \
-        do { \
-                el = ((el) | ((u64)0x1 << (bit))); \
-        } while (0)
-
-#define __SGE_MASK_CLEAR_BIT(el, bit) \
-        do { \
-                el = ((el) & (~((u64)0x1 << (bit)))); \
-        } while (0)
-
-#define SGE_MASK_SET_BIT(fp, idx) \
-        __SGE_MASK_SET_BIT(fp->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \
-                           ((idx) & RX_SGE_MASK_ELEM_MASK))
+#define SUB_S16(a, b)           (s16)((s16)(a) - (s16)(b))
+#define SUB_S32(a, b)           (s32)((s32)(a) - (s32)(b))
 
-#define SGE_MASK_CLEAR_BIT(fp, idx) \
-        __SGE_MASK_CLEAR_BIT(fp->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \
-                             ((idx) & RX_SGE_MASK_ELEM_MASK))
 
+#define BNX2X_SWCID_SHIFT       17
+#define BNX2X_SWCID_MASK        ((0x1 << BNX2X_SWCID_SHIFT) - 1)
 
 /* used on a CID received from the HW */
-#define SW_CID(x)                       (le32_to_cpu(x) & \
-                                         (COMMON_RAMROD_ETH_RX_CQE_CID >> 7))
+#define SW_CID(x)                       (le32_to_cpu(x) & BNX2X_SWCID_MASK)
 #define CQE_CMD(x)                      (le32_to_cpu(x) >> \
                                         COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT)
 
@@ -529,6 +575,9 @@ struct bnx2x_fastpath {
 
 #define BNX2X_DB_MIN_SHIFT              3       /* 8 bytes */
 #define BNX2X_DB_SHIFT                  7       /* 128 bytes*/
+#if (BNX2X_DB_SHIFT < BNX2X_DB_MIN_SHIFT)
+#error "Min DB doorbell stride is 8"
+#endif
 #define DPM_TRIGER_TYPE                 0x40
 #define DOORBELL(bp, cid, val) \
         do { \
@@ -557,13 +606,11 @@ struct bnx2x_fastpath {
 
 
 /* stuff added to make the code fit 80Col */
-
-#define CQE_TYPE(cqe_fp_flags)  ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE)
-
-#define TPA_TYPE_START                  ETH_FAST_PATH_RX_CQE_START_FLG
-#define TPA_TYPE_END                    ETH_FAST_PATH_RX_CQE_END_FLG
-#define TPA_TYPE(cqe_fp_flags)          ((cqe_fp_flags) & \
-                                         (TPA_TYPE_START | TPA_TYPE_END))
+#define CQE_TYPE(cqe_fp_flags)   ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE)
+#define CQE_TYPE_START(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_START_AGG)
+#define CQE_TYPE_STOP(cqe_type)  ((cqe_type) == RX_ETH_CQE_TYPE_ETH_STOP_AGG)
+#define CQE_TYPE_SLOW(cqe_type)  ((cqe_type) == RX_ETH_CQE_TYPE_ETH_RAMROD)
+#define CQE_TYPE_FAST(cqe_type)  ((cqe_type) == RX_ETH_CQE_TYPE_ETH_FASTPATH)
 
 #define ETH_RX_ERROR_FALGS              ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG
 
@@ -590,12 +637,30 @@ struct bnx2x_fastpath {
 #define BNX2X_RX_SUM_FIX(cqe) \
         BNX2X_PRS_FLAG_OVERETH_IPV4(cqe->fast_path_cqe.pars_flags.flags)
 
-#define U_SB_ETH_RX_CQ_INDEX            1
-#define U_SB_ETH_RX_BD_INDEX            2
-#define C_SB_ETH_TX_CQ_INDEX            5
+
+#define FP_USB_FUNC_OFF \
+                        offsetof(struct cstorm_status_block_u, func)
+#define FP_CSB_FUNC_OFF \
+                        offsetof(struct cstorm_status_block_c, func)
+
+#define HC_INDEX_TOE_RX_CQ_CONS         0 /* Formerly Ustorm TOE CQ index */
+                                          /* (HC_INDEX_U_TOE_RX_CQ_CONS)  */
+#define HC_INDEX_ETH_RX_CQ_CONS         1 /* Formerly Ustorm ETH CQ index */
+                                          /* (HC_INDEX_U_ETH_RX_CQ_CONS)  */
+#define HC_INDEX_ETH_RX_BD_CONS         2 /* Formerly Ustorm ETH BD index */
+                                          /* (HC_INDEX_U_ETH_RX_BD_CONS)  */
+
+#define HC_INDEX_TOE_TX_CQ_CONS         4 /* Formerly Cstorm TOE CQ index   */
+                                          /* (HC_INDEX_C_TOE_TX_CQ_CONS)    */
+#define HC_INDEX_ETH_TX_CQ_CONS         5 /* Formerly Cstorm ETH CQ index   */
+                                          /* (HC_INDEX_C_ETH_TX_CQ_CONS)    */
+
+#define U_SB_ETH_RX_CQ_INDEX            HC_INDEX_ETH_RX_CQ_CONS
+#define U_SB_ETH_RX_BD_INDEX            HC_INDEX_ETH_RX_BD_CONS
+#define C_SB_ETH_TX_CQ_INDEX            HC_INDEX_ETH_TX_CQ_CONS
 
 #define BNX2X_RX_SB_INDEX \
-        (&fp->sb_index_values[U_SB_ETH_RX_CQ_INDEX])
+        (&fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS])
 
 #define BNX2X_TX_SB_INDEX \
         (&fp->sb_index_values[C_SB_ETH_TX_CQ_INDEX])
@@ -615,29 +680,53 @@ struct bnx2x_common {
 #define CHIP_NUM_57711                  0x164f
 #define CHIP_NUM_57711E                 0x1650
 #define CHIP_NUM_57712                  0x1662
-#define CHIP_NUM_57712E                 0x1663
+#define CHIP_NUM_57712_MF               0x1663
+#define CHIP_NUM_57713                  0x1651
+#define CHIP_NUM_57713E                 0x1652
+#define CHIP_NUM_57800                  0x168a
+#define CHIP_NUM_57800_MF               0x16a5
+#define CHIP_NUM_57810                  0x168e
+#define CHIP_NUM_57810_MF               0x16ae
+#define CHIP_NUM_57840                  0x168d
+#define CHIP_NUM_57840_MF               0x16ab
 #define CHIP_IS_E1(bp)                  (CHIP_NUM(bp) == CHIP_NUM_57710)
 #define CHIP_IS_57711(bp)               (CHIP_NUM(bp) == CHIP_NUM_57711)
 #define CHIP_IS_57711E(bp)              (CHIP_NUM(bp) == CHIP_NUM_57711E)
 #define CHIP_IS_57712(bp)               (CHIP_NUM(bp) == CHIP_NUM_57712)
-#define CHIP_IS_57712E(bp)              (CHIP_NUM(bp) == CHIP_NUM_57712E)
+#define CHIP_IS_57712_MF(bp)            (CHIP_NUM(bp) == CHIP_NUM_57712_MF)
+#define CHIP_IS_57800(bp)               (CHIP_NUM(bp) == CHIP_NUM_57800)
+#define CHIP_IS_57800_MF(bp)            (CHIP_NUM(bp) == CHIP_NUM_57800_MF)
+#define CHIP_IS_57810(bp)               (CHIP_NUM(bp) == CHIP_NUM_57810)
+#define CHIP_IS_57810_MF(bp)            (CHIP_NUM(bp) == CHIP_NUM_57810_MF)
+#define CHIP_IS_57840(bp)               (CHIP_NUM(bp) == CHIP_NUM_57840)
+#define CHIP_IS_57840_MF(bp)            (CHIP_NUM(bp) == CHIP_NUM_57840_MF)
 #define CHIP_IS_E1H(bp)                 (CHIP_IS_57711(bp) || \
                                          CHIP_IS_57711E(bp))
 #define CHIP_IS_E2(bp)                  (CHIP_IS_57712(bp) || \
-                                         CHIP_IS_57712E(bp))
+                                         CHIP_IS_57712_MF(bp))
+#define CHIP_IS_E3(bp)                  (CHIP_IS_57800(bp) || \
+                                         CHIP_IS_57800_MF(bp) || \
+                                         CHIP_IS_57810(bp) || \
+                                         CHIP_IS_57810_MF(bp) || \
+                                         CHIP_IS_57840(bp) || \
+                                         CHIP_IS_57840_MF(bp))
 #define CHIP_IS_E1x(bp)                 (CHIP_IS_E1((bp)) || CHIP_IS_E1H((bp)))
-#define IS_E1H_OFFSET                   (CHIP_IS_E1H(bp) || CHIP_IS_E2(bp))
-
-#define CHIP_REV(bp)                    (bp->common.chip_id & 0x0000f000)
-#define CHIP_REV_Ax                     0x00000000
+#define USES_WARPCORE(bp)               (CHIP_IS_E3(bp))
+#define IS_E1H_OFFSET                   (!CHIP_IS_E1(bp))
+
+#define CHIP_REV_SHIFT                  12
+#define CHIP_REV_MASK                   (0xF << CHIP_REV_SHIFT)
+#define CHIP_REV_VAL(bp)                (bp->common.chip_id & CHIP_REV_MASK)
+#define CHIP_REV_Ax                     (0x0 << CHIP_REV_SHIFT)
+#define CHIP_REV_Bx                     (0x1 << CHIP_REV_SHIFT)
 /* assume maximum 5 revisions */
-#define CHIP_REV_IS_SLOW(bp)            (CHIP_REV(bp) > 0x00005000)
+#define CHIP_REV_IS_SLOW(bp)            (CHIP_REV_VAL(bp) > 0x00005000)
 /* Emul versions are A=>0xe, B=>0xc, C=>0xa, D=>8, E=>6 */
 #define CHIP_REV_IS_EMUL(bp)            ((CHIP_REV_IS_SLOW(bp)) && \
-                                         !(CHIP_REV(bp) & 0x00001000))
+                                         !(CHIP_REV_VAL(bp) & 0x00001000))
 /* FPGA versions are A=>0xf, B=>0xd, C=>0xb, D=>9, E=>7 */
 #define CHIP_REV_IS_FPGA(bp)            ((CHIP_REV_IS_SLOW(bp)) && \
-                                         (CHIP_REV(bp) & 0x00001000))
+                                         (CHIP_REV_VAL(bp) & 0x00001000))
 
 #define CHIP_TIME(bp)                   ((CHIP_REV_IS_EMUL(bp)) ? 2000 : \
                                         ((CHIP_REV_IS_FPGA(bp)) ? 200 : 1))
@@ -645,6 +734,16 @@ struct bnx2x_common {
 #define CHIP_METAL(bp)                  (bp->common.chip_id & 0x00000ff0)
 #define CHIP_BOND_ID(bp)                (bp->common.chip_id & 0x0000000f)
 #define CHIP_PARITY_ENABLED(bp) (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp))
+#define CHIP_REV_SIM(bp)                (((CHIP_REV_MASK - CHIP_REV_VAL(bp)) >>\
+                                           (CHIP_REV_SHIFT + 1)) \
+                                                << CHIP_REV_SHIFT)
+#define CHIP_REV(bp)                    (CHIP_REV_IS_SLOW(bp) ? \
+                                                CHIP_REV_SIM(bp) :\
+                                                CHIP_REV_VAL(bp))
+#define CHIP_IS_E3B0(bp)                (CHIP_IS_E3(bp) && \
+                                         (CHIP_REV(bp) == CHIP_REV_Bx))
+#define CHIP_IS_E3A0(bp)                (CHIP_IS_E3(bp) && \
+                                         (CHIP_REV(bp) == CHIP_REV_Ax))
 
         int                     flash_size;
 #define NVRAM_1MB_SIZE                  0x20000 /* 1M bit in bytes */
@@ -666,7 +765,7 @@ struct bnx2x_common {
 #define INT_BLOCK_MODE_NORMAL           0
 #define INT_BLOCK_MODE_BW_COMP          2
 #define CHIP_INT_MODE_IS_NBC(bp)                \
-                        (CHIP_IS_E2(bp) &&      \
+                        (!CHIP_IS_E1x(bp) &&    \
                         !((bp)->common.int_block & INT_BLOCK_MODE_BW_COMP))
 #define CHIP_INT_MODE_IS_BC(bp) (!CHIP_INT_MODE_IS_NBC(bp))
 
@@ -712,19 +811,15 @@ struct bnx2x_port {
 
 /* end of port */
 
-/* e1h Classification CAM line allocations */
-enum {
-        CAM_ETH_LINE = 0,
-        CAM_ISCSI_ETH_LINE,
-        CAM_FIP_ETH_LINE,
-        CAM_FIP_MCAST_LINE,
-        CAM_MAX_PF_LINE = CAM_FIP_MCAST_LINE
-};
-/* number of MACs per function in NIG memory - used for SI mode */
-#define NIG_LLH_FUNC_MEM_SIZE           16
-/* number of entries in NIG_REG_LLHX_FUNC_MEM */
-#define NIG_LLH_FUNC_MEM_MAX_OFFSET     8
+#define STATS_OFFSET32(stat_name) \
+                        (offsetof(struct bnx2x_eth_stats, stat_name) / 4)
 
+/* slow path */
+
+/* slow path work-queue */
+extern struct workqueue_struct *bnx2x_wq;
+
+#define BNX2X_MAX_NUM_OF_VFS    64
 #define BNX2X_VF_ID_INVALID     0xFF
 
 /*
@@ -749,8 +844,10 @@ enum {
  *    L2 queue is supported. the cid for the FCoE L2 queue is always X.
  */
 
-#define FP_SB_MAX_E1x           16      /* fast-path interrupt contexts E1x */
-#define FP_SB_MAX_E2            16      /* fast-path interrupt contexts E2 */
+/* fast-path interrupt contexts E1x */
+#define FP_SB_MAX_E1x           16
+/* fast-path interrupt contexts E2 */
+#define FP_SB_MAX_E2            HC_SB_MAX_SB_E2
 
 /*
  * cid_cnt paramter below refers to the value returned by
@@ -761,13 +858,13 @@ enum {
  * The number of FP context allocated by the driver == max number of regular
  * L2 queues + 1 for the FCoE L2 queue
  */
-#define L2_FP_COUNT(cid_cnt)    ((cid_cnt) - CNIC_CONTEXT_USE)
+#define L2_FP_COUNT(cid_cnt)    ((cid_cnt) - FCOE_CONTEXT_USE)
 
 /*
  * The number of FP-SB allocated by the driver == max number of regular L2
  * queues + 1 for the CNIC which also consumes an FP-SB
  */
-#define FP_SB_COUNT(cid_cnt)    ((cid_cnt) - FCOE_CONTEXT_USE)
+#define FP_SB_COUNT(cid_cnt)    ((cid_cnt) - CNIC_CONTEXT_USE)
 #define NUM_IGU_SB_REQUIRED(cid_cnt) \
                                 (FP_SB_COUNT(cid_cnt) - NONE_ETH_CONTEXT_USE)
 
@@ -788,38 +885,61 @@ union cdu_context {
 #define CNIC_ILT_LINES          DIV_ROUND_UP(CNIC_CID_MAX, ILT_PAGE_CIDS)
 #endif
 
-#define QM_ILT_PAGE_SZ_HW       3
-#define QM_ILT_PAGE_SZ          (4096 << QM_ILT_PAGE_SZ_HW) /* 32K */
+#define QM_ILT_PAGE_SZ_HW       0
+#define QM_ILT_PAGE_SZ          (4096 << QM_ILT_PAGE_SZ_HW) /* 4K */
 #define QM_CID_ROUND            1024
 
 #ifdef BCM_CNIC
 /* TM (timers) host DB constants */
-#define TM_ILT_PAGE_SZ_HW       2
-#define TM_ILT_PAGE_SZ          (4096 << TM_ILT_PAGE_SZ_HW) /* 16K */
+#define TM_ILT_PAGE_SZ_HW       0
+#define TM_ILT_PAGE_SZ          (4096 << TM_ILT_PAGE_SZ_HW) /* 4K */
 /* #define TM_CONN_NUM          (CNIC_STARTING_CID+CNIC_ISCSI_CXT_MAX) */
 #define TM_CONN_NUM             1024
 #define TM_ILT_SZ               (8 * TM_CONN_NUM)
 #define TM_ILT_LINES            DIV_ROUND_UP(TM_ILT_SZ, TM_ILT_PAGE_SZ)
 
 /* SRC (Searcher) host DB constants */
-#define SRC_ILT_PAGE_SZ_HW      3
-#define SRC_ILT_PAGE_SZ         (4096 << SRC_ILT_PAGE_SZ_HW) /* 32K */
+#define SRC_ILT_PAGE_SZ_HW      0
+#define SRC_ILT_PAGE_SZ         (4096 << SRC_ILT_PAGE_SZ_HW) /* 4K */
 #define SRC_HASH_BITS           10
 #define SRC_CONN_NUM            (1 << SRC_HASH_BITS) /* 1024 */
 #define SRC_ILT_SZ              (sizeof(struct src_ent) * SRC_CONN_NUM)
 #define SRC_T2_SZ               SRC_ILT_SZ
 #define SRC_ILT_LINES           DIV_ROUND_UP(SRC_ILT_SZ, SRC_ILT_PAGE_SZ)
+
 #endif
 
-#define MAX_DMAE_C                      8
+#define MAX_DMAE_C              8
 
 /* DMA memory not used in fastpath */
 struct bnx2x_slowpath {
-        struct eth_stats_query          fw_stats;
-        struct mac_configuration_cmd    mac_config;
-        struct mac_configuration_cmd    mcast_config;
-        struct mac_configuration_cmd    uc_mac_config;
-        struct client_init_ramrod_data  client_init_data;
+        union {
+                struct mac_configuration_cmd            e1x;
+                struct eth_classify_rules_ramrod_data   e2;
+        } mac_rdata;
+
+
+        union {
+                struct tstorm_eth_mac_filter_config     e1x;
+                struct eth_filter_rules_ramrod_data     e2;
+        } rx_mode_rdata;
+
+        union {
+                struct mac_configuration_cmd            e1;
+                struct eth_multicast_rules_ramrod_data  e2;
+        } mcast_rdata;
+
+        struct eth_rss_update_ramrod_data       rss_rdata;
+
+        /* Queue State related ramrods are always sent under rtnl_lock */
+        union {
+                struct client_init_ramrod_data  init_data;
+                struct client_update_ramrod_data update_data;
+        } q_rdata;
+
+        union {
+                struct function_start_data      func_start;
+        } func_rdata;
 
         /* used by dmae command executer */
         struct dmae_command             dmae[MAX_DMAE_C];
@@ -846,7 +966,7 @@ struct bnx2x_slowpath {
 #define MAX_DYNAMIC_ATTN_GRPS           8
 
 struct attn_route {
-        u32     sig[5];
+        u32 sig[5];
 };
 
 struct iro {
@@ -872,7 +992,7 @@ typedef enum {
         BNX2X_RECOVERY_WAIT,
 } bnx2x_recovery_state_t;
 
-/**
+/*
  * Event queue (EQ or event ring) MC hsi
  * NUM_EQ_PAGES and EQ_DESC_CNT_PAGE must be power of 2
  */
@@ -910,6 +1030,24 @@ enum {
         BNX2X_LINK_REPORT_TX_FC_ON,
 };
 
+enum {
+        BNX2X_PORT_QUERY_IDX,
+        BNX2X_PF_QUERY_IDX,
+        BNX2X_FIRST_QUEUE_QUERY_IDX,
+};
+
+struct bnx2x_fw_stats_req {
+        struct stats_query_header hdr;
+        struct stats_query_entry query[STATS_QUERY_CMD_COUNT];
+};
+
+struct bnx2x_fw_stats_data {
+        struct stats_counter    storm_counters;
+        struct per_port_stats   port;
+        struct per_pf_stats     pf;
+        struct per_queue_stats  queue_stats[1];
+};
+
 struct bnx2x {
         /* Fields used in the tx and intr/napi performance paths
          * are grouped together in the beginning of the structure
@@ -919,10 +1057,23 @@ struct bnx2x {
         void __iomem            *doorbells;
         u16                     db_size;
 
+        u8                      pf_num; /* absolute PF number */
+        u8                      pfid;   /* per-path PF number */
+        int                     base_fw_ndsb; /**/
+#define BP_PATH(bp)                     (CHIP_IS_E1x(bp) ? 0 : (bp->pf_num & 1))
+#define BP_PORT(bp)                     (bp->pfid & 1)
+#define BP_FUNC(bp)                     (bp->pfid)
+#define BP_ABS_FUNC(bp)                 (bp->pf_num)
+#define BP_E1HVN(bp)                    (bp->pfid >> 1)
+#define BP_VN(bp)                       (BP_E1HVN(bp)) /*remove when approved*/
+#define BP_L_ID(bp)                     (BP_E1HVN(bp) << 2)
+#define BP_FW_MB_IDX(bp)                (BP_PORT(bp) +\
+                                         BP_VN(bp) * (CHIP_IS_E1x(bp) ? 2  : 1))
+
         struct net_device       *dev;
         struct pci_dev          *pdev;
 
-        struct iro              *iro_arr;
+        const struct iro        *iro_arr;
 #define IRO (bp->iro_arr)
 
         bnx2x_recovery_state_t  recovery_state;
@@ -940,7 +1091,8 @@ struct bnx2x {
         /* Max supported alignment is 256 (8 shift) */
 #define BNX2X_RX_ALIGN_SHIFT            ((L1_CACHE_SHIFT < 8) ? \
                                          L1_CACHE_SHIFT : 8)
-#define BNX2X_RX_ALIGN                  (1 << BNX2X_RX_ALIGN_SHIFT)
+        /* FW use 2 Cache lines Alignment for start packet and size  */
+#define BNX2X_FW_RX_ALIGN               (2 << BNX2X_RX_ALIGN_SHIFT)
 #define BNX2X_PXP_DRAM_ALIGN            (BNX2X_RX_ALIGN_SHIFT - 5)
 
         struct host_sp_status_block *def_status_blk;
@@ -970,10 +1122,12 @@ struct bnx2x {
         __le16                  *eq_cons_sb;
         atomic_t                eq_spq_left; /* COMMON_XXX ramrods credit */
 
-        /* Flags for marking that there is a STAT_QUERY or
-           SET_MAC ramrod pending */
-        int                     stats_pending;
-        int                     set_mac_pending;
+
+
+        /* Counter for marking that there is a STAT_QUERY ramrod pending */
+        u16                     stats_pending;
+        /*  Counter for completed statistics ramrods */
+        u16                     stats_comp;
 
         /* End of fields used in the performance code paths */
 
@@ -981,47 +1135,27 @@ struct bnx2x {
         int                     msg_enable;
 
         u32                     flags;
-#define PCIX_FLAG                       1
-#define PCI_32BIT_FLAG                  2
-#define ONE_PORT_FLAG                   4
-#define NO_WOL_FLAG                     8
-#define USING_DAC_FLAG                  0x10
-#define USING_MSIX_FLAG                 0x20
-#define USING_MSI_FLAG                  0x40
-
-#define TPA_ENABLE_FLAG                 0x80
-#define NO_MCP_FLAG                     0x100
-#define DISABLE_MSI_FLAG                0x200
+#define PCIX_FLAG                       (1 << 0)
+#define PCI_32BIT_FLAG                  (1 << 1)
+#define ONE_PORT_FLAG                   (1 << 2)
+#define NO_WOL_FLAG                     (1 << 3)
+#define USING_DAC_FLAG                  (1 << 4)
+#define USING_MSIX_FLAG                 (1 << 5)
+#define USING_MSI_FLAG                  (1 << 6)
+#define DISABLE_MSI_FLAG                (1 << 7)
+#define TPA_ENABLE_FLAG                 (1 << 8)
+#define NO_MCP_FLAG                     (1 << 9)
+
 #define BP_NOMCP(bp)                    (bp->flags & NO_MCP_FLAG)
-#define MF_FUNC_DIS                     0x1000
-#define FCOE_MACS_SET                   0x2000
-#define NO_FCOE_FLAG                    0x4000
-#define NO_ISCSI_OOO_FLAG               0x8000
-#define NO_ISCSI_FLAG                   0x10000
+#define MF_FUNC_DIS                     (1 << 11)
+#define OWN_CNIC_IRQ                    (1 << 12)
+#define NO_ISCSI_OOO_FLAG               (1 << 13)
+#define NO_ISCSI_FLAG                   (1 << 14)
+#define NO_FCOE_FLAG                    (1 << 15)
 
-#define NO_FCOE(bp)             ((bp)->flags & NO_FCOE_FLAG)
 #define NO_ISCSI(bp)            ((bp)->flags & NO_ISCSI_FLAG)
 #define NO_ISCSI_OOO(bp)        ((bp)->flags & NO_ISCSI_OOO_FLAG)
-
-        int                     pf_num; /* absolute PF number */
-        int                     pfid;   /* per-path PF number */
-        int                     base_fw_ndsb;
-#define BP_PATH(bp)                     (!CHIP_IS_E2(bp) ? \
-                                                0 : (bp->pf_num & 1))
-#define BP_PORT(bp)                     (bp->pfid & 1)
-#define BP_FUNC(bp)                     (bp->pfid)
-#define BP_ABS_FUNC(bp)                 (bp->pf_num)
-#define BP_E1HVN(bp)                    (bp->pfid >> 1)
-#define BP_VN(bp)                       (CHIP_MODE_IS_4_PORT(bp) ? \
-                                                0 : BP_E1HVN(bp))
-#define BP_L_ID(bp)                     (BP_E1HVN(bp) << 2)
-#define BP_FW_MB_IDX(bp)                (BP_PORT(bp) +\
-                                         BP_VN(bp) * (CHIP_IS_E1x(bp) ? 2  : 1))
-
-#ifdef BCM_CNIC
-#define BCM_CNIC_CID_START              16
-#define BCM_ISCSI_ETH_CL_ID             17
-#endif
+#define NO_FCOE(bp)             ((bp)->flags & NO_FCOE_FLAG)
 
         int                     pm_cap;
         int                     pcie_cap;
@@ -1048,9 +1182,9 @@ struct bnx2x {
 
         struct cmng_struct_per_port cmng;
         u32                     vn_weight_sum;
-
         u32                     mf_config[E1HVN_MAX];
         u32                     mf2_config[E2_FUNC_MAX];
+        u32                     path_has_ovlan; /* E3 */
         u16                     mf_ov;
         u8                      mf_mode;
 #define IS_MF(bp)               (bp->mf_mode != 0)
@@ -1075,32 +1209,20 @@ struct bnx2x {
 
         u32                     lin_cnt;
 
-        int                     state;
+        u16                     state;
 #define BNX2X_STATE_CLOSED              0
 #define BNX2X_STATE_OPENING_WAIT4_LOAD  0x1000
 #define BNX2X_STATE_OPENING_WAIT4_PORT  0x2000
 #define BNX2X_STATE_OPEN                0x3000
 #define BNX2X_STATE_CLOSING_WAIT4_HALT  0x4000
 #define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000
-#define BNX2X_STATE_CLOSING_WAIT4_UNLOAD 0x6000
-#define BNX2X_STATE_FUNC_STARTED        0x7000
+
 #define BNX2X_STATE_DIAG                0xe000
 #define BNX2X_STATE_ERROR               0xf000
 
         int                     multi_mode;
         int                     num_queues;
         int                     disable_tpa;
-        u32                     *rx_indir_table;
-
-        struct tstorm_eth_mac_filter_config     mac_filters;
-#define BNX2X_ACCEPT_NONE               0x0000
-#define BNX2X_ACCEPT_UNICAST            0x0001
-#define BNX2X_ACCEPT_MULTICAST          0x0002
-#define BNX2X_ACCEPT_ALL_UNICAST        0x0004
-#define BNX2X_ACCEPT_ALL_MULTICAST      0x0008
-#define BNX2X_ACCEPT_BROADCAST          0x0010
-#define BNX2X_ACCEPT_UNMATCHED_UCAST    0x0020
-#define BNX2X_PROMISCUOUS_MODE          0x10000
 
         u32                     rx_mode;
 #define BNX2X_RX_MODE_NONE              0
@@ -1108,7 +1230,6 @@ struct bnx2x {
 #define BNX2X_RX_MODE_ALLMULTI          2
 #define BNX2X_RX_MODE_PROMISC           3
 #define BNX2X_MAX_MULTICAST             64
-#define BNX2X_MAX_EMUL_MULTI            16
 
         u8                      igu_dsb_id;
         u8                      igu_base_sb;
@@ -1117,11 +1238,38 @@ struct bnx2x {
 
         struct bnx2x_slowpath   *slowpath;
         dma_addr_t              slowpath_mapping;
+
+        /* Total number of FW statistics requests */
+        u8                      fw_stats_num;
+
+        /*
+         * This is a memory buffer that will contain both statistics
+         * ramrod request and data.
+         */
+        void                    *fw_stats;
+        dma_addr_t              fw_stats_mapping;
+
+        /*
+         * FW statistics request shortcut (points at the
+         * beginning of fw_stats buffer).
+         */
+        struct bnx2x_fw_stats_req       *fw_stats_req;
+        dma_addr_t                      fw_stats_req_mapping;
+        int                             fw_stats_req_sz;
+
+        /*
+         * FW statistics data shortcut (points at the begining of
+         * fw_stats buffer + fw_stats_req_sz).
+         */
+        struct bnx2x_fw_stats_data      *fw_stats_data;
+        dma_addr_t                      fw_stats_data_mapping;
+        int                             fw_stats_data_sz;
+
         struct hw_context       context;
 
         struct bnx2x_ilt        *ilt;
 #define BP_ILT(bp)              ((bp)->ilt)
-#define ILT_MAX_LINES           128
+#define ILT_MAX_LINES           256
 
         int                     l2_cid_count;
 #define L2_ILT_LINES(bp)        (DIV_ROUND_UP((bp)->l2_cid_count, \
@@ -1143,16 +1291,18 @@ struct bnx2x {
         struct cnic_eth_dev     cnic_eth_dev;
         union host_hc_status_block cnic_sb;
         dma_addr_t              cnic_sb_mapping;
-#define CNIC_SB_ID(bp)          ((bp)->base_fw_ndsb + BP_L_ID(bp))
-#define CNIC_IGU_SB_ID(bp)      ((bp)->igu_base_sb)
         struct eth_spe          *cnic_kwq;
         struct eth_spe          *cnic_kwq_prod;
         struct eth_spe          *cnic_kwq_cons;
         struct eth_spe          *cnic_kwq_last;
         u16                     cnic_kwq_pending;
         u16                     cnic_spq_pending;
-        struct mutex            cnic_mutex;
         u8                      fip_mac[ETH_ALEN];
+        struct mutex            cnic_mutex;
+        struct bnx2x_vlan_mac_obj iscsi_l2_mac_obj;
+
+        /* Start index of the "special" (CNIC related) L2 cleints */
+        u8                              cnic_base_cl_id;
 #endif
 
         int                     dmae_ready;
@@ -1189,6 +1339,8 @@ struct bnx2x {
         u16                     *init_ops_offsets;
         /* Data blob - has 32 bit granularity */
         u32                     *init_data;
+        u32                     init_mode_flags;
+#define INIT_MODE_FLAGS(bp)     (bp->init_mode_flags)
         /* Zipped PRAM blobs - raw data */
         const u8                *tsem_int_table_data;
         const u8                *tsem_pram_data;
@@ -1210,8 +1362,10 @@ struct bnx2x {
 #define INIT_CSEM_INT_TABLE_DATA(bp)    (bp->csem_int_table_data)
 #define INIT_CSEM_PRAM_DATA(bp)         (bp->csem_pram_data)
 
+#define PHY_FW_VER_LEN                  20
         char                    fw_ver[32];
         const struct firmware   *firmware;
+
         /* LLDP params */
         struct bnx2x_config_lldp_params         lldp_config_params;
 
@@ -1230,13 +1384,30 @@ struct bnx2x {
         bool dcbx_mode_uset;
 
         struct bnx2x_config_dcbx_params         dcbx_config_params;
-
         struct bnx2x_dcbx_port_params           dcbx_port_params;
         int                                     dcb_version;
 
-        /* DCBX Negotiation results */
+        /* CAM credit pools */
+        struct bnx2x_credit_pool_obj            macs_pool;
+
+        /* RX_MODE object */
+        struct bnx2x_rx_mode_obj                rx_mode_obj;
+
+        /* MCAST object */
+        struct bnx2x_mcast_obj                  mcast_obj;
+
+        /* RSS configuration object */
+        struct bnx2x_rss_config_obj             rss_conf_obj;
+
+        /* Function State controlling object */
+        struct bnx2x_func_sp_obj                func_obj;
+
+        unsigned long                           sp_state;
+
+        /* DCBX Negotation results */
         struct dcbx_features                    dcbx_local_feat;
         u32                                     dcbx_error;
+
 #ifdef BCM_DCBNL
         struct dcbx_features                    dcbx_remote_feat;
         u32                                     dcbx_remote_flags;
@@ -1244,42 +1415,11 @@ struct bnx2x {
         u32                                     pending_max;
 };
 
-/**
- *      Init queue/func interface
- */
-/* queue init flags */
-#define QUEUE_FLG_TPA           0x0001
-#define QUEUE_FLG_CACHE_ALIGN   0x0002
-#define QUEUE_FLG_STATS         0x0004
-#define QUEUE_FLG_OV            0x0008
-#define QUEUE_FLG_VLAN          0x0010
-#define QUEUE_FLG_COS           0x0020
-#define QUEUE_FLG_HC            0x0040
-#define QUEUE_FLG_DHC           0x0080
-#define QUEUE_FLG_OOO           0x0100
-
-#define QUEUE_DROP_IP_CS_ERR    TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR
-#define QUEUE_DROP_TCP_CS_ERR   TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR
-#define QUEUE_DROP_TTL0         TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0
-#define QUEUE_DROP_UDP_CS_ERR   TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR
-
-
-
-/* rss capabilities */
-#define RSS_IPV4_CAP            0x0001
-#define RSS_IPV4_TCP_CAP        0x0002
-#define RSS_IPV6_CAP            0x0004
-#define RSS_IPV6_TCP_CAP        0x0008
-
+/* Tx queues may be less or equal to Rx queues */
+extern int num_queues;
 #define BNX2X_NUM_QUEUES(bp)    (bp->num_queues)
 #define BNX2X_NUM_ETH_QUEUES(bp) (BNX2X_NUM_QUEUES(bp) - NONE_ETH_CONTEXT_USE)
 
-/* ethtool statistics are displayed for all regular ethernet queues and the
- * fcoe L2 queue if not disabled
- */
-#define BNX2X_NUM_STAT_QUEUES(bp) (NO_FCOE(bp) ? BNX2X_NUM_ETH_QUEUES(bp) : \
-                           (BNX2X_NUM_ETH_QUEUES(bp) + FCOE_CONTEXT_USE))
-
 #define is_multi(bp)            (BNX2X_NUM_QUEUES(bp) > 1)
 
 #define BNX2X_MAX_QUEUES(bp)    (bp->igu_sb_cnt - CNIC_CONTEXT_USE)
@@ -1297,107 +1437,15 @@ struct bnx2x {
         TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY
 
 /* func init flags */
-#define FUNC_FLG_STATS          0x0001
-#define FUNC_FLG_TPA            0x0002
-#define FUNC_FLG_SPQ            0x0004
-#define FUNC_FLG_LEADING        0x0008  /* PF only */
-
-struct rxq_pause_params {
-        u16             bd_th_lo;
-        u16             bd_th_hi;
-        u16             rcq_th_lo;
-        u16             rcq_th_hi;
-        u16             sge_th_lo; /* valid iff QUEUE_FLG_TPA */
-        u16             sge_th_hi; /* valid iff QUEUE_FLG_TPA */
-        u16             pri_map;
-};
-
-struct bnx2x_rxq_init_params {
-        /* cxt*/
-        struct eth_context *cxt;
-
-        /* dma */
-        dma_addr_t      dscr_map;
-        dma_addr_t      sge_map;
-        dma_addr_t      rcq_map;
-        dma_addr_t      rcq_np_map;
-
-        u16             flags;
-        u16             drop_flags;
-        u16             mtu;
-        u16             buf_sz;
-        u16             fw_sb_id;
-        u16             cl_id;
-        u16             spcl_id;
-        u16             cl_qzone_id;
-
-        /* valid iff QUEUE_FLG_STATS */
-        u16             stat_id;
-
-        /* valid iff QUEUE_FLG_TPA */
-        u16             tpa_agg_sz;
-        u16             sge_buf_sz;
-        u16             max_sges_pkt;
-
-        /* valid iff QUEUE_FLG_CACHE_ALIGN */
-        u8              cache_line_log;
-
-        u8              sb_cq_index;
-        u32             cid;
-
-        /* desired interrupts per sec. valid iff QUEUE_FLG_HC */
-        u32             hc_rate;
-};
-
-struct bnx2x_txq_init_params {
-        /* cxt*/
-        struct eth_context *cxt;
+#define FUNC_FLG_RSS            0x0001
+#define FUNC_FLG_STATS          0x0002
+/* removed  FUNC_FLG_UNMATCHED  0x0004 */
+#define FUNC_FLG_TPA            0x0008
+#define FUNC_FLG_SPQ            0x0010
+#define FUNC_FLG_LEADING        0x0020  /* PF only */
 
-        /* dma */
-        dma_addr_t      dscr_map;
-
-        u16             flags;
-        u16             fw_sb_id;
-        u8              sb_cq_index;
-        u8              cos;            /* valid iff QUEUE_FLG_COS */
-        u16             stat_id;        /* valid iff QUEUE_FLG_STATS */
-        u16             traffic_type;
-        u32             cid;
-        u16             hc_rate;        /* desired interrupts per sec.*/
-                                        /* valid iff QUEUE_FLG_HC */
-
-};
-
-struct bnx2x_client_ramrod_params {
-        int *pstate;
-        int state;
-        u16 index;
-        u16 cl_id;
-        u32 cid;
-        u8 poll;
-#define CLIENT_IS_FCOE                  0x01
-#define CLIENT_IS_LEADING_RSS           0x02
-        u8 flags;
-};
-
-struct bnx2x_client_init_params {
-        struct rxq_pause_params pause;
-        struct bnx2x_rxq_init_params rxq_params;
-        struct bnx2x_txq_init_params txq_params;
-        struct bnx2x_client_ramrod_params ramrod_params;
-};
-
-struct bnx2x_rss_params {
-        int     mode;
-        u16     cap;
-        u16     result_mask;
-};
 
 struct bnx2x_func_init_params {
-
-        /* rss */
-        struct bnx2x_rss_params *rss;   /* valid iff FUNC_FLG_RSS */
-
         /* dma */
         dma_addr_t      fw_stat_map;    /* valid iff FUNC_FLG_STATS */
         dma_addr_t      spq_map;        /* valid iff FUNC_FLG_SPQ */
@@ -1409,17 +1457,10 @@ struct bnx2x_func_init_params {
 };
 
 #define for_each_eth_queue(bp, var) \
-                        for (var = 0; var < BNX2X_NUM_ETH_QUEUES(bp); var++)
+        for (var = 0; var < BNX2X_NUM_ETH_QUEUES(bp); var++)
 
 #define for_each_nondefault_eth_queue(bp, var) \
-                        for (var = 1; var < BNX2X_NUM_ETH_QUEUES(bp); var++)
-
-#define for_each_napi_queue(bp, var) \
-        for (var = 0; \
-                var < BNX2X_NUM_ETH_QUEUES(bp) + FCOE_CONTEXT_USE; var++) \
-                if (skip_queue(bp, var))        \
-                        continue;               \
-                else
+        for (var = 1; var < BNX2X_NUM_ETH_QUEUES(bp); var++)
 
 #define for_each_queue(bp, var) \
         for (var = 0; var < BNX2X_NUM_QUEUES(bp); var++) \
@@ -1457,11 +1498,66 @@ struct bnx2x_func_init_params {
 
 #define skip_queue(bp, idx)     (NO_FCOE(bp) && IS_FCOE_IDX(idx))
 
-#define WAIT_RAMROD_POLL        0x01
-#define WAIT_RAMROD_COMMON      0x02
 
+
+
+/**
+ * bnx2x_set_mac_one - configure a single MAC address
+ *
+ * @bp:                 driver handle
+ * @mac:                MAC to configure
+ * @obj:                MAC object handle
+ * @set:                if 'true' add a new MAC, otherwise - delete
+ * @mac_type:           the type of the MAC to configure (e.g. ETH, UC list)
+ * @ramrod_flags:       RAMROD_XXX flags (e.g. RAMROD_CONT, RAMROD_COMP_WAIT)
+ *
+ * Configures one MAC according to provided parameters or continues the
+ * execution of previously scheduled commands if RAMROD_CONT is set in
+ * ramrod_flags.
+ *
+ * Returns zero if operation has successfully completed, a positive value if the
+ * operation has been successfully scheduled and a negative - if a requested
+ * operations has failed.
+ */
+int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
+                      struct bnx2x_vlan_mac_obj *obj, bool set,
+                      int mac_type, unsigned long *ramrod_flags);
+/**
+ * Deletes all MACs configured for the specific MAC object.
+ *
+ * @param bp Function driver instance
+ * @param mac_obj MAC object to cleanup
+ *
+ * @return zero if all MACs were cleaned
+ */
+
+/**
+ * bnx2x_del_all_macs - delete all MACs configured for the specific MAC object
+ *
+ * @bp:                 driver handle
+ * @mac_obj:            MAC object handle
+ * @mac_type:           type of the MACs to clear (BNX2X_XXX_MAC)
+ * @wait_for_comp:      if 'true' block until completion
+ *
+ * Deletes all MACs of the specific type (e.g. ETH, UC list).
+ *
+ * Returns zero if operation has successfully completed, a positive value if the
+ * operation has been successfully scheduled and a negative - if a requested
+ * operations has failed.
+ */
+int bnx2x_del_all_macs(struct bnx2x *bp,
+                       struct bnx2x_vlan_mac_obj *mac_obj,
+                       int mac_type, bool wait_for_comp);
+
+/* Init Function API  */
+void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p);
+int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port);
+int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
+int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode);
+int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
 void bnx2x_read_mf_cfg(struct bnx2x *bp);
 
+
 /* dmae */
 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32);
 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
@@ -1472,21 +1568,10 @@ u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode);
 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
                       bool with_comp, u8 comp_type);
 
-int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port);
-int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
-int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
-u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param);
 
 void bnx2x_calc_fc_adv(struct bnx2x *bp);
 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
-                  u32 data_hi, u32 data_lo, int common);
-
-/* Clears multicast and unicast list configuration in the chip. */
-void bnx2x_invalidate_uc_list(struct bnx2x *bp);
-
-int bnx2x_wait_ramrod(struct bnx2x *bp, int state, int idx,
-                             int *state_p, int flags);
-
+                  u32 data_hi, u32 data_lo, int cmd_type);
 void bnx2x_update_coalesce(struct bnx2x *bp);
 int bnx2x_get_cur_phy_idx(struct bnx2x *bp);
 
@@ -1644,7 +1729,8 @@ static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
 
 /* must be used on a CID before placing it on a HW ring */
 #define HW_CID(bp, x)                   ((BP_PORT(bp) << 23) | \
-                                         (BP_E1HVN(bp) << 17) | (x))
+                                         (BP_E1HVN(bp) << BNX2X_SWCID_SHIFT) | \
+                                         (x))
 
 #define SP_DESC_CNT             (BCM_PAGE_SIZE / sizeof(struct eth_spe))
 #define MAX_SP_DESC_CNT                 (SP_DESC_CNT - 1)
@@ -1771,6 +1857,30 @@ static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
                   TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT))
 #define MULTI_MASK                      0x7f
 
+
+#define DEF_USB_FUNC_OFF        offsetof(struct cstorm_def_status_block_u, func)
+#define DEF_CSB_FUNC_OFF        offsetof(struct cstorm_def_status_block_c, func)
+#define DEF_XSB_FUNC_OFF        offsetof(struct xstorm_def_status_block, func)
+#define DEF_TSB_FUNC_OFF        offsetof(struct tstorm_def_status_block, func)
+
+#define DEF_USB_IGU_INDEX_OFF \
+                        offsetof(struct cstorm_def_status_block_u, igu_index)
+#define DEF_CSB_IGU_INDEX_OFF \
+                        offsetof(struct cstorm_def_status_block_c, igu_index)
+#define DEF_XSB_IGU_INDEX_OFF \
+                        offsetof(struct xstorm_def_status_block, igu_index)
+#define DEF_TSB_IGU_INDEX_OFF \
+                        offsetof(struct tstorm_def_status_block, igu_index)
+
+#define DEF_USB_SEGMENT_OFF \
+                        offsetof(struct cstorm_def_status_block_u, segment)
+#define DEF_CSB_SEGMENT_OFF \
+                        offsetof(struct cstorm_def_status_block_c, segment)
+#define DEF_XSB_SEGMENT_OFF \
+                        offsetof(struct xstorm_def_status_block, segment)
+#define DEF_TSB_SEGMENT_OFF \
+                        offsetof(struct tstorm_def_status_block, segment)
+
 #define BNX2X_SP_DSB_INDEX \
                 (&bp->def_status_blk->sp_sb.\
                                         index_values[HC_SP_INDEX_ETH_DEF_CONS])
@@ -1782,7 +1892,7 @@ static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
         } while (0)
 
 #define GET_FLAG(value, mask) \
-        (((value) &= (mask)) >> (mask##_SHIFT))
+        (((value) & (mask)) >> (mask##_SHIFT))
 
 #define GET_FIELD(value, fname) \
         (((value) & (fname##_MASK)) >> (fname##_SHIFT))
@@ -1817,14 +1927,12 @@ static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
 #define HC_SEG_ACCESS_ATTN              4
 #define HC_SEG_ACCESS_NORM              0   /*Driver decision 0-1*/
 
-#ifdef BNX2X_MAIN
-#define BNX2X_EXTERN
-#else
-#define BNX2X_EXTERN extern
-#endif
-
-BNX2X_EXTERN int load_count[2][3]; /* per path: 0-common, 1-port0, 2-port1 */
-
-extern void bnx2x_set_ethtool_ops(struct net_device *netdev);
+static const u32 dmae_reg_go_c[] = {
+        DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3,
+        DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7,
+        DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11,
+        DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15
+};
 
+void bnx2x_set_ethtool_ops(struct net_device *netdev);
 #endif /* bnx2x.h */