diff options
author | Florian Fainelli <florian@openwrt.org> | 2010-09-08 07:11:25 -0400 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2010-09-10 00:36:36 -0400 |
commit | 3441592b34121a38047ed6680f0ed9b9017de9cf (patch) | |
tree | 62a590be79af628b4c70681585d99b36c28c6699 /drivers/net/au1000_eth.h | |
parent | b2abd4c033c3965ce670841dfb401f5f166222d5 (diff) |
au1000-eth: typedefs removal
Signed-off-by: Florian Fainelli <florian@openwrt.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/au1000_eth.h')
-rw-r--r-- | drivers/net/au1000_eth.h | 30 |
1 files changed, 15 insertions, 15 deletions
diff --git a/drivers/net/au1000_eth.h b/drivers/net/au1000_eth.h index d06ec008fbf1..44003e4843b8 100644 --- a/drivers/net/au1000_eth.h +++ b/drivers/net/au1000_eth.h | |||
@@ -44,34 +44,34 @@ | |||
44 | * Data Buffer Descriptor. Data buffers must be aligned on 32 byte | 44 | * Data Buffer Descriptor. Data buffers must be aligned on 32 byte |
45 | * boundary for both, receive and transmit. | 45 | * boundary for both, receive and transmit. |
46 | */ | 46 | */ |
47 | typedef struct db_dest { | 47 | struct db_dest { |
48 | struct db_dest *pnext; | 48 | struct db_dest *pnext; |
49 | volatile u32 *vaddr; | 49 | volatile u32 *vaddr; |
50 | dma_addr_t dma_addr; | 50 | dma_addr_t dma_addr; |
51 | } db_dest_t; | 51 | }; |
52 | 52 | ||
53 | /* | 53 | /* |
54 | * The transmit and receive descriptors are memory | 54 | * The transmit and receive descriptors are memory |
55 | * mapped registers. | 55 | * mapped registers. |
56 | */ | 56 | */ |
57 | typedef struct tx_dma { | 57 | struct tx_dma { |
58 | u32 status; | 58 | u32 status; |
59 | u32 buff_stat; | 59 | u32 buff_stat; |
60 | u32 len; | 60 | u32 len; |
61 | u32 pad; | 61 | u32 pad; |
62 | } tx_dma_t; | 62 | }; |
63 | 63 | ||
64 | typedef struct rx_dma { | 64 | struct rx_dma { |
65 | u32 status; | 65 | u32 status; |
66 | u32 buff_stat; | 66 | u32 buff_stat; |
67 | u32 pad[2]; | 67 | u32 pad[2]; |
68 | } rx_dma_t; | 68 | }; |
69 | 69 | ||
70 | 70 | ||
71 | /* | 71 | /* |
72 | * MAC control registers, memory mapped. | 72 | * MAC control registers, memory mapped. |
73 | */ | 73 | */ |
74 | typedef struct mac_reg { | 74 | struct mac_reg { |
75 | u32 control; | 75 | u32 control; |
76 | u32 mac_addr_high; | 76 | u32 mac_addr_high; |
77 | u32 mac_addr_low; | 77 | u32 mac_addr_low; |
@@ -82,16 +82,16 @@ typedef struct mac_reg { | |||
82 | u32 flow_control; | 82 | u32 flow_control; |
83 | u32 vlan1_tag; | 83 | u32 vlan1_tag; |
84 | u32 vlan2_tag; | 84 | u32 vlan2_tag; |
85 | } mac_reg_t; | 85 | }; |
86 | 86 | ||
87 | 87 | ||
88 | struct au1000_private { | 88 | struct au1000_private { |
89 | db_dest_t *pDBfree; | 89 | struct db_dest *pDBfree; |
90 | db_dest_t db[NUM_RX_BUFFS+NUM_TX_BUFFS]; | 90 | struct db_dest db[NUM_RX_BUFFS+NUM_TX_BUFFS]; |
91 | volatile rx_dma_t *rx_dma_ring[NUM_RX_DMA]; | 91 | volatile struct rx_dma *rx_dma_ring[NUM_RX_DMA]; |
92 | volatile tx_dma_t *tx_dma_ring[NUM_TX_DMA]; | 92 | volatile struct tx_dma *tx_dma_ring[NUM_TX_DMA]; |
93 | db_dest_t *rx_db_inuse[NUM_RX_DMA]; | 93 | struct db_dest *rx_db_inuse[NUM_RX_DMA]; |
94 | db_dest_t *tx_db_inuse[NUM_TX_DMA]; | 94 | struct db_dest *tx_db_inuse[NUM_TX_DMA]; |
95 | u32 rx_head; | 95 | u32 rx_head; |
96 | u32 tx_head; | 96 | u32 tx_head; |
97 | u32 tx_tail; | 97 | u32 tx_tail; |
@@ -118,7 +118,7 @@ struct au1000_private { | |||
118 | int phy_irq; | 118 | int phy_irq; |
119 | 119 | ||
120 | /* These variables are just for quick access to certain regs addresses. */ | 120 | /* These variables are just for quick access to certain regs addresses. */ |
121 | volatile mac_reg_t *mac; /* mac registers */ | 121 | volatile struct mac_reg *mac; /* mac registers */ |
122 | volatile u32 *enable; /* address of MAC Enable Register */ | 122 | volatile u32 *enable; /* address of MAC Enable Register */ |
123 | 123 | ||
124 | u32 vaddr; /* virtual address of rx/tx buffers */ | 124 | u32 vaddr; /* virtual address of rx/tx buffers */ |