diff options
author | Vipin Kumar <vipin.kumar@st.com> | 2012-03-14 02:17:19 -0400 |
---|---|---|
committer | David Woodhouse <David.Woodhouse@intel.com> | 2012-03-26 20:00:30 -0400 |
commit | 2a5dbead29a7c081a47133eb428440147a6d8d5a (patch) | |
tree | 75a021aeeac80fa720375a7845d27ba412d3b12f /drivers/mtd/nand | |
parent | 4774fb0a48aacfec206e6d54ecf58706f6a5320a (diff) |
mtd: nand/fsmc: Remove sparse warnings and errors
This patch removes the sparse below warnings and errors for nand/fsmc driver
/root/vipin/spear/kernel/3.3/linux-3.3/drivers/mtd/nand/fsmc_nand.c:363:31:
warning: incorrect type in initializer (different address spaces)
/root/vipin/spear/kernel/3.3/linux-3.3/drivers/mtd/nand/fsmc_nand.c:363:31:
expected struct fsmc_regs *regs
/root/vipin/spear/kernel/3.3/linux-3.3/drivers/mtd/nand/fsmc_nand.c:363:31:
got void [noderef] <asn:2>*regs_va
[...]
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Diffstat (limited to 'drivers/mtd/nand')
-rw-r--r-- | drivers/mtd/nand/fsmc_nand.c | 91 |
1 files changed, 45 insertions, 46 deletions
diff --git a/drivers/mtd/nand/fsmc_nand.c b/drivers/mtd/nand/fsmc_nand.c index d20a0c63251e..049018213090 100644 --- a/drivers/mtd/nand/fsmc_nand.c +++ b/drivers/mtd/nand/fsmc_nand.c | |||
@@ -360,28 +360,29 @@ static void fsmc_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl) | |||
360 | struct nand_chip *this = mtd->priv; | 360 | struct nand_chip *this = mtd->priv; |
361 | struct fsmc_nand_data *host = container_of(mtd, | 361 | struct fsmc_nand_data *host = container_of(mtd, |
362 | struct fsmc_nand_data, mtd); | 362 | struct fsmc_nand_data, mtd); |
363 | struct fsmc_regs *regs = host->regs_va; | 363 | void *__iomem *regs = host->regs_va; |
364 | unsigned int bank = host->bank; | 364 | unsigned int bank = host->bank; |
365 | 365 | ||
366 | if (ctrl & NAND_CTRL_CHANGE) { | 366 | if (ctrl & NAND_CTRL_CHANGE) { |
367 | u32 pc; | ||
368 | |||
367 | if (ctrl & NAND_CLE) { | 369 | if (ctrl & NAND_CLE) { |
368 | this->IO_ADDR_R = (void __iomem *)host->cmd_va; | 370 | this->IO_ADDR_R = host->cmd_va; |
369 | this->IO_ADDR_W = (void __iomem *)host->cmd_va; | 371 | this->IO_ADDR_W = host->cmd_va; |
370 | } else if (ctrl & NAND_ALE) { | 372 | } else if (ctrl & NAND_ALE) { |
371 | this->IO_ADDR_R = (void __iomem *)host->addr_va; | 373 | this->IO_ADDR_R = host->addr_va; |
372 | this->IO_ADDR_W = (void __iomem *)host->addr_va; | 374 | this->IO_ADDR_W = host->addr_va; |
373 | } else { | 375 | } else { |
374 | this->IO_ADDR_R = (void __iomem *)host->data_va; | 376 | this->IO_ADDR_R = host->data_va; |
375 | this->IO_ADDR_W = (void __iomem *)host->data_va; | 377 | this->IO_ADDR_W = host->data_va; |
376 | } | 378 | } |
377 | 379 | ||
378 | if (ctrl & NAND_NCE) { | 380 | pc = readl(FSMC_NAND_REG(regs, bank, PC)); |
379 | writel(readl(®s->bank_regs[bank].pc) | FSMC_ENABLE, | 381 | if (ctrl & NAND_NCE) |
380 | ®s->bank_regs[bank].pc); | 382 | pc |= FSMC_ENABLE; |
381 | } else { | 383 | else |
382 | writel(readl(®s->bank_regs[bank].pc) & ~FSMC_ENABLE, | 384 | pc &= ~FSMC_ENABLE; |
383 | ®s->bank_regs[bank].pc); | 385 | writel(pc, FSMC_NAND_REG(regs, bank, PC)); |
384 | } | ||
385 | } | 386 | } |
386 | 387 | ||
387 | mb(); | 388 | mb(); |
@@ -396,7 +397,7 @@ static void fsmc_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl) | |||
396 | * This routine initializes timing parameters related to NAND memory access in | 397 | * This routine initializes timing parameters related to NAND memory access in |
397 | * FSMC registers | 398 | * FSMC registers |
398 | */ | 399 | */ |
399 | static void fsmc_nand_setup(struct fsmc_regs *regs, uint32_t bank, | 400 | static void fsmc_nand_setup(void __iomem *regs, uint32_t bank, |
400 | uint32_t busw, struct fsmc_nand_timings *timings) | 401 | uint32_t busw, struct fsmc_nand_timings *timings) |
401 | { | 402 | { |
402 | uint32_t value = FSMC_DEVTYPE_NAND | FSMC_ENABLE | FSMC_WAITON; | 403 | uint32_t value = FSMC_DEVTYPE_NAND | FSMC_ENABLE | FSMC_WAITON; |
@@ -424,14 +425,14 @@ static void fsmc_nand_setup(struct fsmc_regs *regs, uint32_t bank, | |||
424 | tset = (tims->tset & FSMC_TSET_MASK) << FSMC_TSET_SHIFT; | 425 | tset = (tims->tset & FSMC_TSET_MASK) << FSMC_TSET_SHIFT; |
425 | 426 | ||
426 | if (busw) | 427 | if (busw) |
427 | writel(value | FSMC_DEVWID_16, ®s->bank_regs[bank].pc); | 428 | writel(value | FSMC_DEVWID_16, FSMC_NAND_REG(regs, bank, PC)); |
428 | else | 429 | else |
429 | writel(value | FSMC_DEVWID_8, ®s->bank_regs[bank].pc); | 430 | writel(value | FSMC_DEVWID_8, FSMC_NAND_REG(regs, bank, PC)); |
430 | 431 | ||
431 | writel(readl(®s->bank_regs[bank].pc) | tclr | tar, | 432 | writel(readl(FSMC_NAND_REG(regs, bank, PC)) | tclr | tar, |
432 | ®s->bank_regs[bank].pc); | 433 | FSMC_NAND_REG(regs, bank, PC)); |
433 | writel(thiz | thold | twait | tset, ®s->bank_regs[bank].comm); | 434 | writel(thiz | thold | twait | tset, FSMC_NAND_REG(regs, bank, COMM)); |
434 | writel(thiz | thold | twait | tset, ®s->bank_regs[bank].attrib); | 435 | writel(thiz | thold | twait | tset, FSMC_NAND_REG(regs, bank, ATTRIB)); |
435 | } | 436 | } |
436 | 437 | ||
437 | /* | 438 | /* |
@@ -441,15 +442,15 @@ static void fsmc_enable_hwecc(struct mtd_info *mtd, int mode) | |||
441 | { | 442 | { |
442 | struct fsmc_nand_data *host = container_of(mtd, | 443 | struct fsmc_nand_data *host = container_of(mtd, |
443 | struct fsmc_nand_data, mtd); | 444 | struct fsmc_nand_data, mtd); |
444 | struct fsmc_regs *regs = host->regs_va; | 445 | void __iomem *regs = host->regs_va; |
445 | uint32_t bank = host->bank; | 446 | uint32_t bank = host->bank; |
446 | 447 | ||
447 | writel(readl(®s->bank_regs[bank].pc) & ~FSMC_ECCPLEN_256, | 448 | writel(readl(FSMC_NAND_REG(regs, bank, PC)) & ~FSMC_ECCPLEN_256, |
448 | ®s->bank_regs[bank].pc); | 449 | FSMC_NAND_REG(regs, bank, PC)); |
449 | writel(readl(®s->bank_regs[bank].pc) & ~FSMC_ECCEN, | 450 | writel(readl(FSMC_NAND_REG(regs, bank, PC)) & ~FSMC_ECCEN, |
450 | ®s->bank_regs[bank].pc); | 451 | FSMC_NAND_REG(regs, bank, PC)); |
451 | writel(readl(®s->bank_regs[bank].pc) | FSMC_ECCEN, | 452 | writel(readl(FSMC_NAND_REG(regs, bank, PC)) | FSMC_ECCEN, |
452 | ®s->bank_regs[bank].pc); | 453 | FSMC_NAND_REG(regs, bank, PC)); |
453 | } | 454 | } |
454 | 455 | ||
455 | /* | 456 | /* |
@@ -462,13 +463,13 @@ static int fsmc_read_hwecc_ecc4(struct mtd_info *mtd, const uint8_t *data, | |||
462 | { | 463 | { |
463 | struct fsmc_nand_data *host = container_of(mtd, | 464 | struct fsmc_nand_data *host = container_of(mtd, |
464 | struct fsmc_nand_data, mtd); | 465 | struct fsmc_nand_data, mtd); |
465 | struct fsmc_regs *regs = host->regs_va; | 466 | void __iomem *regs = host->regs_va; |
466 | uint32_t bank = host->bank; | 467 | uint32_t bank = host->bank; |
467 | uint32_t ecc_tmp; | 468 | uint32_t ecc_tmp; |
468 | unsigned long deadline = jiffies + FSMC_BUSY_WAIT_TIMEOUT; | 469 | unsigned long deadline = jiffies + FSMC_BUSY_WAIT_TIMEOUT; |
469 | 470 | ||
470 | do { | 471 | do { |
471 | if (readl(®s->bank_regs[bank].sts) & FSMC_CODE_RDY) | 472 | if (readl(FSMC_NAND_REG(regs, bank, STS)) & FSMC_CODE_RDY) |
472 | break; | 473 | break; |
473 | else | 474 | else |
474 | cond_resched(); | 475 | cond_resched(); |
@@ -479,25 +480,25 @@ static int fsmc_read_hwecc_ecc4(struct mtd_info *mtd, const uint8_t *data, | |||
479 | return -ETIMEDOUT; | 480 | return -ETIMEDOUT; |
480 | } | 481 | } |
481 | 482 | ||
482 | ecc_tmp = readl(®s->bank_regs[bank].ecc1); | 483 | ecc_tmp = readl(FSMC_NAND_REG(regs, bank, ECC1)); |
483 | ecc[0] = (uint8_t) (ecc_tmp >> 0); | 484 | ecc[0] = (uint8_t) (ecc_tmp >> 0); |
484 | ecc[1] = (uint8_t) (ecc_tmp >> 8); | 485 | ecc[1] = (uint8_t) (ecc_tmp >> 8); |
485 | ecc[2] = (uint8_t) (ecc_tmp >> 16); | 486 | ecc[2] = (uint8_t) (ecc_tmp >> 16); |
486 | ecc[3] = (uint8_t) (ecc_tmp >> 24); | 487 | ecc[3] = (uint8_t) (ecc_tmp >> 24); |
487 | 488 | ||
488 | ecc_tmp = readl(®s->bank_regs[bank].ecc2); | 489 | ecc_tmp = readl(FSMC_NAND_REG(regs, bank, ECC2)); |
489 | ecc[4] = (uint8_t) (ecc_tmp >> 0); | 490 | ecc[4] = (uint8_t) (ecc_tmp >> 0); |
490 | ecc[5] = (uint8_t) (ecc_tmp >> 8); | 491 | ecc[5] = (uint8_t) (ecc_tmp >> 8); |
491 | ecc[6] = (uint8_t) (ecc_tmp >> 16); | 492 | ecc[6] = (uint8_t) (ecc_tmp >> 16); |
492 | ecc[7] = (uint8_t) (ecc_tmp >> 24); | 493 | ecc[7] = (uint8_t) (ecc_tmp >> 24); |
493 | 494 | ||
494 | ecc_tmp = readl(®s->bank_regs[bank].ecc3); | 495 | ecc_tmp = readl(FSMC_NAND_REG(regs, bank, ECC3)); |
495 | ecc[8] = (uint8_t) (ecc_tmp >> 0); | 496 | ecc[8] = (uint8_t) (ecc_tmp >> 0); |
496 | ecc[9] = (uint8_t) (ecc_tmp >> 8); | 497 | ecc[9] = (uint8_t) (ecc_tmp >> 8); |
497 | ecc[10] = (uint8_t) (ecc_tmp >> 16); | 498 | ecc[10] = (uint8_t) (ecc_tmp >> 16); |
498 | ecc[11] = (uint8_t) (ecc_tmp >> 24); | 499 | ecc[11] = (uint8_t) (ecc_tmp >> 24); |
499 | 500 | ||
500 | ecc_tmp = readl(®s->bank_regs[bank].sts); | 501 | ecc_tmp = readl(FSMC_NAND_REG(regs, bank, STS)); |
501 | ecc[12] = (uint8_t) (ecc_tmp >> 16); | 502 | ecc[12] = (uint8_t) (ecc_tmp >> 16); |
502 | 503 | ||
503 | return 0; | 504 | return 0; |
@@ -513,11 +514,11 @@ static int fsmc_read_hwecc_ecc1(struct mtd_info *mtd, const uint8_t *data, | |||
513 | { | 514 | { |
514 | struct fsmc_nand_data *host = container_of(mtd, | 515 | struct fsmc_nand_data *host = container_of(mtd, |
515 | struct fsmc_nand_data, mtd); | 516 | struct fsmc_nand_data, mtd); |
516 | struct fsmc_regs *regs = host->regs_va; | 517 | void __iomem *regs = host->regs_va; |
517 | uint32_t bank = host->bank; | 518 | uint32_t bank = host->bank; |
518 | uint32_t ecc_tmp; | 519 | uint32_t ecc_tmp; |
519 | 520 | ||
520 | ecc_tmp = readl(®s->bank_regs[bank].ecc1); | 521 | ecc_tmp = readl(FSMC_NAND_REG(regs, bank, ECC1)); |
521 | ecc[0] = (uint8_t) (ecc_tmp >> 0); | 522 | ecc[0] = (uint8_t) (ecc_tmp >> 0); |
522 | ecc[1] = (uint8_t) (ecc_tmp >> 8); | 523 | ecc[1] = (uint8_t) (ecc_tmp >> 8); |
523 | ecc[2] = (uint8_t) (ecc_tmp >> 16); | 524 | ecc[2] = (uint8_t) (ecc_tmp >> 16); |
@@ -771,13 +772,13 @@ static int fsmc_bch8_correct_data(struct mtd_info *mtd, uint8_t *dat, | |||
771 | struct fsmc_nand_data *host = container_of(mtd, | 772 | struct fsmc_nand_data *host = container_of(mtd, |
772 | struct fsmc_nand_data, mtd); | 773 | struct fsmc_nand_data, mtd); |
773 | struct nand_chip *chip = mtd->priv; | 774 | struct nand_chip *chip = mtd->priv; |
774 | struct fsmc_regs *regs = host->regs_va; | 775 | void __iomem *regs = host->regs_va; |
775 | unsigned int bank = host->bank; | 776 | unsigned int bank = host->bank; |
776 | uint32_t err_idx[8]; | 777 | uint32_t err_idx[8]; |
777 | uint32_t num_err, i; | 778 | uint32_t num_err, i; |
778 | uint32_t ecc1, ecc2, ecc3, ecc4; | 779 | uint32_t ecc1, ecc2, ecc3, ecc4; |
779 | 780 | ||
780 | num_err = (readl(®s->bank_regs[bank].sts) >> 10) & 0xF; | 781 | num_err = (readl(FSMC_NAND_REG(regs, bank, STS)) >> 10) & 0xF; |
781 | 782 | ||
782 | /* no bit flipping */ | 783 | /* no bit flipping */ |
783 | if (likely(num_err == 0)) | 784 | if (likely(num_err == 0)) |
@@ -820,10 +821,10 @@ static int fsmc_bch8_correct_data(struct mtd_info *mtd, uint8_t *dat, | |||
820 | * uint64_t array and error offset indexes are populated in err_idx | 821 | * uint64_t array and error offset indexes are populated in err_idx |
821 | * array | 822 | * array |
822 | */ | 823 | */ |
823 | ecc1 = readl(®s->bank_regs[bank].ecc1); | 824 | ecc1 = readl(FSMC_NAND_REG(regs, bank, ECC1)); |
824 | ecc2 = readl(®s->bank_regs[bank].ecc2); | 825 | ecc2 = readl(FSMC_NAND_REG(regs, bank, ECC2)); |
825 | ecc3 = readl(®s->bank_regs[bank].ecc3); | 826 | ecc3 = readl(FSMC_NAND_REG(regs, bank, ECC3)); |
826 | ecc4 = readl(®s->bank_regs[bank].sts); | 827 | ecc4 = readl(FSMC_NAND_REG(regs, bank, STS)); |
827 | 828 | ||
828 | err_idx[0] = (ecc1 >> 0) & 0x1FFF; | 829 | err_idx[0] = (ecc1 >> 0) & 0x1FFF; |
829 | err_idx[1] = (ecc1 >> 13) & 0x1FFF; | 830 | err_idx[1] = (ecc1 >> 13) & 0x1FFF; |
@@ -863,7 +864,6 @@ static int __init fsmc_nand_probe(struct platform_device *pdev) | |||
863 | struct fsmc_nand_data *host; | 864 | struct fsmc_nand_data *host; |
864 | struct mtd_info *mtd; | 865 | struct mtd_info *mtd; |
865 | struct nand_chip *nand; | 866 | struct nand_chip *nand; |
866 | struct fsmc_regs *regs; | ||
867 | struct resource *res; | 867 | struct resource *res; |
868 | dma_cap_mask_t mask; | 868 | dma_cap_mask_t mask; |
869 | int ret = 0; | 869 | int ret = 0; |
@@ -976,8 +976,6 @@ static int __init fsmc_nand_probe(struct platform_device *pdev) | |||
976 | if (host->mode == USE_DMA_ACCESS) | 976 | if (host->mode == USE_DMA_ACCESS) |
977 | init_completion(&host->dma_access_complete); | 977 | init_completion(&host->dma_access_complete); |
978 | 978 | ||
979 | regs = host->regs_va; | ||
980 | |||
981 | /* Link all private pointers */ | 979 | /* Link all private pointers */ |
982 | mtd = &host->mtd; | 980 | mtd = &host->mtd; |
983 | nand = &host->nand; | 981 | nand = &host->nand; |
@@ -1027,7 +1025,8 @@ static int __init fsmc_nand_probe(struct platform_device *pdev) | |||
1027 | break; | 1025 | break; |
1028 | } | 1026 | } |
1029 | 1027 | ||
1030 | fsmc_nand_setup(regs, host->bank, nand->options & NAND_BUSWIDTH_16, | 1028 | fsmc_nand_setup(host->regs_va, host->bank, |
1029 | nand->options & NAND_BUSWIDTH_16, | ||
1031 | host->dev_timings); | 1030 | host->dev_timings); |
1032 | 1031 | ||
1033 | if (AMBA_REV_BITS(host->pid) >= 8) { | 1032 | if (AMBA_REV_BITS(host->pid) >= 8) { |