diff options
author | Sachin Kamat <sachin.kamat@linaro.org> | 2012-07-16 06:32:25 -0400 |
---|---|---|
committer | David Woodhouse <David.Woodhouse@intel.com> | 2012-09-29 09:56:12 -0400 |
commit | a68c5ec85685a8eb7a93a0577f91c5e0952df39e (patch) | |
tree | d6e143078e17da946603ec19203cc1b2d7307076 /drivers/mtd/nand/s3c2410.c | |
parent | d2a89be8e7cedbc7aba7f0265459e75e6627614c (diff) |
mtd: s3c2410: Do not initialise statics to 0 or NULL
Fixes the following checkpatch errors:
ERROR: do not initialise statics to 0 or NULL
+static int hardware_ecc = 0;
ERROR: do not initialise statics to 0 or NULL
+static const int clock_stop = 0;
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Diffstat (limited to 'drivers/mtd/nand/s3c2410.c')
-rw-r--r-- | drivers/mtd/nand/s3c2410.c | 64 |
1 files changed, 27 insertions, 37 deletions
diff --git a/drivers/mtd/nand/s3c2410.c b/drivers/mtd/nand/s3c2410.c index f9bbf55f4b0f..38cecc9620e4 100644 --- a/drivers/mtd/nand/s3c2410.c +++ b/drivers/mtd/nand/s3c2410.c | |||
@@ -49,19 +49,6 @@ | |||
49 | #include <plat/regs-nand.h> | 49 | #include <plat/regs-nand.h> |
50 | #include <plat/nand.h> | 50 | #include <plat/nand.h> |
51 | 51 | ||
52 | #ifdef CONFIG_MTD_NAND_S3C2410_HWECC | ||
53 | static int hardware_ecc = 1; | ||
54 | #else | ||
55 | static int hardware_ecc = 0; | ||
56 | #endif | ||
57 | |||
58 | #ifdef CONFIG_MTD_NAND_S3C2410_CLKSTOP | ||
59 | static const int clock_stop = 1; | ||
60 | #else | ||
61 | static const int clock_stop = 0; | ||
62 | #endif | ||
63 | |||
64 | |||
65 | /* new oob placement block for use with hardware ecc generation | 52 | /* new oob placement block for use with hardware ecc generation |
66 | */ | 53 | */ |
67 | 54 | ||
@@ -170,7 +157,11 @@ static struct s3c2410_platform_nand *to_nand_plat(struct platform_device *dev) | |||
170 | 157 | ||
171 | static inline int allow_clk_suspend(struct s3c2410_nand_info *info) | 158 | static inline int allow_clk_suspend(struct s3c2410_nand_info *info) |
172 | { | 159 | { |
173 | return clock_stop; | 160 | #ifdef CONFIG_MTD_NAND_S3C2410_CLKSTOP |
161 | return 1; | ||
162 | #else | ||
163 | return 0; | ||
164 | #endif | ||
174 | } | 165 | } |
175 | 166 | ||
176 | /** | 167 | /** |
@@ -821,32 +812,31 @@ static void s3c2410_nand_init_chip(struct s3c2410_nand_info *info, | |||
821 | nmtd->mtd.owner = THIS_MODULE; | 812 | nmtd->mtd.owner = THIS_MODULE; |
822 | nmtd->set = set; | 813 | nmtd->set = set; |
823 | 814 | ||
824 | if (hardware_ecc) { | 815 | #ifdef CONFIG_MTD_NAND_S3C2410_HWECC |
816 | chip->ecc.calculate = s3c2410_nand_calculate_ecc; | ||
817 | chip->ecc.correct = s3c2410_nand_correct_data; | ||
818 | chip->ecc.mode = NAND_ECC_HW; | ||
819 | chip->ecc.strength = 1; | ||
820 | |||
821 | switch (info->cpu_type) { | ||
822 | case TYPE_S3C2410: | ||
823 | chip->ecc.hwctl = s3c2410_nand_enable_hwecc; | ||
825 | chip->ecc.calculate = s3c2410_nand_calculate_ecc; | 824 | chip->ecc.calculate = s3c2410_nand_calculate_ecc; |
826 | chip->ecc.correct = s3c2410_nand_correct_data; | 825 | break; |
827 | chip->ecc.mode = NAND_ECC_HW; | ||
828 | chip->ecc.strength = 1; | ||
829 | |||
830 | switch (info->cpu_type) { | ||
831 | case TYPE_S3C2410: | ||
832 | chip->ecc.hwctl = s3c2410_nand_enable_hwecc; | ||
833 | chip->ecc.calculate = s3c2410_nand_calculate_ecc; | ||
834 | break; | ||
835 | |||
836 | case TYPE_S3C2412: | ||
837 | chip->ecc.hwctl = s3c2412_nand_enable_hwecc; | ||
838 | chip->ecc.calculate = s3c2412_nand_calculate_ecc; | ||
839 | break; | ||
840 | |||
841 | case TYPE_S3C2440: | ||
842 | chip->ecc.hwctl = s3c2440_nand_enable_hwecc; | ||
843 | chip->ecc.calculate = s3c2440_nand_calculate_ecc; | ||
844 | break; | ||
845 | 826 | ||
846 | } | 827 | case TYPE_S3C2412: |
847 | } else { | 828 | chip->ecc.hwctl = s3c2412_nand_enable_hwecc; |
848 | chip->ecc.mode = NAND_ECC_SOFT; | 829 | chip->ecc.calculate = s3c2412_nand_calculate_ecc; |
830 | break; | ||
831 | |||
832 | case TYPE_S3C2440: | ||
833 | chip->ecc.hwctl = s3c2440_nand_enable_hwecc; | ||
834 | chip->ecc.calculate = s3c2440_nand_calculate_ecc; | ||
835 | break; | ||
849 | } | 836 | } |
837 | #else | ||
838 | chip->ecc.mode = NAND_ECC_SOFT; | ||
839 | #endif | ||
850 | 840 | ||
851 | if (set->ecc_layout != NULL) | 841 | if (set->ecc_layout != NULL) |
852 | chip->ecc.layout = set->ecc_layout; | 842 | chip->ecc.layout = set->ecc_layout; |