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author | Linus Torvalds <torvalds@linux-foundation.org> | 2010-10-25 16:46:56 -0400 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2010-10-25 16:46:56 -0400 |
commit | 7b6181e06841f5ad15c4ff708b967b4db65a64de (patch) | |
tree | bdfcf5b74b692f76581156e452d268b64c795200 /drivers/mmc | |
parent | 72e58063d63c5f0a7bf65312f1e3a5ed9bb5c2ff (diff) | |
parent | bc487fb341af05120bccb9f59ce76302391dcc77 (diff) |
Merge branch 'omap-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6
* 'omap-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6: (163 commits)
omap: complete removal of machine_desc.io_pg_offst and .phys_io
omap: UART: fix wakeup registers for OMAP24xx UART2
omap: Fix spotty MMC voltages
ASoC: OMAP4: MCPDM: Remove unnecessary include of plat/control.h
serial: omap-serial: fix signess error
OMAP3: DMA: Errata i541: sDMA FIFO draining does not finish
omap: dma: Fix buffering disable bit setting for omap24xx
omap: serial: Fix the boot-up crash/reboot without CONFIG_PM
OMAP3: PM: fix scratchpad memory accesses for off-mode
omap4: pandaboard: enable the ehci port on pandaboard
omap4: pandaboard: Fix the init if CONFIG_MMC_OMAP_HS is not set
omap4: pandaboard: remove unused hsmmc definition
OMAP: McBSP: Remove null omap44xx ops comment
OMAP: McBSP: Swap CLKS source definition
OMAP: McBSP: Fix CLKR and FSR signal muxing
OMAP2+: clock: reduce the amount of standard debugging while disabling unused clocks
OMAP: control: move plat-omap/control.h to mach-omap2/control.h
OMAP: split plat-omap/common.c
OMAP: McBSP: implement functional clock switching via clock framework
OMAP: McBSP: implement McBSP CLKR and FSR signal muxing via mach-omap2/mcbsp.c
...
Fixed up trivial conflicts in arch/arm/mach-omap2/
{board-zoom-peripherals.c,devices.c} as per Tony
Diffstat (limited to 'drivers/mmc')
-rw-r--r-- | drivers/mmc/host/omap_hsmmc.c | 43 |
1 files changed, 27 insertions, 16 deletions
diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c index 4526d2791f29..4693e62145a6 100644 --- a/drivers/mmc/host/omap_hsmmc.c +++ b/drivers/mmc/host/omap_hsmmc.c | |||
@@ -364,6 +364,7 @@ static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host) | |||
364 | { | 364 | { |
365 | struct regulator *reg; | 365 | struct regulator *reg; |
366 | int ret = 0; | 366 | int ret = 0; |
367 | int ocr_value = 0; | ||
367 | 368 | ||
368 | switch (host->id) { | 369 | switch (host->id) { |
369 | case OMAP_MMC1_DEVID: | 370 | case OMAP_MMC1_DEVID: |
@@ -396,6 +397,17 @@ static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host) | |||
396 | } | 397 | } |
397 | } else { | 398 | } else { |
398 | host->vcc = reg; | 399 | host->vcc = reg; |
400 | ocr_value = mmc_regulator_get_ocrmask(reg); | ||
401 | if (!mmc_slot(host).ocr_mask) { | ||
402 | mmc_slot(host).ocr_mask = ocr_value; | ||
403 | } else { | ||
404 | if (!(mmc_slot(host).ocr_mask & ocr_value)) { | ||
405 | pr_err("MMC%d ocrmask %x is not supported\n", | ||
406 | host->id, mmc_slot(host).ocr_mask); | ||
407 | mmc_slot(host).ocr_mask = 0; | ||
408 | return -EINVAL; | ||
409 | } | ||
410 | } | ||
399 | mmc_slot(host).ocr_mask = mmc_regulator_get_ocrmask(reg); | 411 | mmc_slot(host).ocr_mask = mmc_regulator_get_ocrmask(reg); |
400 | 412 | ||
401 | /* Allow an aux regulator */ | 413 | /* Allow an aux regulator */ |
@@ -982,6 +994,17 @@ static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host, | |||
982 | OMAP_HSMMC_WRITE(host->base, SYSCTL, | 994 | OMAP_HSMMC_WRITE(host->base, SYSCTL, |
983 | OMAP_HSMMC_READ(host->base, SYSCTL) | bit); | 995 | OMAP_HSMMC_READ(host->base, SYSCTL) | bit); |
984 | 996 | ||
997 | /* | ||
998 | * OMAP4 ES2 and greater has an updated reset logic. | ||
999 | * Monitor a 0->1 transition first | ||
1000 | */ | ||
1001 | if (mmc_slot(host).features & HSMMC_HAS_UPDATED_RESET) { | ||
1002 | while ((!(OMAP_HSMMC_READ(host, SYSCTL) & bit)) | ||
1003 | && (i++ < limit)) | ||
1004 | cpu_relax(); | ||
1005 | } | ||
1006 | i = 0; | ||
1007 | |||
985 | while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) && | 1008 | while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) && |
986 | (i++ < limit)) | 1009 | (i++ < limit)) |
987 | cpu_relax(); | 1010 | cpu_relax(); |
@@ -2003,6 +2026,8 @@ static int __init omap_hsmmc_probe(struct platform_device *pdev) | |||
2003 | if (res == NULL || irq < 0) | 2026 | if (res == NULL || irq < 0) |
2004 | return -ENXIO; | 2027 | return -ENXIO; |
2005 | 2028 | ||
2029 | res->start += pdata->reg_offset; | ||
2030 | res->end += pdata->reg_offset; | ||
2006 | res = request_mem_region(res->start, res->end - res->start + 1, | 2031 | res = request_mem_region(res->start, res->end - res->start + 1, |
2007 | pdev->name); | 2032 | pdev->name); |
2008 | if (res == NULL) | 2033 | if (res == NULL) |
@@ -2116,23 +2141,9 @@ static int __init omap_hsmmc_probe(struct platform_device *pdev) | |||
2116 | mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | | 2141 | mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | |
2117 | MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE; | 2142 | MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE; |
2118 | 2143 | ||
2119 | switch (mmc_slot(host).wires) { | 2144 | mmc->caps |= mmc_slot(host).caps; |
2120 | case 8: | 2145 | if (mmc->caps & MMC_CAP_8_BIT_DATA) |
2121 | mmc->caps |= MMC_CAP_8_BIT_DATA; | ||
2122 | /* Fall through */ | ||
2123 | case 4: | ||
2124 | mmc->caps |= MMC_CAP_4_BIT_DATA; | 2146 | mmc->caps |= MMC_CAP_4_BIT_DATA; |
2125 | break; | ||
2126 | case 1: | ||
2127 | /* Nothing to crib here */ | ||
2128 | case 0: | ||
2129 | /* Assuming nothing was given by board, Core use's 1-Bit */ | ||
2130 | break; | ||
2131 | default: | ||
2132 | /* Completely unexpected.. Core goes with 1-Bit Width */ | ||
2133 | dev_crit(mmc_dev(host->mmc), "Invalid width %d\n used!" | ||
2134 | "using 1 instead\n", mmc_slot(host).wires); | ||
2135 | } | ||
2136 | 2147 | ||
2137 | if (mmc_slot(host).nonremovable) | 2148 | if (mmc_slot(host).nonremovable) |
2138 | mmc->caps |= MMC_CAP_NONREMOVABLE; | 2149 | mmc->caps |= MMC_CAP_NONREMOVABLE; |