diff options
author | Joerg Roedel <joerg.roedel@amd.com> | 2011-11-09 06:06:03 -0500 |
---|---|---|
committer | Joerg Roedel <joerg.roedel@amd.com> | 2011-12-12 08:54:23 -0500 |
commit | ee6c28684585a64fd79c5a56e849af58ebdc5948 (patch) | |
tree | c58aea90ae017d89a53833097b0ecd95a072c8ec /drivers/iommu/amd_iommu.c | |
parent | dc47ce90c3a822cd7c9e9339fe4d5f61dcb26b50 (diff) |
iommu/amd: Convert dev_table_entry to u64
Convert the contents of 'struct dev_table_entry' to u64 to
allow updating the DTE wit 64bit writes as required by the
spec.
Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
Diffstat (limited to 'drivers/iommu/amd_iommu.c')
-rw-r--r-- | drivers/iommu/amd_iommu.c | 18 |
1 files changed, 10 insertions, 8 deletions
diff --git a/drivers/iommu/amd_iommu.c b/drivers/iommu/amd_iommu.c index 4ee277a8521a..661e2bb4ac15 100644 --- a/drivers/iommu/amd_iommu.c +++ b/drivers/iommu/amd_iommu.c | |||
@@ -365,8 +365,8 @@ static void dump_dte_entry(u16 devid) | |||
365 | { | 365 | { |
366 | int i; | 366 | int i; |
367 | 367 | ||
368 | for (i = 0; i < 8; ++i) | 368 | for (i = 0; i < 4; ++i) |
369 | pr_err("AMD-Vi: DTE[%d]: %08x\n", i, | 369 | pr_err("AMD-Vi: DTE[%d]: %016llx\n", i, |
370 | amd_iommu_dev_table[devid].data[i]); | 370 | amd_iommu_dev_table[devid].data[i]); |
371 | } | 371 | } |
372 | 372 | ||
@@ -1583,19 +1583,22 @@ static bool dma_ops_domain(struct protection_domain *domain) | |||
1583 | static void set_dte_entry(u16 devid, struct protection_domain *domain, bool ats) | 1583 | static void set_dte_entry(u16 devid, struct protection_domain *domain, bool ats) |
1584 | { | 1584 | { |
1585 | u64 pte_root = virt_to_phys(domain->pt_root); | 1585 | u64 pte_root = virt_to_phys(domain->pt_root); |
1586 | u32 flags = 0; | 1586 | u64 flags = 0; |
1587 | 1587 | ||
1588 | pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK) | 1588 | pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK) |
1589 | << DEV_ENTRY_MODE_SHIFT; | 1589 | << DEV_ENTRY_MODE_SHIFT; |
1590 | pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV; | 1590 | pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV; |
1591 | 1591 | ||
1592 | flags = amd_iommu_dev_table[devid].data[1]; | ||
1593 | |||
1592 | if (ats) | 1594 | if (ats) |
1593 | flags |= DTE_FLAG_IOTLB; | 1595 | flags |= DTE_FLAG_IOTLB; |
1594 | 1596 | ||
1595 | amd_iommu_dev_table[devid].data[3] |= flags; | 1597 | flags &= ~(0xffffUL); |
1596 | amd_iommu_dev_table[devid].data[2] = domain->id; | 1598 | flags |= domain->id; |
1597 | amd_iommu_dev_table[devid].data[1] = upper_32_bits(pte_root); | 1599 | |
1598 | amd_iommu_dev_table[devid].data[0] = lower_32_bits(pte_root); | 1600 | amd_iommu_dev_table[devid].data[1] = flags; |
1601 | amd_iommu_dev_table[devid].data[0] = pte_root; | ||
1599 | } | 1602 | } |
1600 | 1603 | ||
1601 | static void clear_dte_entry(u16 devid) | 1604 | static void clear_dte_entry(u16 devid) |
@@ -1603,7 +1606,6 @@ static void clear_dte_entry(u16 devid) | |||
1603 | /* remove entry from the device table seen by the hardware */ | 1606 | /* remove entry from the device table seen by the hardware */ |
1604 | amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV; | 1607 | amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV; |
1605 | amd_iommu_dev_table[devid].data[1] = 0; | 1608 | amd_iommu_dev_table[devid].data[1] = 0; |
1606 | amd_iommu_dev_table[devid].data[2] = 0; | ||
1607 | 1609 | ||
1608 | amd_iommu_apply_erratum_63(devid); | 1610 | amd_iommu_apply_erratum_63(devid); |
1609 | } | 1611 | } |