diff options
author | Or Gerlitz <ogerlitz@mellanox.com> | 2011-10-10 04:54:42 -0400 |
---|---|---|
committer | Roland Dreier <roland@purestorage.com> | 2011-10-31 14:57:51 -0400 |
commit | 80a2dcd8d05c11d42f4e606d7a5f3eaa2794ab34 (patch) | |
tree | 4407b7481a5382bc10e5f91c77dec3b98f7f8b9c /drivers/infiniband | |
parent | bcacb897569f0e7aab7643b22567d8de22ef9dfc (diff) |
IB/mlx4: Don't set VLAN in IBoE WQEs' control segment
There's no need to set the vlan-related fields in an IBoE send WQE
control segment:
- the vlan to be used by a UD QP is set in the datagram segment.
- for GSI (CM) QP, all the headers down to 8021q and MAC are built by
the software anyway.
Signed-off-by: Or Gerlitz <ogerlitz@mellanox.com>
Signed-off-by: Roland Dreier <roland@purestorage.com>
Diffstat (limited to 'drivers/infiniband')
-rw-r--r-- | drivers/infiniband/hw/mlx4/qp.c | 11 |
1 files changed, 2 insertions, 9 deletions
diff --git a/drivers/infiniband/hw/mlx4/qp.c b/drivers/infiniband/hw/mlx4/qp.c index 3a91d9d8dc51..819b1a535b55 100644 --- a/drivers/infiniband/hw/mlx4/qp.c +++ b/drivers/infiniband/hw/mlx4/qp.c | |||
@@ -1547,14 +1547,13 @@ static void set_masked_atomic_seg(struct mlx4_wqe_masked_atomic_seg *aseg, | |||
1547 | } | 1547 | } |
1548 | 1548 | ||
1549 | static void set_datagram_seg(struct mlx4_wqe_datagram_seg *dseg, | 1549 | static void set_datagram_seg(struct mlx4_wqe_datagram_seg *dseg, |
1550 | struct ib_send_wr *wr, __be16 *vlan) | 1550 | struct ib_send_wr *wr) |
1551 | { | 1551 | { |
1552 | memcpy(dseg->av, &to_mah(wr->wr.ud.ah)->av, sizeof (struct mlx4_av)); | 1552 | memcpy(dseg->av, &to_mah(wr->wr.ud.ah)->av, sizeof (struct mlx4_av)); |
1553 | dseg->dqpn = cpu_to_be32(wr->wr.ud.remote_qpn); | 1553 | dseg->dqpn = cpu_to_be32(wr->wr.ud.remote_qpn); |
1554 | dseg->qkey = cpu_to_be32(wr->wr.ud.remote_qkey); | 1554 | dseg->qkey = cpu_to_be32(wr->wr.ud.remote_qkey); |
1555 | dseg->vlan = to_mah(wr->wr.ud.ah)->av.eth.vlan; | 1555 | dseg->vlan = to_mah(wr->wr.ud.ah)->av.eth.vlan; |
1556 | memcpy(dseg->mac, to_mah(wr->wr.ud.ah)->av.eth.mac, 6); | 1556 | memcpy(dseg->mac, to_mah(wr->wr.ud.ah)->av.eth.mac, 6); |
1557 | *vlan = dseg->vlan; | ||
1558 | } | 1557 | } |
1559 | 1558 | ||
1560 | static void set_mlx_icrc_seg(void *dseg) | 1559 | static void set_mlx_icrc_seg(void *dseg) |
@@ -1657,7 +1656,6 @@ int mlx4_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, | |||
1657 | __be32 uninitialized_var(lso_hdr_sz); | 1656 | __be32 uninitialized_var(lso_hdr_sz); |
1658 | __be32 blh; | 1657 | __be32 blh; |
1659 | int i; | 1658 | int i; |
1660 | __be16 vlan = cpu_to_be16(0xffff); | ||
1661 | 1659 | ||
1662 | spin_lock_irqsave(&qp->sq.lock, flags); | 1660 | spin_lock_irqsave(&qp->sq.lock, flags); |
1663 | 1661 | ||
@@ -1761,7 +1759,7 @@ int mlx4_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, | |||
1761 | break; | 1759 | break; |
1762 | 1760 | ||
1763 | case IB_QPT_UD: | 1761 | case IB_QPT_UD: |
1764 | set_datagram_seg(wqe, wr, &vlan); | 1762 | set_datagram_seg(wqe, wr); |
1765 | wqe += sizeof (struct mlx4_wqe_datagram_seg); | 1763 | wqe += sizeof (struct mlx4_wqe_datagram_seg); |
1766 | size += sizeof (struct mlx4_wqe_datagram_seg) / 16; | 1764 | size += sizeof (struct mlx4_wqe_datagram_seg) / 16; |
1767 | 1765 | ||
@@ -1824,11 +1822,6 @@ int mlx4_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, | |||
1824 | ctrl->fence_size = (wr->send_flags & IB_SEND_FENCE ? | 1822 | ctrl->fence_size = (wr->send_flags & IB_SEND_FENCE ? |
1825 | MLX4_WQE_CTRL_FENCE : 0) | size; | 1823 | MLX4_WQE_CTRL_FENCE : 0) | size; |
1826 | 1824 | ||
1827 | if (be16_to_cpu(vlan) < 0x1000) { | ||
1828 | ctrl->ins_vlan = 1 << 6; | ||
1829 | ctrl->vlan_tag = vlan; | ||
1830 | } | ||
1831 | |||
1832 | /* | 1825 | /* |
1833 | * Make sure descriptor is fully written before | 1826 | * Make sure descriptor is fully written before |
1834 | * setting ownership bit (because HW can start | 1827 | * setting ownership bit (because HW can start |