diff options
author | Chien Tung <chien.tin.tung@intel.com> | 2010-02-23 12:52:10 -0500 |
---|---|---|
committer | Roland Dreier <rolandd@cisco.com> | 2010-02-25 13:40:05 -0500 |
commit | 09124e1913cf2140941f60ab4fdf8576e1e8fd8d (patch) | |
tree | cc06308101d1e3e97f31313c980f3ec78adab38f /drivers/infiniband | |
parent | 831d06cf5b036a1ed14e412e9311c5e23075ed8d (diff) |
RDMA/nes: Add support for KR device id 0x0110
Add support for KR device id 0x0110. While at it, cleanup
nes_init_phy() by splitting it into nes_init_1g_phy() and
nes_init_2025_phy().
Remove support for NES_PHY_TYPE_IRIS, which was used on an XFP board
that was only manufactured in small quantities and given out for evals
in even smaller quantities.
Signed-off-by: Chien Tung <chien.tin.tung@intel.com>
Signed-off-by: Roland Dreier <rolandd@cisco.com>
Diffstat (limited to 'drivers/infiniband')
-rw-r--r-- | drivers/infiniband/hw/nes/nes.c | 1 | ||||
-rw-r--r-- | drivers/infiniband/hw/nes/nes.h | 5 | ||||
-rw-r--r-- | drivers/infiniband/hw/nes/nes_hw.c | 396 | ||||
-rw-r--r-- | drivers/infiniband/hw/nes/nes_hw.h | 2 | ||||
-rw-r--r-- | drivers/infiniband/hw/nes/nes_nic.c | 57 |
5 files changed, 243 insertions, 218 deletions
diff --git a/drivers/infiniband/hw/nes/nes.c b/drivers/infiniband/hw/nes/nes.c index b9d09bafd6c1..4272c52e38a4 100644 --- a/drivers/infiniband/hw/nes/nes.c +++ b/drivers/infiniband/hw/nes/nes.c | |||
@@ -110,6 +110,7 @@ static unsigned int sysfs_idx_addr; | |||
110 | 110 | ||
111 | static struct pci_device_id nes_pci_table[] = { | 111 | static struct pci_device_id nes_pci_table[] = { |
112 | {PCI_VENDOR_ID_NETEFFECT, PCI_DEVICE_ID_NETEFFECT_NE020, PCI_ANY_ID, PCI_ANY_ID}, | 112 | {PCI_VENDOR_ID_NETEFFECT, PCI_DEVICE_ID_NETEFFECT_NE020, PCI_ANY_ID, PCI_ANY_ID}, |
113 | {PCI_VENDOR_ID_NETEFFECT, PCI_DEVICE_ID_NETEFFECT_NE020_KR, PCI_ANY_ID, PCI_ANY_ID}, | ||
113 | {0} | 114 | {0} |
114 | }; | 115 | }; |
115 | 116 | ||
diff --git a/drivers/infiniband/hw/nes/nes.h b/drivers/infiniband/hw/nes/nes.h index cffdac4a899f..cc78fee1dd51 100644 --- a/drivers/infiniband/hw/nes/nes.h +++ b/drivers/infiniband/hw/nes/nes.h | |||
@@ -64,8 +64,9 @@ | |||
64 | * NetEffect PCI vendor id and NE010 PCI device id. | 64 | * NetEffect PCI vendor id and NE010 PCI device id. |
65 | */ | 65 | */ |
66 | #ifndef PCI_VENDOR_ID_NETEFFECT /* not in pci.ids yet */ | 66 | #ifndef PCI_VENDOR_ID_NETEFFECT /* not in pci.ids yet */ |
67 | #define PCI_VENDOR_ID_NETEFFECT 0x1678 | 67 | #define PCI_VENDOR_ID_NETEFFECT 0x1678 |
68 | #define PCI_DEVICE_ID_NETEFFECT_NE020 0x0100 | 68 | #define PCI_DEVICE_ID_NETEFFECT_NE020 0x0100 |
69 | #define PCI_DEVICE_ID_NETEFFECT_NE020_KR 0x0110 | ||
69 | #endif | 70 | #endif |
70 | 71 | ||
71 | #define NE020_REV 4 | 72 | #define NE020_REV 4 |
diff --git a/drivers/infiniband/hw/nes/nes_hw.c b/drivers/infiniband/hw/nes/nes_hw.c index 310cc7cab396..ce7f53833577 100644 --- a/drivers/infiniband/hw/nes/nes_hw.c +++ b/drivers/infiniband/hw/nes/nes_hw.c | |||
@@ -748,16 +748,28 @@ static int nes_init_serdes(struct nes_device *nesdev, u8 hw_rev, u8 port_count, | |||
748 | 748 | ||
749 | if (hw_rev != NE020_REV) { | 749 | if (hw_rev != NE020_REV) { |
750 | /* init serdes 0 */ | 750 | /* init serdes 0 */ |
751 | if (wide_ppm_offset && (nesadapter->phy_type[0] == NES_PHY_TYPE_CX4)) | 751 | switch (nesadapter->phy_type[0]) { |
752 | nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_CDR_CONTROL0, 0x000FFFAA); | 752 | case NES_PHY_TYPE_CX4: |
753 | else | 753 | if (wide_ppm_offset) |
754 | nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_CDR_CONTROL0, 0x000FFFAA); | ||
755 | else | ||
756 | nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_CDR_CONTROL0, 0x000000FF); | ||
757 | break; | ||
758 | case NES_PHY_TYPE_KR: | ||
759 | nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_CDR_CONTROL0, 0x000000FF); | ||
760 | nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_TX_EMP0, 0x00000000); | ||
761 | break; | ||
762 | case NES_PHY_TYPE_PUMA_1G: | ||
754 | nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_CDR_CONTROL0, 0x000000FF); | 763 | nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_CDR_CONTROL0, 0x000000FF); |
755 | |||
756 | if (nesadapter->phy_type[0] == NES_PHY_TYPE_PUMA_1G) { | ||
757 | sds = nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL0); | 764 | sds = nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL0); |
758 | sds |= 0x00000100; | 765 | sds |= 0x00000100; |
759 | nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL0, sds); | 766 | nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL0, sds); |
767 | break; | ||
768 | default: | ||
769 | nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_CDR_CONTROL0, 0x000000FF); | ||
770 | break; | ||
760 | } | 771 | } |
772 | |||
761 | if (!OneG_Mode) | 773 | if (!OneG_Mode) |
762 | nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_TX_HIGHZ_LANE_MODE0, 0x11110000); | 774 | nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_TX_HIGHZ_LANE_MODE0, 0x11110000); |
763 | 775 | ||
@@ -778,6 +790,9 @@ static int nes_init_serdes(struct nes_device *nesdev, u8 hw_rev, u8 port_count, | |||
778 | if (wide_ppm_offset) | 790 | if (wide_ppm_offset) |
779 | nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_CDR_CONTROL1, 0x000FFFAA); | 791 | nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_CDR_CONTROL1, 0x000FFFAA); |
780 | break; | 792 | break; |
793 | case NES_PHY_TYPE_KR: | ||
794 | nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_TX_EMP1, 0x00000000); | ||
795 | break; | ||
781 | case NES_PHY_TYPE_PUMA_1G: | 796 | case NES_PHY_TYPE_PUMA_1G: |
782 | sds = nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL1); | 797 | sds = nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL1); |
783 | sds |= 0x000000100; | 798 | sds |= 0x000000100; |
@@ -1279,115 +1294,115 @@ int nes_destroy_cqp(struct nes_device *nesdev) | |||
1279 | 1294 | ||
1280 | 1295 | ||
1281 | /** | 1296 | /** |
1282 | * nes_init_phy | 1297 | * nes_init_1g_phy |
1283 | */ | 1298 | */ |
1284 | int nes_init_phy(struct nes_device *nesdev) | 1299 | int nes_init_1g_phy(struct nes_device *nesdev, u8 phy_type, u8 phy_index) |
1285 | { | 1300 | { |
1286 | struct nes_adapter *nesadapter = nesdev->nesadapter; | ||
1287 | u32 counter = 0; | 1301 | u32 counter = 0; |
1288 | u32 sds; | ||
1289 | u32 mac_index = nesdev->mac_index; | ||
1290 | u32 tx_config = 0; | ||
1291 | u16 phy_data; | 1302 | u16 phy_data; |
1292 | u32 temp_phy_data = 0; | 1303 | int ret = 0; |
1293 | u32 temp_phy_data2 = 0; | ||
1294 | u8 phy_type = nesadapter->phy_type[mac_index]; | ||
1295 | u8 phy_index = nesadapter->phy_index[mac_index]; | ||
1296 | |||
1297 | if ((nesadapter->OneG_Mode) && | ||
1298 | (phy_type != NES_PHY_TYPE_PUMA_1G)) { | ||
1299 | nes_debug(NES_DBG_PHY, "1G PHY, mac_index = %d.\n", mac_index); | ||
1300 | if (phy_type == NES_PHY_TYPE_1G) { | ||
1301 | tx_config = nes_read_indexed(nesdev, NES_IDX_MAC_TX_CONFIG); | ||
1302 | tx_config &= 0xFFFFFFE3; | ||
1303 | tx_config |= 0x04; | ||
1304 | nes_write_indexed(nesdev, NES_IDX_MAC_TX_CONFIG, tx_config); | ||
1305 | } | ||
1306 | |||
1307 | nes_read_1G_phy_reg(nesdev, 1, phy_index, &phy_data); | ||
1308 | nes_write_1G_phy_reg(nesdev, 23, phy_index, 0xb000); | ||
1309 | 1304 | ||
1310 | /* Reset the PHY */ | 1305 | nes_read_1G_phy_reg(nesdev, 1, phy_index, &phy_data); |
1311 | nes_write_1G_phy_reg(nesdev, 0, phy_index, 0x8000); | 1306 | nes_write_1G_phy_reg(nesdev, 23, phy_index, 0xb000); |
1312 | udelay(100); | ||
1313 | counter = 0; | ||
1314 | do { | ||
1315 | nes_read_1G_phy_reg(nesdev, 0, phy_index, &phy_data); | ||
1316 | if (counter++ > 100) | ||
1317 | break; | ||
1318 | } while (phy_data & 0x8000); | ||
1319 | 1307 | ||
1320 | /* Setting no phy loopback */ | 1308 | /* Reset the PHY */ |
1321 | phy_data &= 0xbfff; | 1309 | nes_write_1G_phy_reg(nesdev, 0, phy_index, 0x8000); |
1322 | phy_data |= 0x1140; | 1310 | udelay(100); |
1323 | nes_write_1G_phy_reg(nesdev, 0, phy_index, phy_data); | 1311 | counter = 0; |
1312 | do { | ||
1324 | nes_read_1G_phy_reg(nesdev, 0, phy_index, &phy_data); | 1313 | nes_read_1G_phy_reg(nesdev, 0, phy_index, &phy_data); |
1325 | nes_read_1G_phy_reg(nesdev, 0x17, phy_index, &phy_data); | 1314 | if (counter++ > 100) { |
1326 | nes_read_1G_phy_reg(nesdev, 0x1e, phy_index, &phy_data); | 1315 | ret = -1; |
1327 | 1316 | break; | |
1328 | /* Setting the interrupt mask */ | 1317 | } |
1329 | nes_read_1G_phy_reg(nesdev, 0x19, phy_index, &phy_data); | 1318 | } while (phy_data & 0x8000); |
1330 | nes_write_1G_phy_reg(nesdev, 0x19, phy_index, 0xffee); | 1319 | |
1331 | nes_read_1G_phy_reg(nesdev, 0x19, phy_index, &phy_data); | 1320 | /* Setting no phy loopback */ |
1321 | phy_data &= 0xbfff; | ||
1322 | phy_data |= 0x1140; | ||
1323 | nes_write_1G_phy_reg(nesdev, 0, phy_index, phy_data); | ||
1324 | nes_read_1G_phy_reg(nesdev, 0, phy_index, &phy_data); | ||
1325 | nes_read_1G_phy_reg(nesdev, 0x17, phy_index, &phy_data); | ||
1326 | nes_read_1G_phy_reg(nesdev, 0x1e, phy_index, &phy_data); | ||
1327 | |||
1328 | /* Setting the interrupt mask */ | ||
1329 | nes_read_1G_phy_reg(nesdev, 0x19, phy_index, &phy_data); | ||
1330 | nes_write_1G_phy_reg(nesdev, 0x19, phy_index, 0xffee); | ||
1331 | nes_read_1G_phy_reg(nesdev, 0x19, phy_index, &phy_data); | ||
1332 | |||
1333 | /* turning on flow control */ | ||
1334 | nes_read_1G_phy_reg(nesdev, 4, phy_index, &phy_data); | ||
1335 | nes_write_1G_phy_reg(nesdev, 4, phy_index, (phy_data & ~(0x03E0)) | 0xc00); | ||
1336 | nes_read_1G_phy_reg(nesdev, 4, phy_index, &phy_data); | ||
1337 | |||
1338 | /* Clear Half duplex */ | ||
1339 | nes_read_1G_phy_reg(nesdev, 9, phy_index, &phy_data); | ||
1340 | nes_write_1G_phy_reg(nesdev, 9, phy_index, phy_data & ~(0x0100)); | ||
1341 | nes_read_1G_phy_reg(nesdev, 9, phy_index, &phy_data); | ||
1342 | |||
1343 | nes_read_1G_phy_reg(nesdev, 0, phy_index, &phy_data); | ||
1344 | nes_write_1G_phy_reg(nesdev, 0, phy_index, phy_data | 0x0300); | ||
1345 | |||
1346 | return ret; | ||
1347 | } | ||
1332 | 1348 | ||
1333 | /* turning on flow control */ | ||
1334 | nes_read_1G_phy_reg(nesdev, 4, phy_index, &phy_data); | ||
1335 | nes_write_1G_phy_reg(nesdev, 4, phy_index, (phy_data & ~(0x03E0)) | 0xc00); | ||
1336 | nes_read_1G_phy_reg(nesdev, 4, phy_index, &phy_data); | ||
1337 | 1349 | ||
1338 | /* Clear Half duplex */ | 1350 | /** |
1339 | nes_read_1G_phy_reg(nesdev, 9, phy_index, &phy_data); | 1351 | * nes_init_2025_phy |
1340 | nes_write_1G_phy_reg(nesdev, 9, phy_index, phy_data & ~(0x0100)); | 1352 | */ |
1341 | nes_read_1G_phy_reg(nesdev, 9, phy_index, &phy_data); | 1353 | int nes_init_2025_phy(struct nes_device *nesdev, u8 phy_type, u8 phy_index) |
1354 | { | ||
1355 | u32 temp_phy_data = 0; | ||
1356 | u32 temp_phy_data2 = 0; | ||
1357 | u32 counter = 0; | ||
1358 | u32 sds; | ||
1359 | u32 mac_index = nesdev->mac_index; | ||
1360 | int ret = 0; | ||
1361 | unsigned int first_attempt = 1; | ||
1342 | 1362 | ||
1343 | nes_read_1G_phy_reg(nesdev, 0, phy_index, &phy_data); | 1363 | /* Check firmware heartbeat */ |
1344 | nes_write_1G_phy_reg(nesdev, 0, phy_index, phy_data | 0x0300); | 1364 | nes_read_10G_phy_reg(nesdev, phy_index, 0x3, 0xd7ee); |
1365 | temp_phy_data = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL); | ||
1366 | udelay(1500); | ||
1367 | nes_read_10G_phy_reg(nesdev, phy_index, 0x3, 0xd7ee); | ||
1368 | temp_phy_data2 = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL); | ||
1345 | 1369 | ||
1346 | return 0; | 1370 | if (temp_phy_data != temp_phy_data2) { |
1371 | nes_read_10G_phy_reg(nesdev, phy_index, 0x3, 0xd7fd); | ||
1372 | temp_phy_data = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL); | ||
1373 | if ((temp_phy_data & 0xff) > 0x20) | ||
1374 | return 0; | ||
1375 | printk(PFX "Reinitialize external PHY\n"); | ||
1347 | } | 1376 | } |
1348 | 1377 | ||
1349 | if ((phy_type == NES_PHY_TYPE_IRIS) || | 1378 | /* no heartbeat, configure the PHY */ |
1350 | (phy_type == NES_PHY_TYPE_ARGUS) || | 1379 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0x0000, 0x8000); |
1351 | (phy_type == NES_PHY_TYPE_SFP_D)) { | 1380 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc300, 0x0000); |
1352 | /* setup 10G MDIO operation */ | 1381 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc316, 0x000A); |
1353 | tx_config = nes_read_indexed(nesdev, NES_IDX_MAC_TX_CONFIG); | 1382 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc318, 0x0052); |
1354 | tx_config &= 0xFFFFFFE3; | ||
1355 | tx_config |= 0x15; | ||
1356 | nes_write_indexed(nesdev, NES_IDX_MAC_TX_CONFIG, tx_config); | ||
1357 | } | ||
1358 | if ((phy_type == NES_PHY_TYPE_ARGUS) || | ||
1359 | (phy_type == NES_PHY_TYPE_SFP_D)) { | ||
1360 | u32 first_time = 1; | ||
1361 | 1383 | ||
1362 | /* Check firmware heartbeat */ | 1384 | switch (phy_type) { |
1363 | nes_read_10G_phy_reg(nesdev, phy_index, 0x3, 0xd7ee); | 1385 | case NES_PHY_TYPE_ARGUS: |
1364 | temp_phy_data = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL); | 1386 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc316, 0x000A); |
1365 | udelay(1500); | 1387 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc318, 0x0052); |
1366 | nes_read_10G_phy_reg(nesdev, phy_index, 0x3, 0xd7ee); | 1388 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc302, 0x000C); |
1367 | temp_phy_data2 = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL); | 1389 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc319, 0x0008); |
1390 | nes_write_10G_phy_reg(nesdev, phy_index, 0x3, 0x0027, 0x0001); | ||
1391 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc31a, 0x0098); | ||
1392 | nes_write_10G_phy_reg(nesdev, phy_index, 0x3, 0x0026, 0x0E00); | ||
1368 | 1393 | ||
1369 | if (temp_phy_data != temp_phy_data2) { | 1394 | /* setup LEDs */ |
1370 | nes_read_10G_phy_reg(nesdev, phy_index, 0x3, 0xd7fd); | 1395 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xd006, 0x0007); |
1371 | temp_phy_data = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL); | 1396 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xd007, 0x000A); |
1372 | if ((temp_phy_data & 0xff) > 0x20) | 1397 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xd008, 0x0009); |
1373 | return 0; | 1398 | break; |
1374 | printk(PFX "Reinitializing PHY\n"); | ||
1375 | } | ||
1376 | 1399 | ||
1377 | /* no heartbeat, configure the PHY */ | 1400 | case NES_PHY_TYPE_SFP_D: |
1378 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0x0000, 0x8000); | ||
1379 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc300, 0x0000); | ||
1380 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc316, 0x000A); | 1401 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc316, 0x000A); |
1381 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc318, 0x0052); | 1402 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc318, 0x0052); |
1382 | if (phy_type == NES_PHY_TYPE_ARGUS) { | 1403 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc302, 0x0004); |
1383 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc302, 0x000C); | 1404 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc319, 0x0038); |
1384 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc319, 0x0008); | 1405 | nes_write_10G_phy_reg(nesdev, phy_index, 0x3, 0x0027, 0x0013); |
1385 | nes_write_10G_phy_reg(nesdev, phy_index, 0x3, 0x0027, 0x0001); | ||
1386 | } else { | ||
1387 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc302, 0x0004); | ||
1388 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc319, 0x0038); | ||
1389 | nes_write_10G_phy_reg(nesdev, phy_index, 0x3, 0x0027, 0x0013); | ||
1390 | } | ||
1391 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc31a, 0x0098); | 1406 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc31a, 0x0098); |
1392 | nes_write_10G_phy_reg(nesdev, phy_index, 0x3, 0x0026, 0x0E00); | 1407 | nes_write_10G_phy_reg(nesdev, phy_index, 0x3, 0x0026, 0x0E00); |
1393 | 1408 | ||
@@ -1395,71 +1410,136 @@ int nes_init_phy(struct nes_device *nesdev) | |||
1395 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xd006, 0x0007); | 1410 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xd006, 0x0007); |
1396 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xd007, 0x000A); | 1411 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xd007, 0x000A); |
1397 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xd008, 0x0009); | 1412 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xd008, 0x0009); |
1413 | break; | ||
1398 | 1414 | ||
1399 | nes_write_10G_phy_reg(nesdev, phy_index, 0x3, 0x0028, 0xA528); | 1415 | case NES_PHY_TYPE_KR: |
1416 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc316, 0x000A); | ||
1417 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc318, 0x0052); | ||
1418 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc302, 0x000C); | ||
1419 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc319, 0x0010); | ||
1420 | nes_write_10G_phy_reg(nesdev, phy_index, 0x3, 0x0027, 0x0013); | ||
1421 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc31a, 0x0080); | ||
1422 | nes_write_10G_phy_reg(nesdev, phy_index, 0x3, 0x0026, 0x0E00); | ||
1400 | 1423 | ||
1401 | /* Bring PHY out of reset */ | 1424 | /* setup LEDs */ |
1402 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc300, 0x0002); | 1425 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xd006, 0x000B); |
1426 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xd007, 0x0003); | ||
1427 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xd008, 0x0004); | ||
1403 | 1428 | ||
1404 | /* Check for heartbeat */ | 1429 | nes_write_10G_phy_reg(nesdev, phy_index, 0x3, 0x0022, 0x406D); |
1405 | counter = 0; | 1430 | nes_write_10G_phy_reg(nesdev, phy_index, 0x3, 0x0023, 0x0020); |
1406 | mdelay(690); | 1431 | break; |
1432 | } | ||
1433 | |||
1434 | nes_write_10G_phy_reg(nesdev, phy_index, 0x3, 0x0028, 0xA528); | ||
1435 | |||
1436 | /* Bring PHY out of reset */ | ||
1437 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc300, 0x0002); | ||
1438 | |||
1439 | /* Check for heartbeat */ | ||
1440 | counter = 0; | ||
1441 | mdelay(690); | ||
1442 | nes_read_10G_phy_reg(nesdev, phy_index, 0x3, 0xd7ee); | ||
1443 | temp_phy_data = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL); | ||
1444 | do { | ||
1445 | if (counter++ > 150) { | ||
1446 | printk(PFX "No PHY heartbeat\n"); | ||
1447 | break; | ||
1448 | } | ||
1449 | mdelay(1); | ||
1407 | nes_read_10G_phy_reg(nesdev, phy_index, 0x3, 0xd7ee); | 1450 | nes_read_10G_phy_reg(nesdev, phy_index, 0x3, 0xd7ee); |
1451 | temp_phy_data2 = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL); | ||
1452 | } while ((temp_phy_data2 == temp_phy_data)); | ||
1453 | |||
1454 | /* wait for tracking */ | ||
1455 | counter = 0; | ||
1456 | do { | ||
1457 | nes_read_10G_phy_reg(nesdev, phy_index, 0x3, 0xd7fd); | ||
1408 | temp_phy_data = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL); | 1458 | temp_phy_data = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL); |
1409 | do { | 1459 | if (counter++ > 300) { |
1410 | if (counter++ > 150) { | 1460 | if (((temp_phy_data & 0xff) == 0x0) && first_attempt) { |
1411 | printk(PFX "No PHY heartbeat\n"); | 1461 | first_attempt = 0; |
1462 | counter = 0; | ||
1463 | /* reset AMCC PHY and try again */ | ||
1464 | nes_write_10G_phy_reg(nesdev, phy_index, 0x3, 0xe854, 0x00c0); | ||
1465 | nes_write_10G_phy_reg(nesdev, phy_index, 0x3, 0xe854, 0x0040); | ||
1466 | continue; | ||
1467 | } else { | ||
1468 | ret = 1; | ||
1412 | break; | 1469 | break; |
1413 | } | 1470 | } |
1414 | mdelay(1); | 1471 | } |
1415 | nes_read_10G_phy_reg(nesdev, phy_index, 0x3, 0xd7ee); | 1472 | mdelay(10); |
1416 | temp_phy_data2 = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL); | 1473 | } while ((temp_phy_data & 0xff) < 0x30); |
1417 | } while ((temp_phy_data2 == temp_phy_data)); | 1474 | |
1418 | 1475 | /* setup signal integrity */ | |
1419 | /* wait for tracking */ | 1476 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xd003, 0x0000); |
1420 | counter = 0; | 1477 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xF00D, 0x00FE); |
1421 | do { | 1478 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xF00E, 0x0032); |
1422 | nes_read_10G_phy_reg(nesdev, phy_index, 0x3, 0xd7fd); | 1479 | if (phy_type == NES_PHY_TYPE_KR) { |
1423 | temp_phy_data = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL); | 1480 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xF00F, 0x000C); |
1424 | if (counter++ > 300) { | 1481 | } else { |
1425 | if (((temp_phy_data & 0xff) == 0x0) && first_time) { | ||
1426 | first_time = 0; | ||
1427 | counter = 0; | ||
1428 | /* reset AMCC PHY and try again */ | ||
1429 | nes_write_10G_phy_reg(nesdev, phy_index, 0x3, 0xe854, 0x00c0); | ||
1430 | nes_write_10G_phy_reg(nesdev, phy_index, 0x3, 0xe854, 0x0040); | ||
1431 | continue; | ||
1432 | } else { | ||
1433 | printk(PFX "PHY did not track\n"); | ||
1434 | break; | ||
1435 | } | ||
1436 | } | ||
1437 | mdelay(10); | ||
1438 | } while ((temp_phy_data & 0xff) < 0x30); | ||
1439 | |||
1440 | /* setup signal integrity */ | ||
1441 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xd003, 0x0000); | ||
1442 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xF00D, 0x00FE); | ||
1443 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xF00E, 0x0032); | ||
1444 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xF00F, 0x0002); | 1482 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xF00F, 0x0002); |
1445 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc314, 0x0063); | 1483 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc314, 0x0063); |
1484 | } | ||
1485 | |||
1486 | /* reset serdes */ | ||
1487 | sds = nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL0 + mac_index * 0x200); | ||
1488 | sds |= 0x1; | ||
1489 | nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL0 + mac_index * 0x200, sds); | ||
1490 | sds &= 0xfffffffe; | ||
1491 | nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL0 + mac_index * 0x200, sds); | ||
1492 | |||
1493 | counter = 0; | ||
1494 | while (((nes_read32(nesdev->regs + NES_SOFTWARE_RESET) & 0x00000040) != 0x00000040) | ||
1495 | && (counter++ < 5000)) | ||
1496 | ; | ||
1497 | |||
1498 | return ret; | ||
1499 | } | ||
1500 | |||
1501 | |||
1502 | /** | ||
1503 | * nes_init_phy | ||
1504 | */ | ||
1505 | int nes_init_phy(struct nes_device *nesdev) | ||
1506 | { | ||
1507 | struct nes_adapter *nesadapter = nesdev->nesadapter; | ||
1508 | u32 mac_index = nesdev->mac_index; | ||
1509 | u32 tx_config = 0; | ||
1510 | unsigned long flags; | ||
1511 | u8 phy_type = nesadapter->phy_type[mac_index]; | ||
1512 | u8 phy_index = nesadapter->phy_index[mac_index]; | ||
1513 | int ret = 0; | ||
1514 | |||
1515 | tx_config = nes_read_indexed(nesdev, NES_IDX_MAC_TX_CONFIG); | ||
1516 | if (phy_type == NES_PHY_TYPE_1G) { | ||
1517 | /* setup 1G MDIO operation */ | ||
1518 | tx_config &= 0xFFFFFFE3; | ||
1519 | tx_config |= 0x04; | ||
1520 | } else { | ||
1521 | /* setup 10G MDIO operation */ | ||
1522 | tx_config &= 0xFFFFFFE3; | ||
1523 | tx_config |= 0x15; | ||
1524 | } | ||
1525 | nes_write_indexed(nesdev, NES_IDX_MAC_TX_CONFIG, tx_config); | ||
1446 | 1526 | ||
1447 | /* reset serdes */ | 1527 | spin_lock_irqsave(&nesdev->nesadapter->phy_lock, flags); |
1448 | sds = nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL0 + | 1528 | |
1449 | mac_index * 0x200); | 1529 | switch (phy_type) { |
1450 | sds |= 0x1; | 1530 | case NES_PHY_TYPE_1G: |
1451 | nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL0 + | 1531 | ret = nes_init_1g_phy(nesdev, phy_type, phy_index); |
1452 | mac_index * 0x200, sds); | 1532 | break; |
1453 | sds &= 0xfffffffe; | 1533 | case NES_PHY_TYPE_ARGUS: |
1454 | nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL0 + | 1534 | case NES_PHY_TYPE_SFP_D: |
1455 | mac_index * 0x200, sds); | 1535 | case NES_PHY_TYPE_KR: |
1456 | 1536 | ret = nes_init_2025_phy(nesdev, phy_type, phy_index); | |
1457 | counter = 0; | 1537 | break; |
1458 | while (((nes_read32(nesdev->regs + NES_SOFTWARE_RESET) & 0x00000040) != 0x00000040) | ||
1459 | && (counter++ < 5000)) | ||
1460 | ; | ||
1461 | } | 1538 | } |
1462 | return 0; | 1539 | |
1540 | spin_unlock_irqrestore(&nesdev->nesadapter->phy_lock, flags); | ||
1541 | |||
1542 | return ret; | ||
1463 | } | 1543 | } |
1464 | 1544 | ||
1465 | 1545 | ||
@@ -2460,23 +2540,9 @@ static void nes_process_mac_intr(struct nes_device *nesdev, u32 mac_number) | |||
2460 | } | 2540 | } |
2461 | } else { | 2541 | } else { |
2462 | switch (nesadapter->phy_type[mac_index]) { | 2542 | switch (nesadapter->phy_type[mac_index]) { |
2463 | case NES_PHY_TYPE_IRIS: | ||
2464 | nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 1, 1); | ||
2465 | temp_phy_data = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL); | ||
2466 | u32temp = 20; | ||
2467 | do { | ||
2468 | nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 1, 1); | ||
2469 | phy_data = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL); | ||
2470 | if ((phy_data == temp_phy_data) || (!(--u32temp))) | ||
2471 | break; | ||
2472 | temp_phy_data = phy_data; | ||
2473 | } while (1); | ||
2474 | nes_debug(NES_DBG_PHY, "%s: Phy data = 0x%04X, link was %s.\n", | ||
2475 | __func__, phy_data, nesadapter->mac_link_down[mac_index] ? "DOWN" : "UP"); | ||
2476 | break; | ||
2477 | |||
2478 | case NES_PHY_TYPE_ARGUS: | 2543 | case NES_PHY_TYPE_ARGUS: |
2479 | case NES_PHY_TYPE_SFP_D: | 2544 | case NES_PHY_TYPE_SFP_D: |
2545 | case NES_PHY_TYPE_KR: | ||
2480 | /* clear the alarms */ | 2546 | /* clear the alarms */ |
2481 | nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 4, 0x0008); | 2547 | nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 4, 0x0008); |
2482 | nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 4, 0xc001); | 2548 | nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 4, 0xc001); |
diff --git a/drivers/infiniband/hw/nes/nes_hw.h b/drivers/infiniband/hw/nes/nes_hw.h index 084be0ee689b..9b1e7f869d83 100644 --- a/drivers/infiniband/hw/nes/nes_hw.h +++ b/drivers/infiniband/hw/nes/nes_hw.h | |||
@@ -37,12 +37,12 @@ | |||
37 | 37 | ||
38 | #define NES_PHY_TYPE_CX4 1 | 38 | #define NES_PHY_TYPE_CX4 1 |
39 | #define NES_PHY_TYPE_1G 2 | 39 | #define NES_PHY_TYPE_1G 2 |
40 | #define NES_PHY_TYPE_IRIS 3 | ||
41 | #define NES_PHY_TYPE_ARGUS 4 | 40 | #define NES_PHY_TYPE_ARGUS 4 |
42 | #define NES_PHY_TYPE_PUMA_1G 5 | 41 | #define NES_PHY_TYPE_PUMA_1G 5 |
43 | #define NES_PHY_TYPE_PUMA_10G 6 | 42 | #define NES_PHY_TYPE_PUMA_10G 6 |
44 | #define NES_PHY_TYPE_GLADIUS 7 | 43 | #define NES_PHY_TYPE_GLADIUS 7 |
45 | #define NES_PHY_TYPE_SFP_D 8 | 44 | #define NES_PHY_TYPE_SFP_D 8 |
45 | #define NES_PHY_TYPE_KR 9 | ||
46 | 46 | ||
47 | #define NES_MULTICAST_PF_MAX 8 | 47 | #define NES_MULTICAST_PF_MAX 8 |
48 | 48 | ||
diff --git a/drivers/infiniband/hw/nes/nes_nic.c b/drivers/infiniband/hw/nes/nes_nic.c index 3d550dc77d0d..7dd6ce6e7b99 100644 --- a/drivers/infiniband/hw/nes/nes_nic.c +++ b/drivers/infiniband/hw/nes/nes_nic.c | |||
@@ -1461,9 +1461,9 @@ static int nes_netdev_get_settings(struct net_device *netdev, struct ethtool_cmd | |||
1461 | } | 1461 | } |
1462 | return 0; | 1462 | return 0; |
1463 | } | 1463 | } |
1464 | if ((phy_type == NES_PHY_TYPE_IRIS) || | 1464 | if ((phy_type == NES_PHY_TYPE_ARGUS) || |
1465 | (phy_type == NES_PHY_TYPE_ARGUS) || | 1465 | (phy_type == NES_PHY_TYPE_SFP_D) || |
1466 | (phy_type == NES_PHY_TYPE_SFP_D)) { | 1466 | (phy_type == NES_PHY_TYPE_KR)) { |
1467 | et_cmd->transceiver = XCVR_EXTERNAL; | 1467 | et_cmd->transceiver = XCVR_EXTERNAL; |
1468 | et_cmd->port = PORT_FIBRE; | 1468 | et_cmd->port = PORT_FIBRE; |
1469 | et_cmd->supported = SUPPORTED_FIBRE; | 1469 | et_cmd->supported = SUPPORTED_FIBRE; |
@@ -1583,8 +1583,7 @@ struct net_device *nes_netdev_init(struct nes_device *nesdev, | |||
1583 | struct net_device *netdev; | 1583 | struct net_device *netdev; |
1584 | struct nic_qp_map *curr_qp_map; | 1584 | struct nic_qp_map *curr_qp_map; |
1585 | u32 u32temp; | 1585 | u32 u32temp; |
1586 | u16 phy_data; | 1586 | u8 phy_type = nesdev->nesadapter->phy_type[nesdev->mac_index]; |
1587 | u16 temp_phy_data; | ||
1588 | 1587 | ||
1589 | netdev = alloc_etherdev(sizeof(struct nes_vnic)); | 1588 | netdev = alloc_etherdev(sizeof(struct nes_vnic)); |
1590 | if (!netdev) { | 1589 | if (!netdev) { |
@@ -1692,65 +1691,23 @@ struct net_device *nes_netdev_init(struct nes_device *nesdev, | |||
1692 | 1691 | ||
1693 | if ((nesdev->netdev_count == 0) && | 1692 | if ((nesdev->netdev_count == 0) && |
1694 | ((PCI_FUNC(nesdev->pcidev->devfn) == nesdev->mac_index) || | 1693 | ((PCI_FUNC(nesdev->pcidev->devfn) == nesdev->mac_index) || |
1695 | ((nesdev->nesadapter->phy_type[nesdev->mac_index] == NES_PHY_TYPE_PUMA_1G) && | 1694 | ((phy_type == NES_PHY_TYPE_PUMA_1G) && |
1696 | (((PCI_FUNC(nesdev->pcidev->devfn) == 1) && (nesdev->mac_index == 2)) || | 1695 | (((PCI_FUNC(nesdev->pcidev->devfn) == 1) && (nesdev->mac_index == 2)) || |
1697 | ((PCI_FUNC(nesdev->pcidev->devfn) == 2) && (nesdev->mac_index == 1)))))) { | 1696 | ((PCI_FUNC(nesdev->pcidev->devfn) == 2) && (nesdev->mac_index == 1)))))) { |
1698 | /* | ||
1699 | * nes_debug(NES_DBG_INIT, "Setting up PHY interrupt mask. Using register index 0x%04X\n", | ||
1700 | * NES_IDX_PHY_PCS_CONTROL_STATUS0 + (0x200 * (nesvnic->logical_port & 1))); | ||
1701 | */ | ||
1702 | u32temp = nes_read_indexed(nesdev, NES_IDX_PHY_PCS_CONTROL_STATUS0 + | 1697 | u32temp = nes_read_indexed(nesdev, NES_IDX_PHY_PCS_CONTROL_STATUS0 + |
1703 | (0x200 * (nesdev->mac_index & 1))); | 1698 | (0x200 * (nesdev->mac_index & 1))); |
1704 | if (nesdev->nesadapter->phy_type[nesdev->mac_index] != NES_PHY_TYPE_PUMA_1G) { | 1699 | if (phy_type != NES_PHY_TYPE_PUMA_1G) { |
1705 | u32temp |= 0x00200000; | 1700 | u32temp |= 0x00200000; |
1706 | nes_write_indexed(nesdev, NES_IDX_PHY_PCS_CONTROL_STATUS0 + | 1701 | nes_write_indexed(nesdev, NES_IDX_PHY_PCS_CONTROL_STATUS0 + |
1707 | (0x200 * (nesdev->mac_index & 1)), u32temp); | 1702 | (0x200 * (nesdev->mac_index & 1)), u32temp); |
1708 | } | 1703 | } |
1709 | 1704 | ||
1710 | u32temp = nes_read_indexed(nesdev, NES_IDX_PHY_PCS_CONTROL_STATUS0 + | ||
1711 | (0x200 * (nesdev->mac_index & 1))); | ||
1712 | |||
1713 | if ((u32temp&0x0f1f0000) == 0x0f0f0000) { | ||
1714 | if (nesdev->nesadapter->phy_type[nesdev->mac_index] == NES_PHY_TYPE_IRIS) { | ||
1715 | nes_init_phy(nesdev); | ||
1716 | nes_read_10G_phy_reg(nesdev, nesdev->nesadapter->phy_index[nesdev->mac_index], 1, 1); | ||
1717 | temp_phy_data = (u16)nes_read_indexed(nesdev, | ||
1718 | NES_IDX_MAC_MDIO_CONTROL); | ||
1719 | u32temp = 20; | ||
1720 | do { | ||
1721 | nes_read_10G_phy_reg(nesdev, nesdev->nesadapter->phy_index[nesdev->mac_index], 1, 1); | ||
1722 | phy_data = (u16)nes_read_indexed(nesdev, | ||
1723 | NES_IDX_MAC_MDIO_CONTROL); | ||
1724 | if ((phy_data == temp_phy_data) || (!(--u32temp))) | ||
1725 | break; | ||
1726 | temp_phy_data = phy_data; | ||
1727 | } while (1); | ||
1728 | if (phy_data & 4) { | ||
1729 | nes_debug(NES_DBG_INIT, "The Link is UP!!.\n"); | ||
1730 | nesvnic->linkup = 1; | ||
1731 | } else { | ||
1732 | nes_debug(NES_DBG_INIT, "The Link is DOWN!!.\n"); | ||
1733 | } | ||
1734 | } else { | ||
1735 | nes_debug(NES_DBG_INIT, "The Link is UP!!.\n"); | ||
1736 | nesvnic->linkup = 1; | ||
1737 | } | ||
1738 | } else if (nesdev->nesadapter->phy_type[nesdev->mac_index] == NES_PHY_TYPE_PUMA_1G) { | ||
1739 | nes_debug(NES_DBG_INIT, "mac_index=%d, logical_port=%d, u32temp=0x%04X, PCI_FUNC=%d\n", | ||
1740 | nesdev->mac_index, nesvnic->logical_port, u32temp, PCI_FUNC(nesdev->pcidev->devfn)); | ||
1741 | if (((nesdev->mac_index < 2) && ((u32temp&0x01010000) == 0x01010000)) || | ||
1742 | ((nesdev->mac_index > 1) && ((u32temp&0x02020000) == 0x02020000))) { | ||
1743 | nes_debug(NES_DBG_INIT, "The Link is UP!!.\n"); | ||
1744 | nesvnic->linkup = 1; | ||
1745 | } | ||
1746 | } | ||
1747 | /* clear the MAC interrupt status, assumes direct logical to physical mapping */ | 1705 | /* clear the MAC interrupt status, assumes direct logical to physical mapping */ |
1748 | u32temp = nes_read_indexed(nesdev, NES_IDX_MAC_INT_STATUS + (0x200 * nesdev->mac_index)); | 1706 | u32temp = nes_read_indexed(nesdev, NES_IDX_MAC_INT_STATUS + (0x200 * nesdev->mac_index)); |
1749 | nes_debug(NES_DBG_INIT, "Phy interrupt status = 0x%X.\n", u32temp); | 1707 | nes_debug(NES_DBG_INIT, "Phy interrupt status = 0x%X.\n", u32temp); |
1750 | nes_write_indexed(nesdev, NES_IDX_MAC_INT_STATUS + (0x200 * nesdev->mac_index), u32temp); | 1708 | nes_write_indexed(nesdev, NES_IDX_MAC_INT_STATUS + (0x200 * nesdev->mac_index), u32temp); |
1751 | 1709 | ||
1752 | if (nesdev->nesadapter->phy_type[nesdev->mac_index] != NES_PHY_TYPE_IRIS) | 1710 | nes_init_phy(nesdev); |
1753 | nes_init_phy(nesdev); | ||
1754 | 1711 | ||
1755 | } | 1712 | } |
1756 | 1713 | ||