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authorBenjamin Herrenschmidt <benh@kernel.crashing.org>2011-01-10 23:10:08 -0500
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>2011-01-10 23:10:08 -0500
commiteed0ba0b4ab2d1668588219a8efa81bf8636a12d (patch)
treef5aa3c732e7830a1b24e6071f8bed0f799881187 /drivers/gpu
parent98b14d6b290d96b24ae993ceaccc59b2aa4b130c (diff)
parentc9de9333f5a860cab82052bce6ac28bcac9b2c26 (diff)
Merge remote branch 'gcl/next' into next
Diffstat (limited to 'drivers/gpu')
-rw-r--r--drivers/gpu/drm/drm_crtc.c10
-rw-r--r--drivers/gpu/drm/drm_crtc_helper.c17
-rw-r--r--drivers/gpu/drm/drm_irq.c21
-rw-r--r--drivers/gpu/drm/i915/i915_dma.c3
-rw-r--r--drivers/gpu/drm/i915/i915_gem.c525
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h1
-rw-r--r--drivers/gpu/drm/i915/i915_suspend.c40
-rw-r--r--drivers/gpu/drm/i915/intel_acpi.c34
-rw-r--r--drivers/gpu/drm/i915/intel_bios.c2
-rw-r--r--drivers/gpu/drm/i915/intel_display.c83
-rw-r--r--drivers/gpu/drm/i915/intel_dp.c208
-rw-r--r--drivers/gpu/drm/i915/intel_drv.h2
-rw-r--r--drivers/gpu/drm/i915/intel_lvds.c117
-rw-r--r--drivers/gpu/drm/i915/intel_ringbuffer.c49
-rw-r--r--drivers/gpu/drm/i915/intel_ringbuffer.h5
-rw-r--r--drivers/gpu/drm/i915/intel_sdvo.c93
-rw-r--r--drivers/gpu/drm/radeon/atom.c1
-rw-r--r--drivers/gpu/drm/radeon/atombios_crtc.c7
-rw-r--r--drivers/gpu/drm/radeon/evergreen.c27
-rw-r--r--drivers/gpu/drm/radeon/evergreend.h1
-rw-r--r--drivers/gpu/drm/radeon/r600.c27
-rw-r--r--drivers/gpu/drm/radeon/r600_cs.c9
-rw-r--r--drivers/gpu/drm/radeon/r600_reg.h1
-rw-r--r--drivers/gpu/drm/radeon/radeon_atombios.c16
-rw-r--r--drivers/gpu/drm/radeon/radeon_bios.c13
-rw-r--r--drivers/gpu/drm/radeon/radeon_combios.c2
-rw-r--r--drivers/gpu/drm/radeon/radeon_connectors.c34
-rw-r--r--drivers/gpu/drm/radeon/radeon_device.c13
-rw-r--r--drivers/gpu/drm/radeon/radeon_drv.c19
-rw-r--r--drivers/gpu/drm/radeon/radeon_fb.c2
-rw-r--r--drivers/gpu/drm/radeon/radeon_object.c13
31 files changed, 830 insertions, 565 deletions
diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
index 6985cb1da72c..2baa6708e44c 100644
--- a/drivers/gpu/drm/drm_crtc.c
+++ b/drivers/gpu/drm/drm_crtc.c
@@ -156,12 +156,12 @@ static struct drm_conn_prop_enum_list drm_connector_enum_list[] =
156 { DRM_MODE_CONNECTOR_SVIDEO, "SVIDEO", 0 }, 156 { DRM_MODE_CONNECTOR_SVIDEO, "SVIDEO", 0 },
157 { DRM_MODE_CONNECTOR_LVDS, "LVDS", 0 }, 157 { DRM_MODE_CONNECTOR_LVDS, "LVDS", 0 },
158 { DRM_MODE_CONNECTOR_Component, "Component", 0 }, 158 { DRM_MODE_CONNECTOR_Component, "Component", 0 },
159 { DRM_MODE_CONNECTOR_9PinDIN, "9-pin DIN", 0 }, 159 { DRM_MODE_CONNECTOR_9PinDIN, "DIN", 0 },
160 { DRM_MODE_CONNECTOR_DisplayPort, "DisplayPort", 0 }, 160 { DRM_MODE_CONNECTOR_DisplayPort, "DP", 0 },
161 { DRM_MODE_CONNECTOR_HDMIA, "HDMI Type A", 0 }, 161 { DRM_MODE_CONNECTOR_HDMIA, "HDMI-A", 0 },
162 { DRM_MODE_CONNECTOR_HDMIB, "HDMI Type B", 0 }, 162 { DRM_MODE_CONNECTOR_HDMIB, "HDMI-B", 0 },
163 { DRM_MODE_CONNECTOR_TV, "TV", 0 }, 163 { DRM_MODE_CONNECTOR_TV, "TV", 0 },
164 { DRM_MODE_CONNECTOR_eDP, "Embedded DisplayPort", 0 }, 164 { DRM_MODE_CONNECTOR_eDP, "eDP", 0 },
165}; 165};
166 166
167static struct drm_prop_enum_list drm_encoder_enum_list[] = 167static struct drm_prop_enum_list drm_encoder_enum_list[] =
diff --git a/drivers/gpu/drm/drm_crtc_helper.c b/drivers/gpu/drm/drm_crtc_helper.c
index f7af91cb273d..2d4e17a004db 100644
--- a/drivers/gpu/drm/drm_crtc_helper.c
+++ b/drivers/gpu/drm/drm_crtc_helper.c
@@ -471,6 +471,7 @@ int drm_crtc_helper_set_config(struct drm_mode_set *set)
471 int count = 0, ro, fail = 0; 471 int count = 0, ro, fail = 0;
472 struct drm_crtc_helper_funcs *crtc_funcs; 472 struct drm_crtc_helper_funcs *crtc_funcs;
473 int ret = 0; 473 int ret = 0;
474 int i;
474 475
475 DRM_DEBUG_KMS("\n"); 476 DRM_DEBUG_KMS("\n");
476 477
@@ -666,6 +667,12 @@ int drm_crtc_helper_set_config(struct drm_mode_set *set)
666 if (ret != 0) 667 if (ret != 0)
667 goto fail; 668 goto fail;
668 } 669 }
670 DRM_DEBUG_KMS("Setting connector DPMS state to on\n");
671 for (i = 0; i < set->num_connectors; i++) {
672 DRM_DEBUG_KMS("\t[CONNECTOR:%d:%s] set DPMS on\n", set->connectors[i]->base.id,
673 drm_get_connector_name(set->connectors[i]));
674 set->connectors[i]->dpms = DRM_MODE_DPMS_ON;
675 }
669 676
670 kfree(save_connectors); 677 kfree(save_connectors);
671 kfree(save_encoders); 678 kfree(save_encoders);
@@ -841,7 +848,7 @@ static void output_poll_execute(struct work_struct *work)
841 struct delayed_work *delayed_work = to_delayed_work(work); 848 struct delayed_work *delayed_work = to_delayed_work(work);
842 struct drm_device *dev = container_of(delayed_work, struct drm_device, mode_config.output_poll_work); 849 struct drm_device *dev = container_of(delayed_work, struct drm_device, mode_config.output_poll_work);
843 struct drm_connector *connector; 850 struct drm_connector *connector;
844 enum drm_connector_status old_status, status; 851 enum drm_connector_status old_status;
845 bool repoll = false, changed = false; 852 bool repoll = false, changed = false;
846 853
847 if (!drm_kms_helper_poll) 854 if (!drm_kms_helper_poll)
@@ -866,8 +873,12 @@ static void output_poll_execute(struct work_struct *work)
866 !(connector->polled & DRM_CONNECTOR_POLL_HPD)) 873 !(connector->polled & DRM_CONNECTOR_POLL_HPD))
867 continue; 874 continue;
868 875
869 status = connector->funcs->detect(connector, false); 876 connector->status = connector->funcs->detect(connector, false);
870 if (old_status != status) 877 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %d to %d\n",
878 connector->base.id,
879 drm_get_connector_name(connector),
880 old_status, connector->status);
881 if (old_status != connector->status)
871 changed = true; 882 changed = true;
872 } 883 }
873 884
diff --git a/drivers/gpu/drm/drm_irq.c b/drivers/gpu/drm/drm_irq.c
index 9d3a5030b6e1..16d5155edad1 100644
--- a/drivers/gpu/drm/drm_irq.c
+++ b/drivers/gpu/drm/drm_irq.c
@@ -585,10 +585,13 @@ static int drm_queue_vblank_event(struct drm_device *dev, int pipe,
585 struct timeval now; 585 struct timeval now;
586 unsigned long flags; 586 unsigned long flags;
587 unsigned int seq; 587 unsigned int seq;
588 int ret;
588 589
589 e = kzalloc(sizeof *e, GFP_KERNEL); 590 e = kzalloc(sizeof *e, GFP_KERNEL);
590 if (e == NULL) 591 if (e == NULL) {
591 return -ENOMEM; 592 ret = -ENOMEM;
593 goto err_put;
594 }
592 595
593 e->pipe = pipe; 596 e->pipe = pipe;
594 e->base.pid = current->pid; 597 e->base.pid = current->pid;
@@ -603,9 +606,8 @@ static int drm_queue_vblank_event(struct drm_device *dev, int pipe,
603 spin_lock_irqsave(&dev->event_lock, flags); 606 spin_lock_irqsave(&dev->event_lock, flags);
604 607
605 if (file_priv->event_space < sizeof e->event) { 608 if (file_priv->event_space < sizeof e->event) {
606 spin_unlock_irqrestore(&dev->event_lock, flags); 609 ret = -EBUSY;
607 kfree(e); 610 goto err_unlock;
608 return -ENOMEM;
609 } 611 }
610 612
611 file_priv->event_space -= sizeof e->event; 613 file_priv->event_space -= sizeof e->event;
@@ -626,7 +628,7 @@ static int drm_queue_vblank_event(struct drm_device *dev, int pipe,
626 if ((seq - vblwait->request.sequence) <= (1 << 23)) { 628 if ((seq - vblwait->request.sequence) <= (1 << 23)) {
627 e->event.tv_sec = now.tv_sec; 629 e->event.tv_sec = now.tv_sec;
628 e->event.tv_usec = now.tv_usec; 630 e->event.tv_usec = now.tv_usec;
629 drm_vblank_put(dev, e->pipe); 631 drm_vblank_put(dev, pipe);
630 list_add_tail(&e->base.link, &e->base.file_priv->event_list); 632 list_add_tail(&e->base.link, &e->base.file_priv->event_list);
631 wake_up_interruptible(&e->base.file_priv->event_wait); 633 wake_up_interruptible(&e->base.file_priv->event_wait);
632 trace_drm_vblank_event_delivered(current->pid, pipe, 634 trace_drm_vblank_event_delivered(current->pid, pipe,
@@ -638,6 +640,13 @@ static int drm_queue_vblank_event(struct drm_device *dev, int pipe,
638 spin_unlock_irqrestore(&dev->event_lock, flags); 640 spin_unlock_irqrestore(&dev->event_lock, flags);
639 641
640 return 0; 642 return 0;
643
644err_unlock:
645 spin_unlock_irqrestore(&dev->event_lock, flags);
646 kfree(e);
647err_put:
648 drm_vblank_put(dev, pipe);
649 return ret;
641} 650}
642 651
643/** 652/**
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 7a26f4dd21ae..e6800819bca8 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -767,6 +767,9 @@ static int i915_getparam(struct drm_device *dev, void *data,
767 case I915_PARAM_HAS_BLT: 767 case I915_PARAM_HAS_BLT:
768 value = HAS_BLT(dev); 768 value = HAS_BLT(dev);
769 break; 769 break;
770 case I915_PARAM_HAS_COHERENT_RINGS:
771 value = 1;
772 break;
770 default: 773 default:
771 DRM_DEBUG_DRIVER("Unknown parameter %d\n", 774 DRM_DEBUG_DRIVER("Unknown parameter %d\n",
772 param->param); 775 param->param);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 17b1cba3b5f1..275ec6ed43ae 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -38,8 +38,7 @@
38 38
39static uint32_t i915_gem_get_gtt_alignment(struct drm_gem_object *obj); 39static uint32_t i915_gem_get_gtt_alignment(struct drm_gem_object *obj);
40 40
41static int i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj, 41static int i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj);
42 bool pipelined);
43static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj); 42static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj);
44static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj); 43static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj);
45static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, 44static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj,
@@ -2594,7 +2593,7 @@ i915_gem_object_put_fence_reg(struct drm_gem_object *obj,
2594 if (reg->gpu) { 2593 if (reg->gpu) {
2595 int ret; 2594 int ret;
2596 2595
2597 ret = i915_gem_object_flush_gpu_write_domain(obj, true); 2596 ret = i915_gem_object_flush_gpu_write_domain(obj);
2598 if (ret) 2597 if (ret)
2599 return ret; 2598 return ret;
2600 2599
@@ -2742,8 +2741,7 @@ i915_gem_clflush_object(struct drm_gem_object *obj)
2742 2741
2743/** Flushes any GPU write domain for the object if it's dirty. */ 2742/** Flushes any GPU write domain for the object if it's dirty. */
2744static int 2743static int
2745i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj, 2744i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj)
2746 bool pipelined)
2747{ 2745{
2748 struct drm_device *dev = obj->dev; 2746 struct drm_device *dev = obj->dev;
2749 uint32_t old_write_domain; 2747 uint32_t old_write_domain;
@@ -2762,10 +2760,7 @@ i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj,
2762 obj->read_domains, 2760 obj->read_domains,
2763 old_write_domain); 2761 old_write_domain);
2764 2762
2765 if (pipelined) 2763 return 0;
2766 return 0;
2767
2768 return i915_gem_object_wait_rendering(obj, true);
2769} 2764}
2770 2765
2771/** Flushes the GTT write domain for the object if it's dirty. */ 2766/** Flushes the GTT write domain for the object if it's dirty. */
@@ -2826,18 +2821,15 @@ i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write)
2826 if (obj_priv->gtt_space == NULL) 2821 if (obj_priv->gtt_space == NULL)
2827 return -EINVAL; 2822 return -EINVAL;
2828 2823
2829 ret = i915_gem_object_flush_gpu_write_domain(obj, false); 2824 ret = i915_gem_object_flush_gpu_write_domain(obj);
2830 if (ret != 0) 2825 if (ret != 0)
2831 return ret; 2826 return ret;
2827 ret = i915_gem_object_wait_rendering(obj, true);
2828 if (ret)
2829 return ret;
2832 2830
2833 i915_gem_object_flush_cpu_write_domain(obj); 2831 i915_gem_object_flush_cpu_write_domain(obj);
2834 2832
2835 if (write) {
2836 ret = i915_gem_object_wait_rendering(obj, true);
2837 if (ret)
2838 return ret;
2839 }
2840
2841 old_write_domain = obj->write_domain; 2833 old_write_domain = obj->write_domain;
2842 old_read_domains = obj->read_domains; 2834 old_read_domains = obj->read_domains;
2843 2835
@@ -2875,7 +2867,7 @@ i915_gem_object_set_to_display_plane(struct drm_gem_object *obj,
2875 if (obj_priv->gtt_space == NULL) 2867 if (obj_priv->gtt_space == NULL)
2876 return -EINVAL; 2868 return -EINVAL;
2877 2869
2878 ret = i915_gem_object_flush_gpu_write_domain(obj, true); 2870 ret = i915_gem_object_flush_gpu_write_domain(obj);
2879 if (ret) 2871 if (ret)
2880 return ret; 2872 return ret;
2881 2873
@@ -2924,9 +2916,12 @@ i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write)
2924 uint32_t old_write_domain, old_read_domains; 2916 uint32_t old_write_domain, old_read_domains;
2925 int ret; 2917 int ret;
2926 2918
2927 ret = i915_gem_object_flush_gpu_write_domain(obj, false); 2919 ret = i915_gem_object_flush_gpu_write_domain(obj);
2928 if (ret != 0) 2920 if (ret != 0)
2929 return ret; 2921 return ret;
2922 ret = i915_gem_object_wait_rendering(obj, true);
2923 if (ret)
2924 return ret;
2930 2925
2931 i915_gem_object_flush_gtt_write_domain(obj); 2926 i915_gem_object_flush_gtt_write_domain(obj);
2932 2927
@@ -2935,12 +2930,6 @@ i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write)
2935 */ 2930 */
2936 i915_gem_object_set_to_full_cpu_read_domain(obj); 2931 i915_gem_object_set_to_full_cpu_read_domain(obj);
2937 2932
2938 if (write) {
2939 ret = i915_gem_object_wait_rendering(obj, true);
2940 if (ret)
2941 return ret;
2942 }
2943
2944 old_write_domain = obj->write_domain; 2933 old_write_domain = obj->write_domain;
2945 old_read_domains = obj->read_domains; 2934 old_read_domains = obj->read_domains;
2946 2935
@@ -3205,9 +3194,13 @@ i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
3205 if (offset == 0 && size == obj->size) 3194 if (offset == 0 && size == obj->size)
3206 return i915_gem_object_set_to_cpu_domain(obj, 0); 3195 return i915_gem_object_set_to_cpu_domain(obj, 0);
3207 3196
3208 ret = i915_gem_object_flush_gpu_write_domain(obj, false); 3197 ret = i915_gem_object_flush_gpu_write_domain(obj);
3209 if (ret != 0) 3198 if (ret != 0)
3210 return ret; 3199 return ret;
3200 ret = i915_gem_object_wait_rendering(obj, true);
3201 if (ret)
3202 return ret;
3203
3211 i915_gem_object_flush_gtt_write_domain(obj); 3204 i915_gem_object_flush_gtt_write_domain(obj);
3212 3205
3213 /* If we're already fully in the CPU read domain, we're done. */ 3206 /* If we're already fully in the CPU read domain, we're done. */
@@ -3254,192 +3247,230 @@ i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
3254 return 0; 3247 return 0;
3255} 3248}
3256 3249
3257/**
3258 * Pin an object to the GTT and evaluate the relocations landing in it.
3259 */
3260static int 3250static int
3261i915_gem_execbuffer_relocate(struct drm_i915_gem_object *obj, 3251i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj,
3262 struct drm_file *file_priv, 3252 struct drm_file *file_priv,
3263 struct drm_i915_gem_exec_object2 *entry) 3253 struct drm_i915_gem_exec_object2 *entry,
3254 struct drm_i915_gem_relocation_entry *reloc)
3264{ 3255{
3265 struct drm_device *dev = obj->base.dev; 3256 struct drm_device *dev = obj->base.dev;
3266 drm_i915_private_t *dev_priv = dev->dev_private; 3257 struct drm_gem_object *target_obj;
3267 struct drm_i915_gem_relocation_entry __user *user_relocs; 3258 uint32_t target_offset;
3268 struct drm_gem_object *target_obj = NULL; 3259 int ret = -EINVAL;
3269 uint32_t target_handle = 0;
3270 int i, ret = 0;
3271 3260
3272 user_relocs = (void __user *)(uintptr_t)entry->relocs_ptr; 3261 target_obj = drm_gem_object_lookup(dev, file_priv,
3273 for (i = 0; i < entry->relocation_count; i++) { 3262 reloc->target_handle);
3274 struct drm_i915_gem_relocation_entry reloc; 3263 if (target_obj == NULL)
3275 uint32_t target_offset; 3264 return -ENOENT;
3276 3265
3277 if (__copy_from_user_inatomic(&reloc, 3266 target_offset = to_intel_bo(target_obj)->gtt_offset;
3278 user_relocs+i,
3279 sizeof(reloc))) {
3280 ret = -EFAULT;
3281 break;
3282 }
3283 3267
3284 if (reloc.target_handle != target_handle) { 3268#if WATCH_RELOC
3285 drm_gem_object_unreference(target_obj); 3269 DRM_INFO("%s: obj %p offset %08x target %d "
3270 "read %08x write %08x gtt %08x "
3271 "presumed %08x delta %08x\n",
3272 __func__,
3273 obj,
3274 (int) reloc->offset,
3275 (int) reloc->target_handle,
3276 (int) reloc->read_domains,
3277 (int) reloc->write_domain,
3278 (int) target_offset,
3279 (int) reloc->presumed_offset,
3280 reloc->delta);
3281#endif
3286 3282
3287 target_obj = drm_gem_object_lookup(dev, file_priv, 3283 /* The target buffer should have appeared before us in the
3288 reloc.target_handle); 3284 * exec_object list, so it should have a GTT space bound by now.
3289 if (target_obj == NULL) { 3285 */
3290 ret = -ENOENT; 3286 if (target_offset == 0) {
3291 break; 3287 DRM_ERROR("No GTT space found for object %d\n",
3292 } 3288 reloc->target_handle);
3289 goto err;
3290 }
3293 3291
3294 target_handle = reloc.target_handle; 3292 /* Validate that the target is in a valid r/w GPU domain */
3295 } 3293 if (reloc->write_domain & (reloc->write_domain - 1)) {
3296 target_offset = to_intel_bo(target_obj)->gtt_offset; 3294 DRM_ERROR("reloc with multiple write domains: "
3295 "obj %p target %d offset %d "
3296 "read %08x write %08x",
3297 obj, reloc->target_handle,
3298 (int) reloc->offset,
3299 reloc->read_domains,
3300 reloc->write_domain);
3301 goto err;
3302 }
3303 if (reloc->write_domain & I915_GEM_DOMAIN_CPU ||
3304 reloc->read_domains & I915_GEM_DOMAIN_CPU) {
3305 DRM_ERROR("reloc with read/write CPU domains: "
3306 "obj %p target %d offset %d "
3307 "read %08x write %08x",
3308 obj, reloc->target_handle,
3309 (int) reloc->offset,
3310 reloc->read_domains,
3311 reloc->write_domain);
3312 goto err;
3313 }
3314 if (reloc->write_domain && target_obj->pending_write_domain &&
3315 reloc->write_domain != target_obj->pending_write_domain) {
3316 DRM_ERROR("Write domain conflict: "
3317 "obj %p target %d offset %d "
3318 "new %08x old %08x\n",
3319 obj, reloc->target_handle,
3320 (int) reloc->offset,
3321 reloc->write_domain,
3322 target_obj->pending_write_domain);
3323 goto err;
3324 }
3297 3325
3298#if WATCH_RELOC 3326 target_obj->pending_read_domains |= reloc->read_domains;
3299 DRM_INFO("%s: obj %p offset %08x target %d " 3327 target_obj->pending_write_domain |= reloc->write_domain;
3300 "read %08x write %08x gtt %08x "
3301 "presumed %08x delta %08x\n",
3302 __func__,
3303 obj,
3304 (int) reloc.offset,
3305 (int) reloc.target_handle,
3306 (int) reloc.read_domains,
3307 (int) reloc.write_domain,
3308 (int) target_offset,
3309 (int) reloc.presumed_offset,
3310 reloc.delta);
3311#endif
3312 3328
3313 /* The target buffer should have appeared before us in the 3329 /* If the relocation already has the right value in it, no
3314 * exec_object list, so it should have a GTT space bound by now. 3330 * more work needs to be done.
3315 */ 3331 */
3316 if (target_offset == 0) { 3332 if (target_offset == reloc->presumed_offset)
3317 DRM_ERROR("No GTT space found for object %d\n", 3333 goto out;
3318 reloc.target_handle);
3319 ret = -EINVAL;
3320 break;
3321 }
3322 3334
3323 /* Validate that the target is in a valid r/w GPU domain */ 3335 /* Check that the relocation address is valid... */
3324 if (reloc.write_domain & (reloc.write_domain - 1)) { 3336 if (reloc->offset > obj->base.size - 4) {
3325 DRM_ERROR("reloc with multiple write domains: " 3337 DRM_ERROR("Relocation beyond object bounds: "
3326 "obj %p target %d offset %d " 3338 "obj %p target %d offset %d size %d.\n",
3327 "read %08x write %08x", 3339 obj, reloc->target_handle,
3328 obj, reloc.target_handle, 3340 (int) reloc->offset,
3329 (int) reloc.offset, 3341 (int) obj->base.size);
3330 reloc.read_domains, 3342 goto err;
3331 reloc.write_domain); 3343 }
3332 ret = -EINVAL; 3344 if (reloc->offset & 3) {
3333 break; 3345 DRM_ERROR("Relocation not 4-byte aligned: "
3334 } 3346 "obj %p target %d offset %d.\n",
3335 if (reloc.write_domain & I915_GEM_DOMAIN_CPU || 3347 obj, reloc->target_handle,
3336 reloc.read_domains & I915_GEM_DOMAIN_CPU) { 3348 (int) reloc->offset);
3337 DRM_ERROR("reloc with read/write CPU domains: " 3349 goto err;
3338 "obj %p target %d offset %d " 3350 }
3339 "read %08x write %08x",
3340 obj, reloc.target_handle,
3341 (int) reloc.offset,
3342 reloc.read_domains,
3343 reloc.write_domain);
3344 ret = -EINVAL;
3345 break;
3346 }
3347 if (reloc.write_domain && target_obj->pending_write_domain &&
3348 reloc.write_domain != target_obj->pending_write_domain) {
3349 DRM_ERROR("Write domain conflict: "
3350 "obj %p target %d offset %d "
3351 "new %08x old %08x\n",
3352 obj, reloc.target_handle,
3353 (int) reloc.offset,
3354 reloc.write_domain,
3355 target_obj->pending_write_domain);
3356 ret = -EINVAL;
3357 break;
3358 }
3359 3351
3360 target_obj->pending_read_domains |= reloc.read_domains; 3352 /* and points to somewhere within the target object. */
3361 target_obj->pending_write_domain |= reloc.write_domain; 3353 if (reloc->delta >= target_obj->size) {
3354 DRM_ERROR("Relocation beyond target object bounds: "
3355 "obj %p target %d delta %d size %d.\n",
3356 obj, reloc->target_handle,
3357 (int) reloc->delta,
3358 (int) target_obj->size);
3359 goto err;
3360 }
3362 3361
3363 /* If the relocation already has the right value in it, no 3362 reloc->delta += target_offset;
3364 * more work needs to be done. 3363 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) {
3365 */ 3364 uint32_t page_offset = reloc->offset & ~PAGE_MASK;
3366 if (target_offset == reloc.presumed_offset) 3365 char *vaddr;
3367 continue;
3368 3366
3369 /* Check that the relocation address is valid... */ 3367 vaddr = kmap_atomic(obj->pages[reloc->offset >> PAGE_SHIFT]);
3370 if (reloc.offset > obj->base.size - 4) { 3368 *(uint32_t *)(vaddr + page_offset) = reloc->delta;
3371 DRM_ERROR("Relocation beyond object bounds: " 3369 kunmap_atomic(vaddr);
3372 "obj %p target %d offset %d size %d.\n", 3370 } else {
3373 obj, reloc.target_handle, 3371 struct drm_i915_private *dev_priv = dev->dev_private;
3374 (int) reloc.offset, (int) obj->base.size); 3372 uint32_t __iomem *reloc_entry;
3375 ret = -EINVAL; 3373 void __iomem *reloc_page;
3376 break;
3377 }
3378 if (reloc.offset & 3) {
3379 DRM_ERROR("Relocation not 4-byte aligned: "
3380 "obj %p target %d offset %d.\n",
3381 obj, reloc.target_handle,
3382 (int) reloc.offset);
3383 ret = -EINVAL;
3384 break;
3385 }
3386 3374
3387 /* and points to somewhere within the target object. */ 3375 ret = i915_gem_object_set_to_gtt_domain(&obj->base, 1);
3388 if (reloc.delta >= target_obj->size) { 3376 if (ret)
3389 DRM_ERROR("Relocation beyond target object bounds: " 3377 goto err;
3390 "obj %p target %d delta %d size %d.\n",
3391 obj, reloc.target_handle,
3392 (int) reloc.delta, (int) target_obj->size);
3393 ret = -EINVAL;
3394 break;
3395 }
3396 3378
3397 reloc.delta += target_offset; 3379 /* Map the page containing the relocation we're going to perform. */
3398 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) { 3380 reloc->offset += obj->gtt_offset;
3399 uint32_t page_offset = reloc.offset & ~PAGE_MASK; 3381 reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
3400 char *vaddr; 3382 reloc->offset & PAGE_MASK);
3383 reloc_entry = (uint32_t __iomem *)
3384 (reloc_page + (reloc->offset & ~PAGE_MASK));
3385 iowrite32(reloc->delta, reloc_entry);
3386 io_mapping_unmap_atomic(reloc_page);
3387 }
3401 3388
3402 vaddr = kmap_atomic(obj->pages[reloc.offset >> PAGE_SHIFT]); 3389 /* and update the user's relocation entry */
3403 *(uint32_t *)(vaddr + page_offset) = reloc.delta; 3390 reloc->presumed_offset = target_offset;
3404 kunmap_atomic(vaddr);
3405 } else {
3406 uint32_t __iomem *reloc_entry;
3407 void __iomem *reloc_page;
3408 3391
3409 ret = i915_gem_object_set_to_gtt_domain(&obj->base, 1); 3392out:
3410 if (ret) 3393 ret = 0;
3411 break; 3394err:
3395 drm_gem_object_unreference(target_obj);
3396 return ret;
3397}
3412 3398
3413 /* Map the page containing the relocation we're going to perform. */ 3399static int
3414 reloc.offset += obj->gtt_offset; 3400i915_gem_execbuffer_relocate_object(struct drm_i915_gem_object *obj,
3415 reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping, 3401 struct drm_file *file_priv,
3416 reloc.offset & PAGE_MASK); 3402 struct drm_i915_gem_exec_object2 *entry)
3417 reloc_entry = (uint32_t __iomem *) 3403{
3418 (reloc_page + (reloc.offset & ~PAGE_MASK)); 3404 struct drm_i915_gem_relocation_entry __user *user_relocs;
3419 iowrite32(reloc.delta, reloc_entry); 3405 int i, ret;
3420 io_mapping_unmap_atomic(reloc_page); 3406
3421 } 3407 user_relocs = (void __user *)(uintptr_t)entry->relocs_ptr;
3408 for (i = 0; i < entry->relocation_count; i++) {
3409 struct drm_i915_gem_relocation_entry reloc;
3410
3411 if (__copy_from_user_inatomic(&reloc,
3412 user_relocs+i,
3413 sizeof(reloc)))
3414 return -EFAULT;
3415
3416 ret = i915_gem_execbuffer_relocate_entry(obj, file_priv, entry, &reloc);
3417 if (ret)
3418 return ret;
3422 3419
3423 /* and update the user's relocation entry */
3424 reloc.presumed_offset = target_offset;
3425 if (__copy_to_user_inatomic(&user_relocs[i].presumed_offset, 3420 if (__copy_to_user_inatomic(&user_relocs[i].presumed_offset,
3426 &reloc.presumed_offset, 3421 &reloc.presumed_offset,
3427 sizeof(reloc.presumed_offset))) { 3422 sizeof(reloc.presumed_offset)))
3428 ret = -EFAULT; 3423 return -EFAULT;
3429 break;
3430 }
3431 } 3424 }
3432 3425
3433 drm_gem_object_unreference(target_obj); 3426 return 0;
3434 return ret; 3427}
3428
3429static int
3430i915_gem_execbuffer_relocate_object_slow(struct drm_i915_gem_object *obj,
3431 struct drm_file *file_priv,
3432 struct drm_i915_gem_exec_object2 *entry,
3433 struct drm_i915_gem_relocation_entry *relocs)
3434{
3435 int i, ret;
3436
3437 for (i = 0; i < entry->relocation_count; i++) {
3438 ret = i915_gem_execbuffer_relocate_entry(obj, file_priv, entry, &relocs[i]);
3439 if (ret)
3440 return ret;
3441 }
3442
3443 return 0;
3435} 3444}
3436 3445
3437static int 3446static int
3438i915_gem_execbuffer_pin(struct drm_device *dev, 3447i915_gem_execbuffer_relocate(struct drm_device *dev,
3439 struct drm_file *file, 3448 struct drm_file *file,
3440 struct drm_gem_object **object_list, 3449 struct drm_gem_object **object_list,
3441 struct drm_i915_gem_exec_object2 *exec_list, 3450 struct drm_i915_gem_exec_object2 *exec_list,
3442 int count) 3451 int count)
3452{
3453 int i, ret;
3454
3455 for (i = 0; i < count; i++) {
3456 struct drm_i915_gem_object *obj = to_intel_bo(object_list[i]);
3457 obj->base.pending_read_domains = 0;
3458 obj->base.pending_write_domain = 0;
3459 ret = i915_gem_execbuffer_relocate_object(obj, file,
3460 &exec_list[i]);
3461 if (ret)
3462 return ret;
3463 }
3464
3465 return 0;
3466}
3467
3468static int
3469i915_gem_execbuffer_reserve(struct drm_device *dev,
3470 struct drm_file *file,
3471 struct drm_gem_object **object_list,
3472 struct drm_i915_gem_exec_object2 *exec_list,
3473 int count)
3443{ 3474{
3444 struct drm_i915_private *dev_priv = dev->dev_private; 3475 struct drm_i915_private *dev_priv = dev->dev_private;
3445 int ret, i, retry; 3476 int ret, i, retry;
@@ -3502,6 +3533,87 @@ i915_gem_execbuffer_pin(struct drm_device *dev,
3502} 3533}
3503 3534
3504static int 3535static int
3536i915_gem_execbuffer_relocate_slow(struct drm_device *dev,
3537 struct drm_file *file,
3538 struct drm_gem_object **object_list,
3539 struct drm_i915_gem_exec_object2 *exec_list,
3540 int count)
3541{
3542 struct drm_i915_gem_relocation_entry *reloc;
3543 int i, total, ret;
3544
3545 for (i = 0; i < count; i++) {
3546 struct drm_i915_gem_object *obj = to_intel_bo(object_list[i]);
3547 obj->in_execbuffer = false;
3548 }
3549
3550 mutex_unlock(&dev->struct_mutex);
3551
3552 total = 0;
3553 for (i = 0; i < count; i++)
3554 total += exec_list[i].relocation_count;
3555
3556 reloc = drm_malloc_ab(total, sizeof(*reloc));
3557 if (reloc == NULL) {
3558 mutex_lock(&dev->struct_mutex);
3559 return -ENOMEM;
3560 }
3561
3562 total = 0;
3563 for (i = 0; i < count; i++) {
3564 struct drm_i915_gem_relocation_entry __user *user_relocs;
3565
3566 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3567
3568 if (copy_from_user(reloc+total, user_relocs,
3569 exec_list[i].relocation_count *
3570 sizeof(*reloc))) {
3571 ret = -EFAULT;
3572 mutex_lock(&dev->struct_mutex);
3573 goto err;
3574 }
3575
3576 total += exec_list[i].relocation_count;
3577 }
3578
3579 ret = i915_mutex_lock_interruptible(dev);
3580 if (ret) {
3581 mutex_lock(&dev->struct_mutex);
3582 goto err;
3583 }
3584
3585 ret = i915_gem_execbuffer_reserve(dev, file,
3586 object_list, exec_list,
3587 count);
3588 if (ret)
3589 goto err;
3590
3591 total = 0;
3592 for (i = 0; i < count; i++) {
3593 struct drm_i915_gem_object *obj = to_intel_bo(object_list[i]);
3594 obj->base.pending_read_domains = 0;
3595 obj->base.pending_write_domain = 0;
3596 ret = i915_gem_execbuffer_relocate_object_slow(obj, file,
3597 &exec_list[i],
3598 reloc + total);
3599 if (ret)
3600 goto err;
3601
3602 total += exec_list[i].relocation_count;
3603 }
3604
3605 /* Leave the user relocations as are, this is the painfully slow path,
3606 * and we want to avoid the complication of dropping the lock whilst
3607 * having buffers reserved in the aperture and so causing spurious
3608 * ENOSPC for random operations.
3609 */
3610
3611err:
3612 drm_free_large(reloc);
3613 return ret;
3614}
3615
3616static int
3505i915_gem_execbuffer_move_to_gpu(struct drm_device *dev, 3617i915_gem_execbuffer_move_to_gpu(struct drm_device *dev,
3506 struct drm_file *file, 3618 struct drm_file *file,
3507 struct intel_ring_buffer *ring, 3619 struct intel_ring_buffer *ring,
@@ -3630,8 +3742,15 @@ validate_exec_list(struct drm_i915_gem_exec_object2 *exec,
3630 3742
3631 for (i = 0; i < count; i++) { 3743 for (i = 0; i < count; i++) {
3632 char __user *ptr = (char __user *)(uintptr_t)exec[i].relocs_ptr; 3744 char __user *ptr = (char __user *)(uintptr_t)exec[i].relocs_ptr;
3633 size_t length = exec[i].relocation_count * sizeof(struct drm_i915_gem_relocation_entry); 3745 int length; /* limited by fault_in_pages_readable() */
3746
3747 /* First check for malicious input causing overflow */
3748 if (exec[i].relocation_count >
3749 INT_MAX / sizeof(struct drm_i915_gem_relocation_entry))
3750 return -EINVAL;
3634 3751
3752 length = exec[i].relocation_count *
3753 sizeof(struct drm_i915_gem_relocation_entry);
3635 if (!access_ok(VERIFY_READ, ptr, length)) 3754 if (!access_ok(VERIFY_READ, ptr, length))
3636 return -EFAULT; 3755 return -EFAULT;
3637 3756
@@ -3774,18 +3893,24 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
3774 } 3893 }
3775 3894
3776 /* Move the objects en-masse into the GTT, evicting if necessary. */ 3895 /* Move the objects en-masse into the GTT, evicting if necessary. */
3777 ret = i915_gem_execbuffer_pin(dev, file, 3896 ret = i915_gem_execbuffer_reserve(dev, file,
3778 object_list, exec_list, 3897 object_list, exec_list,
3779 args->buffer_count); 3898 args->buffer_count);
3780 if (ret) 3899 if (ret)
3781 goto err; 3900 goto err;
3782 3901
3783 /* The objects are in their final locations, apply the relocations. */ 3902 /* The objects are in their final locations, apply the relocations. */
3784 for (i = 0; i < args->buffer_count; i++) { 3903 ret = i915_gem_execbuffer_relocate(dev, file,
3785 struct drm_i915_gem_object *obj = to_intel_bo(object_list[i]); 3904 object_list, exec_list,
3786 obj->base.pending_read_domains = 0; 3905 args->buffer_count);
3787 obj->base.pending_write_domain = 0; 3906 if (ret) {
3788 ret = i915_gem_execbuffer_relocate(obj, file, &exec_list[i]); 3907 if (ret == -EFAULT) {
3908 ret = i915_gem_execbuffer_relocate_slow(dev, file,
3909 object_list,
3910 exec_list,
3911 args->buffer_count);
3912 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
3913 }
3789 if (ret) 3914 if (ret)
3790 goto err; 3915 goto err;
3791 } 3916 }
@@ -4249,10 +4374,20 @@ i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4249 * use this buffer rather sooner than later, so issuing the required 4374 * use this buffer rather sooner than later, so issuing the required
4250 * flush earlier is beneficial. 4375 * flush earlier is beneficial.
4251 */ 4376 */
4252 if (obj->write_domain & I915_GEM_GPU_DOMAINS) 4377 if (obj->write_domain & I915_GEM_GPU_DOMAINS) {
4253 i915_gem_flush_ring(dev, file_priv, 4378 i915_gem_flush_ring(dev, file_priv,
4254 obj_priv->ring, 4379 obj_priv->ring,
4255 0, obj->write_domain); 4380 0, obj->write_domain);
4381 } else if (obj_priv->ring->outstanding_lazy_request) {
4382 /* This ring is not being cleared by active usage,
4383 * so emit a request to do so.
4384 */
4385 u32 seqno = i915_add_request(dev,
4386 NULL, NULL,
4387 obj_priv->ring);
4388 if (seqno == 0)
4389 ret = -ENOMEM;
4390 }
4256 4391
4257 /* Update the active list for the hardware's current position. 4392 /* Update the active list for the hardware's current position.
4258 * Otherwise this only updates on a delayed timer or when irqs 4393 * Otherwise this only updates on a delayed timer or when irqs
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 25ed911a3112..878fc766a12c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3033,6 +3033,7 @@
3033#define TRANS_DP_10BPC (1<<9) 3033#define TRANS_DP_10BPC (1<<9)
3034#define TRANS_DP_6BPC (2<<9) 3034#define TRANS_DP_6BPC (2<<9)
3035#define TRANS_DP_12BPC (3<<9) 3035#define TRANS_DP_12BPC (3<<9)
3036#define TRANS_DP_BPC_MASK (3<<9)
3036#define TRANS_DP_VSYNC_ACTIVE_HIGH (1<<4) 3037#define TRANS_DP_VSYNC_ACTIVE_HIGH (1<<4)
3037#define TRANS_DP_VSYNC_ACTIVE_LOW 0 3038#define TRANS_DP_VSYNC_ACTIVE_LOW 0
3038#define TRANS_DP_HSYNC_ACTIVE_HIGH (1<<3) 3039#define TRANS_DP_HSYNC_ACTIVE_HIGH (1<<3)
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index 454c064f8ef7..42729d25da58 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -239,6 +239,16 @@ static void i915_save_modeset_reg(struct drm_device *dev)
239 if (drm_core_check_feature(dev, DRIVER_MODESET)) 239 if (drm_core_check_feature(dev, DRIVER_MODESET))
240 return; 240 return;
241 241
242 /* Cursor state */
243 dev_priv->saveCURACNTR = I915_READ(CURACNTR);
244 dev_priv->saveCURAPOS = I915_READ(CURAPOS);
245 dev_priv->saveCURABASE = I915_READ(CURABASE);
246 dev_priv->saveCURBCNTR = I915_READ(CURBCNTR);
247 dev_priv->saveCURBPOS = I915_READ(CURBPOS);
248 dev_priv->saveCURBBASE = I915_READ(CURBBASE);
249 if (IS_GEN2(dev))
250 dev_priv->saveCURSIZE = I915_READ(CURSIZE);
251
242 if (HAS_PCH_SPLIT(dev)) { 252 if (HAS_PCH_SPLIT(dev)) {
243 dev_priv->savePCH_DREF_CONTROL = I915_READ(PCH_DREF_CONTROL); 253 dev_priv->savePCH_DREF_CONTROL = I915_READ(PCH_DREF_CONTROL);
244 dev_priv->saveDISP_ARB_CTL = I915_READ(DISP_ARB_CTL); 254 dev_priv->saveDISP_ARB_CTL = I915_READ(DISP_ARB_CTL);
@@ -529,6 +539,16 @@ static void i915_restore_modeset_reg(struct drm_device *dev)
529 I915_WRITE(DSPBCNTR, dev_priv->saveDSPBCNTR); 539 I915_WRITE(DSPBCNTR, dev_priv->saveDSPBCNTR);
530 I915_WRITE(DSPBADDR, I915_READ(DSPBADDR)); 540 I915_WRITE(DSPBADDR, I915_READ(DSPBADDR));
531 541
542 /* Cursor state */
543 I915_WRITE(CURAPOS, dev_priv->saveCURAPOS);
544 I915_WRITE(CURACNTR, dev_priv->saveCURACNTR);
545 I915_WRITE(CURABASE, dev_priv->saveCURABASE);
546 I915_WRITE(CURBPOS, dev_priv->saveCURBPOS);
547 I915_WRITE(CURBCNTR, dev_priv->saveCURBCNTR);
548 I915_WRITE(CURBBASE, dev_priv->saveCURBBASE);
549 if (IS_GEN2(dev))
550 I915_WRITE(CURSIZE, dev_priv->saveCURSIZE);
551
532 return; 552 return;
533} 553}
534 554
@@ -543,16 +563,6 @@ void i915_save_display(struct drm_device *dev)
543 /* Don't save them in KMS mode */ 563 /* Don't save them in KMS mode */
544 i915_save_modeset_reg(dev); 564 i915_save_modeset_reg(dev);
545 565
546 /* Cursor state */
547 dev_priv->saveCURACNTR = I915_READ(CURACNTR);
548 dev_priv->saveCURAPOS = I915_READ(CURAPOS);
549 dev_priv->saveCURABASE = I915_READ(CURABASE);
550 dev_priv->saveCURBCNTR = I915_READ(CURBCNTR);
551 dev_priv->saveCURBPOS = I915_READ(CURBPOS);
552 dev_priv->saveCURBBASE = I915_READ(CURBBASE);
553 if (IS_GEN2(dev))
554 dev_priv->saveCURSIZE = I915_READ(CURSIZE);
555
556 /* CRT state */ 566 /* CRT state */
557 if (HAS_PCH_SPLIT(dev)) { 567 if (HAS_PCH_SPLIT(dev)) {
558 dev_priv->saveADPA = I915_READ(PCH_ADPA); 568 dev_priv->saveADPA = I915_READ(PCH_ADPA);
@@ -657,16 +667,6 @@ void i915_restore_display(struct drm_device *dev)
657 /* Don't restore them in KMS mode */ 667 /* Don't restore them in KMS mode */
658 i915_restore_modeset_reg(dev); 668 i915_restore_modeset_reg(dev);
659 669
660 /* Cursor state */
661 I915_WRITE(CURAPOS, dev_priv->saveCURAPOS);
662 I915_WRITE(CURACNTR, dev_priv->saveCURACNTR);
663 I915_WRITE(CURABASE, dev_priv->saveCURABASE);
664 I915_WRITE(CURBPOS, dev_priv->saveCURBPOS);
665 I915_WRITE(CURBCNTR, dev_priv->saveCURBCNTR);
666 I915_WRITE(CURBBASE, dev_priv->saveCURBBASE);
667 if (IS_GEN2(dev))
668 I915_WRITE(CURSIZE, dev_priv->saveCURSIZE);
669
670 /* CRT state */ 670 /* CRT state */
671 if (HAS_PCH_SPLIT(dev)) 671 if (HAS_PCH_SPLIT(dev))
672 I915_WRITE(PCH_ADPA, dev_priv->saveADPA); 672 I915_WRITE(PCH_ADPA, dev_priv->saveADPA);
diff --git a/drivers/gpu/drm/i915/intel_acpi.c b/drivers/gpu/drm/i915/intel_acpi.c
index 65c88f9ba12c..2cb8e0b9f1ee 100644
--- a/drivers/gpu/drm/i915/intel_acpi.c
+++ b/drivers/gpu/drm/i915/intel_acpi.c
@@ -190,37 +190,6 @@ out:
190 kfree(output.pointer); 190 kfree(output.pointer);
191} 191}
192 192
193static int intel_dsm_switchto(enum vga_switcheroo_client_id id)
194{
195 return 0;
196}
197
198static int intel_dsm_power_state(enum vga_switcheroo_client_id id,
199 enum vga_switcheroo_state state)
200{
201 return 0;
202}
203
204static int intel_dsm_init(void)
205{
206 return 0;
207}
208
209static int intel_dsm_get_client_id(struct pci_dev *pdev)
210{
211 if (intel_dsm_priv.dhandle == DEVICE_ACPI_HANDLE(&pdev->dev))
212 return VGA_SWITCHEROO_IGD;
213 else
214 return VGA_SWITCHEROO_DIS;
215}
216
217static struct vga_switcheroo_handler intel_dsm_handler = {
218 .switchto = intel_dsm_switchto,
219 .power_state = intel_dsm_power_state,
220 .init = intel_dsm_init,
221 .get_client_id = intel_dsm_get_client_id,
222};
223
224static bool intel_dsm_pci_probe(struct pci_dev *pdev) 193static bool intel_dsm_pci_probe(struct pci_dev *pdev)
225{ 194{
226 acpi_handle dhandle, intel_handle; 195 acpi_handle dhandle, intel_handle;
@@ -276,11 +245,8 @@ void intel_register_dsm_handler(void)
276{ 245{
277 if (!intel_dsm_detect()) 246 if (!intel_dsm_detect())
278 return; 247 return;
279
280 vga_switcheroo_register_handler(&intel_dsm_handler);
281} 248}
282 249
283void intel_unregister_dsm_handler(void) 250void intel_unregister_dsm_handler(void)
284{ 251{
285 vga_switcheroo_unregister_handler();
286} 252}
diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index b0b1200ed650..2b2078695d2a 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -270,7 +270,7 @@ parse_general_features(struct drm_i915_private *dev_priv,
270 general->ssc_freq ? 66 : 48; 270 general->ssc_freq ? 66 : 48;
271 else if (IS_GEN5(dev) || IS_GEN6(dev)) 271 else if (IS_GEN5(dev) || IS_GEN6(dev))
272 dev_priv->lvds_ssc_freq = 272 dev_priv->lvds_ssc_freq =
273 general->ssc_freq ? 100 : 120; 273 general->ssc_freq ? 120 : 100;
274 else 274 else
275 dev_priv->lvds_ssc_freq = 275 dev_priv->lvds_ssc_freq =
276 general->ssc_freq ? 100 : 96; 276 general->ssc_freq ? 100 : 96;
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index bee24b1a58e8..d9b7092439ef 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2120,9 +2120,11 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
2120 reg = TRANS_DP_CTL(pipe); 2120 reg = TRANS_DP_CTL(pipe);
2121 temp = I915_READ(reg); 2121 temp = I915_READ(reg);
2122 temp &= ~(TRANS_DP_PORT_SEL_MASK | 2122 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2123 TRANS_DP_SYNC_MASK); 2123 TRANS_DP_SYNC_MASK |
2124 TRANS_DP_BPC_MASK);
2124 temp |= (TRANS_DP_OUTPUT_ENABLE | 2125 temp |= (TRANS_DP_OUTPUT_ENABLE |
2125 TRANS_DP_ENH_FRAMING); 2126 TRANS_DP_ENH_FRAMING);
2127 temp |= TRANS_DP_8BPC;
2126 2128
2127 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) 2129 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2128 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; 2130 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
@@ -2712,27 +2714,19 @@ fdi_reduce_ratio(u32 *num, u32 *den)
2712 } 2714 }
2713} 2715}
2714 2716
2715#define DATA_N 0x800000
2716#define LINK_N 0x80000
2717
2718static void 2717static void
2719ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock, 2718ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
2720 int link_clock, struct fdi_m_n *m_n) 2719 int link_clock, struct fdi_m_n *m_n)
2721{ 2720{
2722 u64 temp;
2723
2724 m_n->tu = 64; /* default size */ 2721 m_n->tu = 64; /* default size */
2725 2722
2726 temp = (u64) DATA_N * pixel_clock; 2723 /* BUG_ON(pixel_clock > INT_MAX / 36); */
2727 temp = div_u64(temp, link_clock); 2724 m_n->gmch_m = bits_per_pixel * pixel_clock;
2728 m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes); 2725 m_n->gmch_n = link_clock * nlanes * 8;
2729 m_n->gmch_m >>= 3; /* convert to bytes_per_pixel */
2730 m_n->gmch_n = DATA_N;
2731 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n); 2726 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
2732 2727
2733 temp = (u64) LINK_N * pixel_clock; 2728 m_n->link_m = pixel_clock;
2734 m_n->link_m = div_u64(temp, link_clock); 2729 m_n->link_n = link_clock;
2735 m_n->link_n = LINK_N;
2736 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n); 2730 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
2737} 2731}
2738 2732
@@ -3716,6 +3710,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
3716 3710
3717 /* FDI link */ 3711 /* FDI link */
3718 if (HAS_PCH_SPLIT(dev)) { 3712 if (HAS_PCH_SPLIT(dev)) {
3713 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
3719 int lane = 0, link_bw, bpp; 3714 int lane = 0, link_bw, bpp;
3720 /* CPU eDP doesn't require FDI link, so just set DP M/N 3715 /* CPU eDP doesn't require FDI link, so just set DP M/N
3721 according to current link config */ 3716 according to current link config */
@@ -3799,6 +3794,8 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
3799 3794
3800 intel_crtc->fdi_lanes = lane; 3795 intel_crtc->fdi_lanes = lane;
3801 3796
3797 if (pixel_multiplier > 1)
3798 link_bw *= pixel_multiplier;
3802 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n); 3799 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
3803 } 3800 }
3804 3801
@@ -5236,6 +5233,55 @@ static const struct drm_crtc_funcs intel_crtc_funcs = {
5236 .page_flip = intel_crtc_page_flip, 5233 .page_flip = intel_crtc_page_flip,
5237}; 5234};
5238 5235
5236static void intel_sanitize_modesetting(struct drm_device *dev,
5237 int pipe, int plane)
5238{
5239 struct drm_i915_private *dev_priv = dev->dev_private;
5240 u32 reg, val;
5241
5242 if (HAS_PCH_SPLIT(dev))
5243 return;
5244
5245 /* Who knows what state these registers were left in by the BIOS or
5246 * grub?
5247 *
5248 * If we leave the registers in a conflicting state (e.g. with the
5249 * display plane reading from the other pipe than the one we intend
5250 * to use) then when we attempt to teardown the active mode, we will
5251 * not disable the pipes and planes in the correct order -- leaving
5252 * a plane reading from a disabled pipe and possibly leading to
5253 * undefined behaviour.
5254 */
5255
5256 reg = DSPCNTR(plane);
5257 val = I915_READ(reg);
5258
5259 if ((val & DISPLAY_PLANE_ENABLE) == 0)
5260 return;
5261 if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
5262 return;
5263
5264 /* This display plane is active and attached to the other CPU pipe. */
5265 pipe = !pipe;
5266
5267 /* Disable the plane and wait for it to stop reading from the pipe. */
5268 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
5269 intel_flush_display_plane(dev, plane);
5270
5271 if (IS_GEN2(dev))
5272 intel_wait_for_vblank(dev, pipe);
5273
5274 if (pipe == 0 && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
5275 return;
5276
5277 /* Switch off the pipe. */
5278 reg = PIPECONF(pipe);
5279 val = I915_READ(reg);
5280 if (val & PIPECONF_ENABLE) {
5281 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
5282 intel_wait_for_pipe_off(dev, pipe);
5283 }
5284}
5239 5285
5240static void intel_crtc_init(struct drm_device *dev, int pipe) 5286static void intel_crtc_init(struct drm_device *dev, int pipe)
5241{ 5287{
@@ -5287,6 +5333,8 @@ static void intel_crtc_init(struct drm_device *dev, int pipe)
5287 5333
5288 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer, 5334 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
5289 (unsigned long)intel_crtc); 5335 (unsigned long)intel_crtc);
5336
5337 intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
5290} 5338}
5291 5339
5292int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, 5340int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
@@ -5336,9 +5384,14 @@ static void intel_setup_outputs(struct drm_device *dev)
5336 struct drm_i915_private *dev_priv = dev->dev_private; 5384 struct drm_i915_private *dev_priv = dev->dev_private;
5337 struct intel_encoder *encoder; 5385 struct intel_encoder *encoder;
5338 bool dpd_is_edp = false; 5386 bool dpd_is_edp = false;
5387 bool has_lvds = false;
5339 5388
5340 if (IS_MOBILE(dev) && !IS_I830(dev)) 5389 if (IS_MOBILE(dev) && !IS_I830(dev))
5341 intel_lvds_init(dev); 5390 has_lvds = intel_lvds_init(dev);
5391 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
5392 /* disable the panel fitter on everything but LVDS */
5393 I915_WRITE(PFIT_CONTROL, 0);
5394 }
5342 5395
5343 if (HAS_PCH_SPLIT(dev)) { 5396 if (HAS_PCH_SPLIT(dev)) {
5344 dpd_is_edp = intel_dpd_is_edp(dev); 5397 dpd_is_edp = intel_dpd_is_edp(dev);
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index c8e005553310..864417cffe9a 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -479,6 +479,7 @@ intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
479 uint16_t address = algo_data->address; 479 uint16_t address = algo_data->address;
480 uint8_t msg[5]; 480 uint8_t msg[5];
481 uint8_t reply[2]; 481 uint8_t reply[2];
482 unsigned retry;
482 int msg_bytes; 483 int msg_bytes;
483 int reply_bytes; 484 int reply_bytes;
484 int ret; 485 int ret;
@@ -513,14 +514,33 @@ intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
513 break; 514 break;
514 } 515 }
515 516
516 for (;;) { 517 for (retry = 0; retry < 5; retry++) {
517 ret = intel_dp_aux_ch(intel_dp, 518 ret = intel_dp_aux_ch(intel_dp,
518 msg, msg_bytes, 519 msg, msg_bytes,
519 reply, reply_bytes); 520 reply, reply_bytes);
520 if (ret < 0) { 521 if (ret < 0) {
521 DRM_DEBUG_KMS("aux_ch failed %d\n", ret); 522 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
522 return ret; 523 return ret;
523 } 524 }
525
526 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
527 case AUX_NATIVE_REPLY_ACK:
528 /* I2C-over-AUX Reply field is only valid
529 * when paired with AUX ACK.
530 */
531 break;
532 case AUX_NATIVE_REPLY_NACK:
533 DRM_DEBUG_KMS("aux_ch native nack\n");
534 return -EREMOTEIO;
535 case AUX_NATIVE_REPLY_DEFER:
536 udelay(100);
537 continue;
538 default:
539 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
540 reply[0]);
541 return -EREMOTEIO;
542 }
543
524 switch (reply[0] & AUX_I2C_REPLY_MASK) { 544 switch (reply[0] & AUX_I2C_REPLY_MASK) {
525 case AUX_I2C_REPLY_ACK: 545 case AUX_I2C_REPLY_ACK:
526 if (mode == MODE_I2C_READ) { 546 if (mode == MODE_I2C_READ) {
@@ -528,17 +548,20 @@ intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
528 } 548 }
529 return reply_bytes - 1; 549 return reply_bytes - 1;
530 case AUX_I2C_REPLY_NACK: 550 case AUX_I2C_REPLY_NACK:
531 DRM_DEBUG_KMS("aux_ch nack\n"); 551 DRM_DEBUG_KMS("aux_i2c nack\n");
532 return -EREMOTEIO; 552 return -EREMOTEIO;
533 case AUX_I2C_REPLY_DEFER: 553 case AUX_I2C_REPLY_DEFER:
534 DRM_DEBUG_KMS("aux_ch defer\n"); 554 DRM_DEBUG_KMS("aux_i2c defer\n");
535 udelay(100); 555 udelay(100);
536 break; 556 break;
537 default: 557 default:
538 DRM_ERROR("aux_ch invalid reply 0x%02x\n", reply[0]); 558 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
539 return -EREMOTEIO; 559 return -EREMOTEIO;
540 } 560 }
541 } 561 }
562
563 DRM_ERROR("too many retries, giving up\n");
564 return -EREMOTEIO;
542} 565}
543 566
544static int 567static int
@@ -584,17 +607,6 @@ intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
584 mode->clock = dev_priv->panel_fixed_mode->clock; 607 mode->clock = dev_priv->panel_fixed_mode->clock;
585 } 608 }
586 609
587 /* Just use VBT values for eDP */
588 if (is_edp(intel_dp)) {
589 intel_dp->lane_count = dev_priv->edp.lanes;
590 intel_dp->link_bw = dev_priv->edp.rate;
591 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
592 DRM_DEBUG_KMS("eDP link bw %02x lane count %d clock %d\n",
593 intel_dp->link_bw, intel_dp->lane_count,
594 adjusted_mode->clock);
595 return true;
596 }
597
598 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) { 610 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
599 for (clock = 0; clock <= max_clock; clock++) { 611 for (clock = 0; clock <= max_clock; clock++) {
600 int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count); 612 int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
@@ -613,6 +625,19 @@ intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
613 } 625 }
614 } 626 }
615 627
628 if (is_edp(intel_dp)) {
629 /* okay we failed just pick the highest */
630 intel_dp->lane_count = max_lane_count;
631 intel_dp->link_bw = bws[max_clock];
632 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
633 DRM_DEBUG_KMS("Force picking display port link bw %02x lane "
634 "count %d clock %d\n",
635 intel_dp->link_bw, intel_dp->lane_count,
636 adjusted_mode->clock);
637
638 return true;
639 }
640
616 return false; 641 return false;
617} 642}
618 643
@@ -1087,21 +1112,11 @@ intel_get_adjust_train(struct intel_dp *intel_dp)
1087} 1112}
1088 1113
1089static uint32_t 1114static uint32_t
1090intel_dp_signal_levels(struct intel_dp *intel_dp) 1115intel_dp_signal_levels(uint8_t train_set, int lane_count)
1091{ 1116{
1092 struct drm_device *dev = intel_dp->base.base.dev; 1117 uint32_t signal_levels = 0;
1093 struct drm_i915_private *dev_priv = dev->dev_private;
1094 uint32_t signal_levels = 0;
1095 u8 train_set = intel_dp->train_set[0];
1096 u32 vswing = train_set & DP_TRAIN_VOLTAGE_SWING_MASK;
1097 u32 preemphasis = train_set & DP_TRAIN_PRE_EMPHASIS_MASK;
1098 1118
1099 if (is_edp(intel_dp)) { 1119 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1100 vswing = dev_priv->edp.vswing;
1101 preemphasis = dev_priv->edp.preemphasis;
1102 }
1103
1104 switch (vswing) {
1105 case DP_TRAIN_VOLTAGE_SWING_400: 1120 case DP_TRAIN_VOLTAGE_SWING_400:
1106 default: 1121 default:
1107 signal_levels |= DP_VOLTAGE_0_4; 1122 signal_levels |= DP_VOLTAGE_0_4;
@@ -1116,7 +1131,7 @@ intel_dp_signal_levels(struct intel_dp *intel_dp)
1116 signal_levels |= DP_VOLTAGE_1_2; 1131 signal_levels |= DP_VOLTAGE_1_2;
1117 break; 1132 break;
1118 } 1133 }
1119 switch (preemphasis) { 1134 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1120 case DP_TRAIN_PRE_EMPHASIS_0: 1135 case DP_TRAIN_PRE_EMPHASIS_0:
1121 default: 1136 default:
1122 signal_levels |= DP_PRE_EMPHASIS_0; 1137 signal_levels |= DP_PRE_EMPHASIS_0;
@@ -1203,18 +1218,6 @@ intel_channel_eq_ok(struct intel_dp *intel_dp)
1203} 1218}
1204 1219
1205static bool 1220static bool
1206intel_dp_aux_handshake_required(struct intel_dp *intel_dp)
1207{
1208 struct drm_device *dev = intel_dp->base.base.dev;
1209 struct drm_i915_private *dev_priv = dev->dev_private;
1210
1211 if (is_edp(intel_dp) && dev_priv->no_aux_handshake)
1212 return false;
1213
1214 return true;
1215}
1216
1217static bool
1218intel_dp_set_link_train(struct intel_dp *intel_dp, 1221intel_dp_set_link_train(struct intel_dp *intel_dp,
1219 uint32_t dp_reg_value, 1222 uint32_t dp_reg_value,
1220 uint8_t dp_train_pat) 1223 uint8_t dp_train_pat)
@@ -1226,9 +1229,6 @@ intel_dp_set_link_train(struct intel_dp *intel_dp,
1226 I915_WRITE(intel_dp->output_reg, dp_reg_value); 1229 I915_WRITE(intel_dp->output_reg, dp_reg_value);
1227 POSTING_READ(intel_dp->output_reg); 1230 POSTING_READ(intel_dp->output_reg);
1228 1231
1229 if (!intel_dp_aux_handshake_required(intel_dp))
1230 return true;
1231
1232 intel_dp_aux_native_write_1(intel_dp, 1232 intel_dp_aux_native_write_1(intel_dp,
1233 DP_TRAINING_PATTERN_SET, 1233 DP_TRAINING_PATTERN_SET,
1234 dp_train_pat); 1234 dp_train_pat);
@@ -1261,11 +1261,10 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
1261 POSTING_READ(intel_dp->output_reg); 1261 POSTING_READ(intel_dp->output_reg);
1262 intel_wait_for_vblank(dev, intel_crtc->pipe); 1262 intel_wait_for_vblank(dev, intel_crtc->pipe);
1263 1263
1264 if (intel_dp_aux_handshake_required(intel_dp)) 1264 /* Write the link configuration data */
1265 /* Write the link configuration data */ 1265 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1266 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET, 1266 intel_dp->link_configuration,
1267 intel_dp->link_configuration, 1267 DP_LINK_CONFIGURATION_SIZE);
1268 DP_LINK_CONFIGURATION_SIZE);
1269 1268
1270 DP |= DP_PORT_EN; 1269 DP |= DP_PORT_EN;
1271 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) 1270 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
@@ -1283,7 +1282,7 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
1283 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]); 1282 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1284 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels; 1283 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1285 } else { 1284 } else {
1286 signal_levels = intel_dp_signal_levels(intel_dp); 1285 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0], intel_dp->lane_count);
1287 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels; 1286 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1288 } 1287 }
1289 1288
@@ -1297,37 +1296,33 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
1297 break; 1296 break;
1298 /* Set training pattern 1 */ 1297 /* Set training pattern 1 */
1299 1298
1300 udelay(500); 1299 udelay(100);
1301 if (intel_dp_aux_handshake_required(intel_dp)) { 1300 if (!intel_dp_get_link_status(intel_dp))
1302 break; 1301 break;
1303 } else {
1304 if (!intel_dp_get_link_status(intel_dp))
1305 break;
1306 1302
1307 if (intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) { 1303 if (intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) {
1308 clock_recovery = true; 1304 clock_recovery = true;
1309 break; 1305 break;
1310 } 1306 }
1311 1307
1312 /* Check to see if we've tried the max voltage */ 1308 /* Check to see if we've tried the max voltage */
1313 for (i = 0; i < intel_dp->lane_count; i++) 1309 for (i = 0; i < intel_dp->lane_count; i++)
1314 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) 1310 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1315 break;
1316 if (i == intel_dp->lane_count)
1317 break; 1311 break;
1312 if (i == intel_dp->lane_count)
1313 break;
1318 1314
1319 /* Check to see if we've tried the same voltage 5 times */ 1315 /* Check to see if we've tried the same voltage 5 times */
1320 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { 1316 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
1321 ++tries; 1317 ++tries;
1322 if (tries == 5) 1318 if (tries == 5)
1323 break; 1319 break;
1324 } else 1320 } else
1325 tries = 0; 1321 tries = 0;
1326 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; 1322 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1327 1323
1328 /* Compute new intel_dp->train_set as requested by target */ 1324 /* Compute new intel_dp->train_set as requested by target */
1329 intel_get_adjust_train(intel_dp); 1325 intel_get_adjust_train(intel_dp);
1330 }
1331 } 1326 }
1332 1327
1333 intel_dp->DP = DP; 1328 intel_dp->DP = DP;
@@ -1354,7 +1349,7 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
1354 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]); 1349 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1355 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels; 1350 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1356 } else { 1351 } else {
1357 signal_levels = intel_dp_signal_levels(intel_dp); 1352 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0], intel_dp->lane_count);
1358 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels; 1353 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1359 } 1354 }
1360 1355
@@ -1368,28 +1363,24 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
1368 DP_TRAINING_PATTERN_2)) 1363 DP_TRAINING_PATTERN_2))
1369 break; 1364 break;
1370 1365
1371 udelay(500); 1366 udelay(400);
1372 1367 if (!intel_dp_get_link_status(intel_dp))
1373 if (!intel_dp_aux_handshake_required(intel_dp)) {
1374 break; 1368 break;
1375 } else {
1376 if (!intel_dp_get_link_status(intel_dp))
1377 break;
1378 1369
1379 if (intel_channel_eq_ok(intel_dp)) { 1370 if (intel_channel_eq_ok(intel_dp)) {
1380 channel_eq = true; 1371 channel_eq = true;
1381 break; 1372 break;
1382 } 1373 }
1383 1374
1384 /* Try 5 times */ 1375 /* Try 5 times */
1385 if (tries > 5) 1376 if (tries > 5)
1386 break; 1377 break;
1387 1378
1388 /* Compute new intel_dp->train_set as requested by target */ 1379 /* Compute new intel_dp->train_set as requested by target */
1389 intel_get_adjust_train(intel_dp); 1380 intel_get_adjust_train(intel_dp);
1390 ++tries; 1381 ++tries;
1391 }
1392 } 1382 }
1383
1393 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) 1384 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1394 reg = DP | DP_LINK_TRAIN_OFF_CPT; 1385 reg = DP | DP_LINK_TRAIN_OFF_CPT;
1395 else 1386 else
@@ -1408,6 +1399,9 @@ intel_dp_link_down(struct intel_dp *intel_dp)
1408 struct drm_i915_private *dev_priv = dev->dev_private; 1399 struct drm_i915_private *dev_priv = dev->dev_private;
1409 uint32_t DP = intel_dp->DP; 1400 uint32_t DP = intel_dp->DP;
1410 1401
1402 if ((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)
1403 return;
1404
1411 DRM_DEBUG_KMS("\n"); 1405 DRM_DEBUG_KMS("\n");
1412 1406
1413 if (is_edp(intel_dp)) { 1407 if (is_edp(intel_dp)) {
@@ -1430,6 +1424,28 @@ intel_dp_link_down(struct intel_dp *intel_dp)
1430 1424
1431 if (is_edp(intel_dp)) 1425 if (is_edp(intel_dp))
1432 DP |= DP_LINK_TRAIN_OFF; 1426 DP |= DP_LINK_TRAIN_OFF;
1427
1428 if (!HAS_PCH_CPT(dev) &&
1429 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
1430 struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
1431 /* Hardware workaround: leaving our transcoder select
1432 * set to transcoder B while it's off will prevent the
1433 * corresponding HDMI output on transcoder A.
1434 *
1435 * Combine this with another hardware workaround:
1436 * transcoder select bit can only be cleared while the
1437 * port is enabled.
1438 */
1439 DP &= ~DP_PIPEB_SELECT;
1440 I915_WRITE(intel_dp->output_reg, DP);
1441
1442 /* Changes to enable or select take place the vblank
1443 * after being written.
1444 */
1445 intel_wait_for_vblank(intel_dp->base.base.dev,
1446 intel_crtc->pipe);
1447 }
1448
1433 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); 1449 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
1434 POSTING_READ(intel_dp->output_reg); 1450 POSTING_READ(intel_dp->output_reg);
1435} 1451}
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 21551fe74541..e52c6125bb1f 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -237,7 +237,7 @@ extern bool intel_sdvo_init(struct drm_device *dev, int output_device);
237extern void intel_dvo_init(struct drm_device *dev); 237extern void intel_dvo_init(struct drm_device *dev);
238extern void intel_tv_init(struct drm_device *dev); 238extern void intel_tv_init(struct drm_device *dev);
239extern void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj); 239extern void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj);
240extern void intel_lvds_init(struct drm_device *dev); 240extern bool intel_lvds_init(struct drm_device *dev);
241extern void intel_dp_init(struct drm_device *dev, int dp_reg); 241extern void intel_dp_init(struct drm_device *dev, int dp_reg);
242void 242void
243intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode, 243intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index 4324a326f98e..25bcedf386fd 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -68,7 +68,7 @@ static struct intel_lvds *intel_attached_lvds(struct drm_connector *connector)
68/** 68/**
69 * Sets the power state for the panel. 69 * Sets the power state for the panel.
70 */ 70 */
71static void intel_lvds_set_power(struct intel_lvds *intel_lvds, bool on) 71static void intel_lvds_enable(struct intel_lvds *intel_lvds)
72{ 72{
73 struct drm_device *dev = intel_lvds->base.base.dev; 73 struct drm_device *dev = intel_lvds->base.base.dev;
74 struct drm_i915_private *dev_priv = dev->dev_private; 74 struct drm_i915_private *dev_priv = dev->dev_private;
@@ -82,26 +82,61 @@ static void intel_lvds_set_power(struct intel_lvds *intel_lvds, bool on)
82 lvds_reg = LVDS; 82 lvds_reg = LVDS;
83 } 83 }
84 84
85 if (on) { 85 I915_WRITE(lvds_reg, I915_READ(lvds_reg) | LVDS_PORT_EN);
86 I915_WRITE(lvds_reg, I915_READ(lvds_reg) | LVDS_PORT_EN);
87 I915_WRITE(ctl_reg, I915_READ(ctl_reg) | POWER_TARGET_ON);
88 intel_panel_set_backlight(dev, dev_priv->backlight_level);
89 } else {
90 dev_priv->backlight_level = intel_panel_get_backlight(dev);
91
92 intel_panel_set_backlight(dev, 0);
93 I915_WRITE(ctl_reg, I915_READ(ctl_reg) & ~POWER_TARGET_ON);
94 86
95 if (intel_lvds->pfit_control) { 87 if (intel_lvds->pfit_dirty) {
96 if (wait_for((I915_READ(PP_STATUS) & PP_ON) == 0, 1000)) 88 /*
97 DRM_ERROR("timed out waiting for panel to power off\n"); 89 * Enable automatic panel scaling so that non-native modes
98 I915_WRITE(PFIT_CONTROL, 0); 90 * fill the screen. The panel fitter should only be
99 intel_lvds->pfit_control = 0; 91 * adjusted whilst the pipe is disabled, according to
92 * register description and PRM.
93 */
94 DRM_DEBUG_KMS("applying panel-fitter: %x, %x\n",
95 intel_lvds->pfit_control,
96 intel_lvds->pfit_pgm_ratios);
97 if (wait_for((I915_READ(PP_STATUS) & PP_ON) == 0, 1000)) {
98 DRM_ERROR("timed out waiting for panel to power off\n");
99 } else {
100 I915_WRITE(PFIT_PGM_RATIOS, intel_lvds->pfit_pgm_ratios);
101 I915_WRITE(PFIT_CONTROL, intel_lvds->pfit_control);
100 intel_lvds->pfit_dirty = false; 102 intel_lvds->pfit_dirty = false;
101 } 103 }
104 }
105
106 I915_WRITE(ctl_reg, I915_READ(ctl_reg) | POWER_TARGET_ON);
107 POSTING_READ(lvds_reg);
108
109 intel_panel_set_backlight(dev, dev_priv->backlight_level);
110}
111
112static void intel_lvds_disable(struct intel_lvds *intel_lvds)
113{
114 struct drm_device *dev = intel_lvds->base.base.dev;
115 struct drm_i915_private *dev_priv = dev->dev_private;
116 u32 ctl_reg, lvds_reg;
117
118 if (HAS_PCH_SPLIT(dev)) {
119 ctl_reg = PCH_PP_CONTROL;
120 lvds_reg = PCH_LVDS;
121 } else {
122 ctl_reg = PP_CONTROL;
123 lvds_reg = LVDS;
124 }
125
126 dev_priv->backlight_level = intel_panel_get_backlight(dev);
127 intel_panel_set_backlight(dev, 0);
128
129 I915_WRITE(ctl_reg, I915_READ(ctl_reg) & ~POWER_TARGET_ON);
130
131 if (intel_lvds->pfit_control) {
132 if (wait_for((I915_READ(PP_STATUS) & PP_ON) == 0, 1000))
133 DRM_ERROR("timed out waiting for panel to power off\n");
102 134
103 I915_WRITE(lvds_reg, I915_READ(lvds_reg) & ~LVDS_PORT_EN); 135 I915_WRITE(PFIT_CONTROL, 0);
136 intel_lvds->pfit_dirty = true;
104 } 137 }
138
139 I915_WRITE(lvds_reg, I915_READ(lvds_reg) & ~LVDS_PORT_EN);
105 POSTING_READ(lvds_reg); 140 POSTING_READ(lvds_reg);
106} 141}
107 142
@@ -110,9 +145,9 @@ static void intel_lvds_dpms(struct drm_encoder *encoder, int mode)
110 struct intel_lvds *intel_lvds = to_intel_lvds(encoder); 145 struct intel_lvds *intel_lvds = to_intel_lvds(encoder);
111 146
112 if (mode == DRM_MODE_DPMS_ON) 147 if (mode == DRM_MODE_DPMS_ON)
113 intel_lvds_set_power(intel_lvds, true); 148 intel_lvds_enable(intel_lvds);
114 else 149 else
115 intel_lvds_set_power(intel_lvds, false); 150 intel_lvds_disable(intel_lvds);
116 151
117 /* XXX: We never power down the LVDS pairs. */ 152 /* XXX: We never power down the LVDS pairs. */
118} 153}
@@ -411,43 +446,18 @@ static void intel_lvds_commit(struct drm_encoder *encoder)
411 /* Always do a full power on as we do not know what state 446 /* Always do a full power on as we do not know what state
412 * we were left in. 447 * we were left in.
413 */ 448 */
414 intel_lvds_set_power(intel_lvds, true); 449 intel_lvds_enable(intel_lvds);
415} 450}
416 451
417static void intel_lvds_mode_set(struct drm_encoder *encoder, 452static void intel_lvds_mode_set(struct drm_encoder *encoder,
418 struct drm_display_mode *mode, 453 struct drm_display_mode *mode,
419 struct drm_display_mode *adjusted_mode) 454 struct drm_display_mode *adjusted_mode)
420{ 455{
421 struct drm_device *dev = encoder->dev;
422 struct drm_i915_private *dev_priv = dev->dev_private;
423 struct intel_lvds *intel_lvds = to_intel_lvds(encoder);
424
425 /* 456 /*
426 * The LVDS pin pair will already have been turned on in the 457 * The LVDS pin pair will already have been turned on in the
427 * intel_crtc_mode_set since it has a large impact on the DPLL 458 * intel_crtc_mode_set since it has a large impact on the DPLL
428 * settings. 459 * settings.
429 */ 460 */
430
431 if (HAS_PCH_SPLIT(dev))
432 return;
433
434 if (!intel_lvds->pfit_dirty)
435 return;
436
437 /*
438 * Enable automatic panel scaling so that non-native modes fill the
439 * screen. Should be enabled before the pipe is enabled, according to
440 * register description and PRM.
441 */
442 DRM_DEBUG_KMS("applying panel-fitter: %x, %x\n",
443 intel_lvds->pfit_control,
444 intel_lvds->pfit_pgm_ratios);
445 if (wait_for((I915_READ(PP_STATUS) & PP_ON) == 0, 1000))
446 DRM_ERROR("timed out waiting for panel to power off\n");
447
448 I915_WRITE(PFIT_PGM_RATIOS, intel_lvds->pfit_pgm_ratios);
449 I915_WRITE(PFIT_CONTROL, intel_lvds->pfit_control);
450 intel_lvds->pfit_dirty = false;
451} 461}
452 462
453/** 463/**
@@ -837,7 +847,7 @@ static bool intel_lvds_ddc_probe(struct drm_device *dev, u8 pin)
837 * Create the connector, register the LVDS DDC bus, and try to figure out what 847 * Create the connector, register the LVDS DDC bus, and try to figure out what
838 * modes we can display on the LVDS panel (if present). 848 * modes we can display on the LVDS panel (if present).
839 */ 849 */
840void intel_lvds_init(struct drm_device *dev) 850bool intel_lvds_init(struct drm_device *dev)
841{ 851{
842 struct drm_i915_private *dev_priv = dev->dev_private; 852 struct drm_i915_private *dev_priv = dev->dev_private;
843 struct intel_lvds *intel_lvds; 853 struct intel_lvds *intel_lvds;
@@ -853,37 +863,37 @@ void intel_lvds_init(struct drm_device *dev)
853 863
854 /* Skip init on machines we know falsely report LVDS */ 864 /* Skip init on machines we know falsely report LVDS */
855 if (dmi_check_system(intel_no_lvds)) 865 if (dmi_check_system(intel_no_lvds))
856 return; 866 return false;
857 867
858 pin = GMBUS_PORT_PANEL; 868 pin = GMBUS_PORT_PANEL;
859 if (!lvds_is_present_in_vbt(dev, &pin)) { 869 if (!lvds_is_present_in_vbt(dev, &pin)) {
860 DRM_DEBUG_KMS("LVDS is not present in VBT\n"); 870 DRM_DEBUG_KMS("LVDS is not present in VBT\n");
861 return; 871 return false;
862 } 872 }
863 873
864 if (HAS_PCH_SPLIT(dev)) { 874 if (HAS_PCH_SPLIT(dev)) {
865 if ((I915_READ(PCH_LVDS) & LVDS_DETECTED) == 0) 875 if ((I915_READ(PCH_LVDS) & LVDS_DETECTED) == 0)
866 return; 876 return false;
867 if (dev_priv->edp.support) { 877 if (dev_priv->edp.support) {
868 DRM_DEBUG_KMS("disable LVDS for eDP support\n"); 878 DRM_DEBUG_KMS("disable LVDS for eDP support\n");
869 return; 879 return false;
870 } 880 }
871 } 881 }
872 882
873 if (!intel_lvds_ddc_probe(dev, pin)) { 883 if (!intel_lvds_ddc_probe(dev, pin)) {
874 DRM_DEBUG_KMS("LVDS did not respond to DDC probe\n"); 884 DRM_DEBUG_KMS("LVDS did not respond to DDC probe\n");
875 return; 885 return false;
876 } 886 }
877 887
878 intel_lvds = kzalloc(sizeof(struct intel_lvds), GFP_KERNEL); 888 intel_lvds = kzalloc(sizeof(struct intel_lvds), GFP_KERNEL);
879 if (!intel_lvds) { 889 if (!intel_lvds) {
880 return; 890 return false;
881 } 891 }
882 892
883 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); 893 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
884 if (!intel_connector) { 894 if (!intel_connector) {
885 kfree(intel_lvds); 895 kfree(intel_lvds);
886 return; 896 return false;
887 } 897 }
888 898
889 if (!HAS_PCH_SPLIT(dev)) { 899 if (!HAS_PCH_SPLIT(dev)) {
@@ -1026,7 +1036,7 @@ out:
1026 /* keep the LVDS connector */ 1036 /* keep the LVDS connector */
1027 dev_priv->int_lvds_connector = connector; 1037 dev_priv->int_lvds_connector = connector;
1028 drm_sysfs_connector_add(connector); 1038 drm_sysfs_connector_add(connector);
1029 return; 1039 return true;
1030 1040
1031failed: 1041failed:
1032 DRM_DEBUG_KMS("No LVDS modes found, disabling.\n"); 1042 DRM_DEBUG_KMS("No LVDS modes found, disabling.\n");
@@ -1034,4 +1044,5 @@ failed:
1034 drm_encoder_cleanup(encoder); 1044 drm_encoder_cleanup(encoder);
1035 kfree(intel_lvds); 1045 kfree(intel_lvds);
1036 kfree(intel_connector); 1046 kfree(intel_connector);
1047 return false;
1037} 1048}
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index b83306f9244b..31cd7e33e820 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -156,23 +156,25 @@ static int init_ring_common(struct drm_device *dev,
156 156
157 /* G45 ring initialization fails to reset head to zero */ 157 /* G45 ring initialization fails to reset head to zero */
158 if (head != 0) { 158 if (head != 0) {
159 DRM_ERROR("%s head not reset to zero " 159 DRM_DEBUG_KMS("%s head not reset to zero "
160 "ctl %08x head %08x tail %08x start %08x\n", 160 "ctl %08x head %08x tail %08x start %08x\n",
161 ring->name, 161 ring->name,
162 I915_READ_CTL(ring), 162 I915_READ_CTL(ring),
163 I915_READ_HEAD(ring), 163 I915_READ_HEAD(ring),
164 I915_READ_TAIL(ring), 164 I915_READ_TAIL(ring),
165 I915_READ_START(ring)); 165 I915_READ_START(ring));
166 166
167 I915_WRITE_HEAD(ring, 0); 167 I915_WRITE_HEAD(ring, 0);
168 168
169 DRM_ERROR("%s head forced to zero " 169 if (I915_READ_HEAD(ring) & HEAD_ADDR) {
170 "ctl %08x head %08x tail %08x start %08x\n", 170 DRM_ERROR("failed to set %s head to zero "
171 ring->name, 171 "ctl %08x head %08x tail %08x start %08x\n",
172 I915_READ_CTL(ring), 172 ring->name,
173 I915_READ_HEAD(ring), 173 I915_READ_CTL(ring),
174 I915_READ_TAIL(ring), 174 I915_READ_HEAD(ring),
175 I915_READ_START(ring)); 175 I915_READ_TAIL(ring),
176 I915_READ_START(ring));
177 }
176 } 178 }
177 179
178 I915_WRITE_CTL(ring, 180 I915_WRITE_CTL(ring,
@@ -694,20 +696,17 @@ int intel_wait_ring_buffer(struct drm_device *dev,
694 drm_i915_private_t *dev_priv = dev->dev_private; 696 drm_i915_private_t *dev_priv = dev->dev_private;
695 u32 head; 697 u32 head;
696 698
697 head = intel_read_status_page(ring, 4);
698 if (head) {
699 ring->head = head & HEAD_ADDR;
700 ring->space = ring->head - (ring->tail + 8);
701 if (ring->space < 0)
702 ring->space += ring->size;
703 if (ring->space >= n)
704 return 0;
705 }
706
707 trace_i915_ring_wait_begin (dev); 699 trace_i915_ring_wait_begin (dev);
708 end = jiffies + 3 * HZ; 700 end = jiffies + 3 * HZ;
709 do { 701 do {
710 ring->head = I915_READ_HEAD(ring) & HEAD_ADDR; 702 /* If the reported head position has wrapped or hasn't advanced,
703 * fallback to the slow and accurate path.
704 */
705 head = intel_read_status_page(ring, 4);
706 if (head < ring->actual_head)
707 head = I915_READ_HEAD(ring);
708 ring->actual_head = head;
709 ring->head = head & HEAD_ADDR;
711 ring->space = ring->head - (ring->tail + 8); 710 ring->space = ring->head - (ring->tail + 8);
712 if (ring->space < 0) 711 if (ring->space < 0)
713 ring->space += ring->size; 712 ring->space += ring->size;
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 3126c2681983..d2cd0f1efeed 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -30,8 +30,9 @@ struct intel_ring_buffer {
30 struct drm_device *dev; 30 struct drm_device *dev;
31 struct drm_gem_object *gem_object; 31 struct drm_gem_object *gem_object;
32 32
33 unsigned int head; 33 u32 actual_head;
34 unsigned int tail; 34 u32 head;
35 u32 tail;
35 int space; 36 int space;
36 struct intel_hw_status_page status_page; 37 struct intel_hw_status_page status_page;
37 38
diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index de158b76bcd5..27e63abf2a73 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -107,7 +107,8 @@ struct intel_sdvo {
107 * This is set if we treat the device as HDMI, instead of DVI. 107 * This is set if we treat the device as HDMI, instead of DVI.
108 */ 108 */
109 bool is_hdmi; 109 bool is_hdmi;
110 bool has_audio; 110 bool has_hdmi_monitor;
111 bool has_hdmi_audio;
111 112
112 /** 113 /**
113 * This is set if we detect output of sdvo device as LVDS and 114 * This is set if we detect output of sdvo device as LVDS and
@@ -1023,7 +1024,7 @@ static void intel_sdvo_mode_set(struct drm_encoder *encoder,
1023 if (!intel_sdvo_set_target_input(intel_sdvo)) 1024 if (!intel_sdvo_set_target_input(intel_sdvo))
1024 return; 1025 return;
1025 1026
1026 if (intel_sdvo->is_hdmi && 1027 if (intel_sdvo->has_hdmi_monitor &&
1027 !intel_sdvo_set_avi_infoframe(intel_sdvo)) 1028 !intel_sdvo_set_avi_infoframe(intel_sdvo))
1028 return; 1029 return;
1029 1030
@@ -1063,7 +1064,7 @@ static void intel_sdvo_mode_set(struct drm_encoder *encoder,
1063 } 1064 }
1064 if (intel_crtc->pipe == 1) 1065 if (intel_crtc->pipe == 1)
1065 sdvox |= SDVO_PIPE_B_SELECT; 1066 sdvox |= SDVO_PIPE_B_SELECT;
1066 if (intel_sdvo->has_audio) 1067 if (intel_sdvo->has_hdmi_audio)
1067 sdvox |= SDVO_AUDIO_ENABLE; 1068 sdvox |= SDVO_AUDIO_ENABLE;
1068 1069
1069 if (INTEL_INFO(dev)->gen >= 4) { 1070 if (INTEL_INFO(dev)->gen >= 4) {
@@ -1295,55 +1296,14 @@ intel_sdvo_get_edid(struct drm_connector *connector)
1295 return drm_get_edid(connector, &sdvo->ddc); 1296 return drm_get_edid(connector, &sdvo->ddc);
1296} 1297}
1297 1298
1298static struct drm_connector *
1299intel_find_analog_connector(struct drm_device *dev)
1300{
1301 struct drm_connector *connector;
1302 struct intel_sdvo *encoder;
1303
1304 list_for_each_entry(encoder,
1305 &dev->mode_config.encoder_list,
1306 base.base.head) {
1307 if (encoder->base.type == INTEL_OUTPUT_ANALOG) {
1308 list_for_each_entry(connector,
1309 &dev->mode_config.connector_list,
1310 head) {
1311 if (&encoder->base ==
1312 intel_attached_encoder(connector))
1313 return connector;
1314 }
1315 }
1316 }
1317
1318 return NULL;
1319}
1320
1321static int
1322intel_analog_is_connected(struct drm_device *dev)
1323{
1324 struct drm_connector *analog_connector;
1325
1326 analog_connector = intel_find_analog_connector(dev);
1327 if (!analog_connector)
1328 return false;
1329
1330 if (analog_connector->funcs->detect(analog_connector, false) ==
1331 connector_status_disconnected)
1332 return false;
1333
1334 return true;
1335}
1336
1337/* Mac mini hack -- use the same DDC as the analog connector */ 1299/* Mac mini hack -- use the same DDC as the analog connector */
1338static struct edid * 1300static struct edid *
1339intel_sdvo_get_analog_edid(struct drm_connector *connector) 1301intel_sdvo_get_analog_edid(struct drm_connector *connector)
1340{ 1302{
1341 struct drm_i915_private *dev_priv = connector->dev->dev_private; 1303 struct drm_i915_private *dev_priv = connector->dev->dev_private;
1342 1304
1343 if (!intel_analog_is_connected(connector->dev)) 1305 return drm_get_edid(connector,
1344 return NULL; 1306 &dev_priv->gmbus[dev_priv->crt_ddc_pin].adapter);
1345
1346 return drm_get_edid(connector, &dev_priv->gmbus[dev_priv->crt_ddc_pin].adapter);
1347} 1307}
1348 1308
1349enum drm_connector_status 1309enum drm_connector_status
@@ -1388,8 +1348,10 @@ intel_sdvo_hdmi_sink_detect(struct drm_connector *connector)
1388 /* DDC bus is shared, match EDID to connector type */ 1348 /* DDC bus is shared, match EDID to connector type */
1389 if (edid->input & DRM_EDID_INPUT_DIGITAL) { 1349 if (edid->input & DRM_EDID_INPUT_DIGITAL) {
1390 status = connector_status_connected; 1350 status = connector_status_connected;
1391 intel_sdvo->is_hdmi = drm_detect_hdmi_monitor(edid); 1351 if (intel_sdvo->is_hdmi) {
1392 intel_sdvo->has_audio = drm_detect_monitor_audio(edid); 1352 intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid);
1353 intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid);
1354 }
1393 } 1355 }
1394 connector->display_info.raw_edid = NULL; 1356 connector->display_info.raw_edid = NULL;
1395 kfree(edid); 1357 kfree(edid);
@@ -1398,7 +1360,7 @@ intel_sdvo_hdmi_sink_detect(struct drm_connector *connector)
1398 if (status == connector_status_connected) { 1360 if (status == connector_status_connected) {
1399 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); 1361 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
1400 if (intel_sdvo_connector->force_audio) 1362 if (intel_sdvo_connector->force_audio)
1401 intel_sdvo->has_audio = intel_sdvo_connector->force_audio > 0; 1363 intel_sdvo->has_hdmi_audio = intel_sdvo_connector->force_audio > 0;
1402 } 1364 }
1403 1365
1404 return status; 1366 return status;
@@ -1415,10 +1377,12 @@ intel_sdvo_detect(struct drm_connector *connector, bool force)
1415 if (!intel_sdvo_write_cmd(intel_sdvo, 1377 if (!intel_sdvo_write_cmd(intel_sdvo,
1416 SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0)) 1378 SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0))
1417 return connector_status_unknown; 1379 return connector_status_unknown;
1418 if (intel_sdvo->is_tv) { 1380
1419 /* add 30ms delay when the output type is SDVO-TV */ 1381 /* add 30ms delay when the output type might be TV */
1382 if (intel_sdvo->caps.output_flags &
1383 (SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_CVBS0))
1420 mdelay(30); 1384 mdelay(30);
1421 } 1385
1422 if (!intel_sdvo_read_response(intel_sdvo, &response, 2)) 1386 if (!intel_sdvo_read_response(intel_sdvo, &response, 2))
1423 return connector_status_unknown; 1387 return connector_status_unknown;
1424 1388
@@ -1472,8 +1436,10 @@ static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
1472 edid = intel_sdvo_get_analog_edid(connector); 1436 edid = intel_sdvo_get_analog_edid(connector);
1473 1437
1474 if (edid != NULL) { 1438 if (edid != NULL) {
1475 drm_mode_connector_update_edid_property(connector, edid); 1439 if (edid->input & DRM_EDID_INPUT_DIGITAL) {
1476 drm_add_edid_modes(connector, edid); 1440 drm_mode_connector_update_edid_property(connector, edid);
1441 drm_add_edid_modes(connector, edid);
1442 }
1477 connector->display_info.raw_edid = NULL; 1443 connector->display_info.raw_edid = NULL;
1478 kfree(edid); 1444 kfree(edid);
1479 } 1445 }
@@ -1713,12 +1679,12 @@ intel_sdvo_set_property(struct drm_connector *connector,
1713 1679
1714 intel_sdvo_connector->force_audio = val; 1680 intel_sdvo_connector->force_audio = val;
1715 1681
1716 if (val > 0 && intel_sdvo->has_audio) 1682 if (val > 0 && intel_sdvo->has_hdmi_audio)
1717 return 0; 1683 return 0;
1718 if (val < 0 && !intel_sdvo->has_audio) 1684 if (val < 0 && !intel_sdvo->has_hdmi_audio)
1719 return 0; 1685 return 0;
1720 1686
1721 intel_sdvo->has_audio = val > 0; 1687 intel_sdvo->has_hdmi_audio = val > 0;
1722 goto done; 1688 goto done;
1723 } 1689 }
1724 1690
@@ -1942,9 +1908,12 @@ intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv,
1942 speed = mapping->i2c_speed; 1908 speed = mapping->i2c_speed;
1943 } 1909 }
1944 1910
1945 sdvo->i2c = &dev_priv->gmbus[pin].adapter; 1911 if (pin < GMBUS_NUM_PORTS) {
1946 intel_gmbus_set_speed(sdvo->i2c, speed); 1912 sdvo->i2c = &dev_priv->gmbus[pin].adapter;
1947 intel_gmbus_force_bit(sdvo->i2c, true); 1913 intel_gmbus_set_speed(sdvo->i2c, speed);
1914 intel_gmbus_force_bit(sdvo->i2c, true);
1915 } else
1916 sdvo->i2c = &dev_priv->gmbus[GMBUS_PORT_DPB].adapter;
1948} 1917}
1949 1918
1950static bool 1919static bool
@@ -2070,6 +2039,8 @@ intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device)
2070 intel_sdvo_set_colorimetry(intel_sdvo, 2039 intel_sdvo_set_colorimetry(intel_sdvo,
2071 SDVO_COLORIMETRY_RGB256); 2040 SDVO_COLORIMETRY_RGB256);
2072 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA; 2041 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
2042
2043 intel_sdvo_add_hdmi_properties(intel_sdvo_connector);
2073 intel_sdvo->is_hdmi = true; 2044 intel_sdvo->is_hdmi = true;
2074 } 2045 }
2075 intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) | 2046 intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
@@ -2077,8 +2048,6 @@ intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device)
2077 2048
2078 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo); 2049 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
2079 2050
2080 intel_sdvo_add_hdmi_properties(intel_sdvo_connector);
2081
2082 return true; 2051 return true;
2083} 2052}
2084 2053
diff --git a/drivers/gpu/drm/radeon/atom.c b/drivers/gpu/drm/radeon/atom.c
index 8e421f644a54..05efb5b9f13e 100644
--- a/drivers/gpu/drm/radeon/atom.c
+++ b/drivers/gpu/drm/radeon/atom.c
@@ -112,6 +112,7 @@ static uint32_t atom_iio_execute(struct atom_context *ctx, int base,
112 base += 3; 112 base += 3;
113 break; 113 break;
114 case ATOM_IIO_WRITE: 114 case ATOM_IIO_WRITE:
115 (void)ctx->card->ioreg_read(ctx->card, CU16(base + 1));
115 ctx->card->ioreg_write(ctx->card, CU16(base + 1), temp); 116 ctx->card->ioreg_write(ctx->card, CU16(base + 1), temp);
116 base += 3; 117 base += 3;
117 break; 118 break;
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index df2b6f2b35f8..9fbabaa6ee44 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -253,7 +253,8 @@ void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
253 case DRM_MODE_DPMS_SUSPEND: 253 case DRM_MODE_DPMS_SUSPEND:
254 case DRM_MODE_DPMS_OFF: 254 case DRM_MODE_DPMS_OFF:
255 drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id); 255 drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
256 atombios_blank_crtc(crtc, ATOM_ENABLE); 256 if (radeon_crtc->enabled)
257 atombios_blank_crtc(crtc, ATOM_ENABLE);
257 if (ASIC_IS_DCE3(rdev)) 258 if (ASIC_IS_DCE3(rdev))
258 atombios_enable_crtc_memreq(crtc, ATOM_DISABLE); 259 atombios_enable_crtc_memreq(crtc, ATOM_DISABLE);
259 atombios_enable_crtc(crtc, ATOM_DISABLE); 260 atombios_enable_crtc(crtc, ATOM_DISABLE);
@@ -530,7 +531,7 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc,
530 dp_clock = dig_connector->dp_clock; 531 dp_clock = dig_connector->dp_clock;
531 } 532 }
532 } 533 }
533 534#if 0 /* doesn't work properly on some laptops */
534 /* use recommended ref_div for ss */ 535 /* use recommended ref_div for ss */
535 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 536 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
536 if (ss_enabled) { 537 if (ss_enabled) {
@@ -540,7 +541,7 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc,
540 } 541 }
541 } 542 }
542 } 543 }
543 544#endif
544 if (ASIC_IS_AVIVO(rdev)) { 545 if (ASIC_IS_AVIVO(rdev)) {
545 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */ 546 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
546 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1) 547 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index 4dc5b4714c5a..7b337c361a12 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -748,6 +748,8 @@ void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev)
748 unsigned i; 748 unsigned i;
749 u32 tmp; 749 u32 tmp;
750 750
751 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
752
751 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1)); 753 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
752 for (i = 0; i < rdev->usec_timeout; i++) { 754 for (i = 0; i < rdev->usec_timeout; i++) {
753 /* read MC_STATUS */ 755 /* read MC_STATUS */
@@ -1922,7 +1924,6 @@ bool evergreen_gpu_is_lockup(struct radeon_device *rdev)
1922static int evergreen_gpu_soft_reset(struct radeon_device *rdev) 1924static int evergreen_gpu_soft_reset(struct radeon_device *rdev)
1923{ 1925{
1924 struct evergreen_mc_save save; 1926 struct evergreen_mc_save save;
1925 u32 srbm_reset = 0;
1926 u32 grbm_reset = 0; 1927 u32 grbm_reset = 0;
1927 1928
1928 dev_info(rdev->dev, "GPU softreset \n"); 1929 dev_info(rdev->dev, "GPU softreset \n");
@@ -1961,16 +1962,6 @@ static int evergreen_gpu_soft_reset(struct radeon_device *rdev)
1961 udelay(50); 1962 udelay(50);
1962 WREG32(GRBM_SOFT_RESET, 0); 1963 WREG32(GRBM_SOFT_RESET, 0);
1963 (void)RREG32(GRBM_SOFT_RESET); 1964 (void)RREG32(GRBM_SOFT_RESET);
1964
1965 /* reset all the system blocks */
1966 srbm_reset = SRBM_SOFT_RESET_ALL_MASK;
1967
1968 dev_info(rdev->dev, " SRBM_SOFT_RESET=0x%08X\n", srbm_reset);
1969 WREG32(SRBM_SOFT_RESET, srbm_reset);
1970 (void)RREG32(SRBM_SOFT_RESET);
1971 udelay(50);
1972 WREG32(SRBM_SOFT_RESET, 0);
1973 (void)RREG32(SRBM_SOFT_RESET);
1974 /* Wait a little for things to settle down */ 1965 /* Wait a little for things to settle down */
1975 udelay(50); 1966 udelay(50);
1976 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n", 1967 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
@@ -1981,10 +1972,6 @@ static int evergreen_gpu_soft_reset(struct radeon_device *rdev)
1981 RREG32(GRBM_STATUS_SE1)); 1972 RREG32(GRBM_STATUS_SE1));
1982 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n", 1973 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
1983 RREG32(SRBM_STATUS)); 1974 RREG32(SRBM_STATUS));
1984 /* After reset we need to reinit the asic as GPU often endup in an
1985 * incoherent state.
1986 */
1987 atom_asic_init(rdev->mode_info.atom_context);
1988 evergreen_mc_resume(rdev, &save); 1975 evergreen_mc_resume(rdev, &save);
1989 return 0; 1976 return 0;
1990} 1977}
@@ -2596,6 +2583,11 @@ int evergreen_resume(struct radeon_device *rdev)
2596{ 2583{
2597 int r; 2584 int r;
2598 2585
2586 /* reset the asic, the gfx blocks are often in a bad state
2587 * after the driver is unloaded or after a resume
2588 */
2589 if (radeon_asic_reset(rdev))
2590 dev_warn(rdev->dev, "GPU reset failed !\n");
2599 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw, 2591 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
2600 * posting will perform necessary task to bring back GPU into good 2592 * posting will perform necessary task to bring back GPU into good
2601 * shape. 2593 * shape.
@@ -2712,6 +2704,11 @@ int evergreen_init(struct radeon_device *rdev)
2712 r = radeon_atombios_init(rdev); 2704 r = radeon_atombios_init(rdev);
2713 if (r) 2705 if (r)
2714 return r; 2706 return r;
2707 /* reset the asic, the gfx blocks are often in a bad state
2708 * after the driver is unloaded or after a resume
2709 */
2710 if (radeon_asic_reset(rdev))
2711 dev_warn(rdev->dev, "GPU reset failed !\n");
2715 /* Post card if necessary */ 2712 /* Post card if necessary */
2716 if (!evergreen_card_posted(rdev)) { 2713 if (!evergreen_card_posted(rdev)) {
2717 if (!rdev->bios) { 2714 if (!rdev->bios) {
diff --git a/drivers/gpu/drm/radeon/evergreend.h b/drivers/gpu/drm/radeon/evergreend.h
index 113c70cc8b39..a73b53c44359 100644
--- a/drivers/gpu/drm/radeon/evergreend.h
+++ b/drivers/gpu/drm/radeon/evergreend.h
@@ -174,6 +174,7 @@
174#define HDP_NONSURFACE_BASE 0x2C04 174#define HDP_NONSURFACE_BASE 0x2C04
175#define HDP_NONSURFACE_INFO 0x2C08 175#define HDP_NONSURFACE_INFO 0x2C08
176#define HDP_NONSURFACE_SIZE 0x2C0C 176#define HDP_NONSURFACE_SIZE 0x2C0C
177#define HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480
177#define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 178#define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0
178#define HDP_TILING_CONFIG 0x2F3C 179#define HDP_TILING_CONFIG 0x2F3C
179 180
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index a3552594ccc4..9c92db7c896b 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -878,12 +878,15 @@ void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
878 u32 tmp; 878 u32 tmp;
879 879
880 /* flush hdp cache so updates hit vram */ 880 /* flush hdp cache so updates hit vram */
881 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740)) { 881 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
882 !(rdev->flags & RADEON_IS_AGP)) {
882 void __iomem *ptr = (void *)rdev->gart.table.vram.ptr; 883 void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
883 u32 tmp; 884 u32 tmp;
884 885
885 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read 886 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read
886 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL 887 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL
888 * This seems to cause problems on some AGP cards. Just use the old
889 * method for them.
887 */ 890 */
888 WREG32(HDP_DEBUG1, 0); 891 WREG32(HDP_DEBUG1, 0);
889 tmp = readl((void __iomem *)ptr); 892 tmp = readl((void __iomem *)ptr);
@@ -1195,8 +1198,10 @@ void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
1195 mc->vram_end, mc->real_vram_size >> 20); 1198 mc->vram_end, mc->real_vram_size >> 20);
1196 } else { 1199 } else {
1197 u64 base = 0; 1200 u64 base = 0;
1198 if (rdev->flags & RADEON_IS_IGP) 1201 if (rdev->flags & RADEON_IS_IGP) {
1199 base = (RREG32(MC_VM_FB_LOCATION) & 0xFFFF) << 24; 1202 base = RREG32(MC_VM_FB_LOCATION) & 0xFFFF;
1203 base <<= 24;
1204 }
1200 radeon_vram_location(rdev, &rdev->mc, base); 1205 radeon_vram_location(rdev, &rdev->mc, base);
1201 rdev->mc.gtt_base_align = 0; 1206 rdev->mc.gtt_base_align = 0;
1202 radeon_gtt_location(rdev, mc); 1207 radeon_gtt_location(rdev, mc);
@@ -1337,13 +1342,19 @@ bool r600_gpu_is_lockup(struct radeon_device *rdev)
1337 u32 srbm_status; 1342 u32 srbm_status;
1338 u32 grbm_status; 1343 u32 grbm_status;
1339 u32 grbm_status2; 1344 u32 grbm_status2;
1345 struct r100_gpu_lockup *lockup;
1340 int r; 1346 int r;
1341 1347
1348 if (rdev->family >= CHIP_RV770)
1349 lockup = &rdev->config.rv770.lockup;
1350 else
1351 lockup = &rdev->config.r600.lockup;
1352
1342 srbm_status = RREG32(R_000E50_SRBM_STATUS); 1353 srbm_status = RREG32(R_000E50_SRBM_STATUS);
1343 grbm_status = RREG32(R_008010_GRBM_STATUS); 1354 grbm_status = RREG32(R_008010_GRBM_STATUS);
1344 grbm_status2 = RREG32(R_008014_GRBM_STATUS2); 1355 grbm_status2 = RREG32(R_008014_GRBM_STATUS2);
1345 if (!G_008010_GUI_ACTIVE(grbm_status)) { 1356 if (!G_008010_GUI_ACTIVE(grbm_status)) {
1346 r100_gpu_lockup_update(&rdev->config.r300.lockup, &rdev->cp); 1357 r100_gpu_lockup_update(lockup, &rdev->cp);
1347 return false; 1358 return false;
1348 } 1359 }
1349 /* force CP activities */ 1360 /* force CP activities */
@@ -1355,7 +1366,7 @@ bool r600_gpu_is_lockup(struct radeon_device *rdev)
1355 radeon_ring_unlock_commit(rdev); 1366 radeon_ring_unlock_commit(rdev);
1356 } 1367 }
1357 rdev->cp.rptr = RREG32(R600_CP_RB_RPTR); 1368 rdev->cp.rptr = RREG32(R600_CP_RB_RPTR);
1358 return r100_gpu_cp_is_lockup(rdev, &rdev->config.r300.lockup, &rdev->cp); 1369 return r100_gpu_cp_is_lockup(rdev, lockup, &rdev->cp);
1359} 1370}
1360 1371
1361int r600_asic_reset(struct radeon_device *rdev) 1372int r600_asic_reset(struct radeon_device *rdev)
@@ -3483,10 +3494,12 @@ int r600_debugfs_mc_info_init(struct radeon_device *rdev)
3483void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo) 3494void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo)
3484{ 3495{
3485 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read 3496 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read
3486 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL 3497 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL.
3498 * This seems to cause problems on some AGP cards. Just use the old
3499 * method for them.
3487 */ 3500 */
3488 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) && 3501 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
3489 rdev->vram_scratch.ptr) { 3502 rdev->vram_scratch.ptr && !(rdev->flags & RADEON_IS_AGP)) {
3490 void __iomem *ptr = (void *)rdev->vram_scratch.ptr; 3503 void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
3491 u32 tmp; 3504 u32 tmp;
3492 3505
diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c
index 9bebac1ec006..7831e0890210 100644
--- a/drivers/gpu/drm/radeon/r600_cs.c
+++ b/drivers/gpu/drm/radeon/r600_cs.c
@@ -315,11 +315,10 @@ static inline int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i)
315 if (array_mode == V_0280A0_ARRAY_LINEAR_GENERAL) { 315 if (array_mode == V_0280A0_ARRAY_LINEAR_GENERAL) {
316 /* the initial DDX does bad things with the CB size occasionally */ 316 /* the initial DDX does bad things with the CB size occasionally */
317 /* it rounds up height too far for slice tile max but the BO is smaller */ 317 /* it rounds up height too far for slice tile max but the BO is smaller */
318 tmp = (height - 7) * pitch * bpe; 318 /* r600c,g also seem to flush at bad times in some apps resulting in
319 if ((tmp + track->cb_color_bo_offset[i]) > radeon_bo_size(track->cb_color_bo[i])) { 319 * bogus values here. So for linear just allow anything to avoid breaking
320 dev_warn(p->dev, "%s offset[%d] %d %d %lu too big\n", __func__, i, track->cb_color_bo_offset[i], tmp, radeon_bo_size(track->cb_color_bo[i])); 320 * broken userspace.
321 return -EINVAL; 321 */
322 }
323 } else { 322 } else {
324 dev_warn(p->dev, "%s offset[%d] %d %d %lu too big\n", __func__, i, track->cb_color_bo_offset[i], tmp, radeon_bo_size(track->cb_color_bo[i])); 323 dev_warn(p->dev, "%s offset[%d] %d %d %lu too big\n", __func__, i, track->cb_color_bo_offset[i], tmp, radeon_bo_size(track->cb_color_bo[i]));
325 return -EINVAL; 324 return -EINVAL;
diff --git a/drivers/gpu/drm/radeon/r600_reg.h b/drivers/gpu/drm/radeon/r600_reg.h
index d84612ae47e0..33cda016b083 100644
--- a/drivers/gpu/drm/radeon/r600_reg.h
+++ b/drivers/gpu/drm/radeon/r600_reg.h
@@ -86,6 +86,7 @@
86#define R600_HDP_NONSURFACE_BASE 0x2c04 86#define R600_HDP_NONSURFACE_BASE 0x2c04
87 87
88#define R600_BUS_CNTL 0x5420 88#define R600_BUS_CNTL 0x5420
89# define R600_BIOS_ROM_DIS (1 << 1)
89#define R600_CONFIG_CNTL 0x5424 90#define R600_CONFIG_CNTL 0x5424
90#define R600_CONFIG_MEMSIZE 0x5428 91#define R600_CONFIG_MEMSIZE 0x5428
91#define R600_CONFIG_F0_BASE 0x542C 92#define R600_CONFIG_F0_BASE 0x542C
diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c
index 87ead090c7d5..bc5a2c3382d9 100644
--- a/drivers/gpu/drm/radeon/radeon_atombios.c
+++ b/drivers/gpu/drm/radeon/radeon_atombios.c
@@ -98,6 +98,14 @@ static inline struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_dev
98 } 98 }
99 } 99 }
100 100
101 /* some DCE3 boards have bad data for this entry */
102 if (ASIC_IS_DCE3(rdev)) {
103 if ((i == 4) &&
104 (gpio->usClkMaskRegisterIndex == 0x1fda) &&
105 (gpio->sucI2cId.ucAccess == 0x94))
106 gpio->sucI2cId.ucAccess = 0x14;
107 }
108
101 if (gpio->sucI2cId.ucAccess == id) { 109 if (gpio->sucI2cId.ucAccess == id) {
102 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4; 110 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
103 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4; 111 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
@@ -174,6 +182,14 @@ void radeon_atombios_i2c_init(struct radeon_device *rdev)
174 } 182 }
175 } 183 }
176 184
185 /* some DCE3 boards have bad data for this entry */
186 if (ASIC_IS_DCE3(rdev)) {
187 if ((i == 4) &&
188 (gpio->usClkMaskRegisterIndex == 0x1fda) &&
189 (gpio->sucI2cId.ucAccess == 0x94))
190 gpio->sucI2cId.ucAccess = 0x14;
191 }
192
177 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4; 193 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
178 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4; 194 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
179 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4; 195 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
diff --git a/drivers/gpu/drm/radeon/radeon_bios.c b/drivers/gpu/drm/radeon/radeon_bios.c
index 654787ec43f4..8f2c7b50dcf5 100644
--- a/drivers/gpu/drm/radeon/radeon_bios.c
+++ b/drivers/gpu/drm/radeon/radeon_bios.c
@@ -130,6 +130,7 @@ static bool radeon_atrm_get_bios(struct radeon_device *rdev)
130 } 130 }
131 return true; 131 return true;
132} 132}
133
133static bool r700_read_disabled_bios(struct radeon_device *rdev) 134static bool r700_read_disabled_bios(struct radeon_device *rdev)
134{ 135{
135 uint32_t viph_control; 136 uint32_t viph_control;
@@ -143,7 +144,7 @@ static bool r700_read_disabled_bios(struct radeon_device *rdev)
143 bool r; 144 bool r;
144 145
145 viph_control = RREG32(RADEON_VIPH_CONTROL); 146 viph_control = RREG32(RADEON_VIPH_CONTROL);
146 bus_cntl = RREG32(RADEON_BUS_CNTL); 147 bus_cntl = RREG32(R600_BUS_CNTL);
147 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 148 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
148 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 149 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
149 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 150 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
@@ -152,7 +153,7 @@ static bool r700_read_disabled_bios(struct radeon_device *rdev)
152 /* disable VIP */ 153 /* disable VIP */
153 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 154 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
154 /* enable the rom */ 155 /* enable the rom */
155 WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); 156 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
156 /* Disable VGA mode */ 157 /* Disable VGA mode */
157 WREG32(AVIVO_D1VGA_CONTROL, 158 WREG32(AVIVO_D1VGA_CONTROL,
158 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 159 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
@@ -191,7 +192,7 @@ static bool r700_read_disabled_bios(struct radeon_device *rdev)
191 cg_spll_status = RREG32(R600_CG_SPLL_STATUS); 192 cg_spll_status = RREG32(R600_CG_SPLL_STATUS);
192 } 193 }
193 WREG32(RADEON_VIPH_CONTROL, viph_control); 194 WREG32(RADEON_VIPH_CONTROL, viph_control);
194 WREG32(RADEON_BUS_CNTL, bus_cntl); 195 WREG32(R600_BUS_CNTL, bus_cntl);
195 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 196 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
196 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 197 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
197 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 198 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
@@ -216,7 +217,7 @@ static bool r600_read_disabled_bios(struct radeon_device *rdev)
216 bool r; 217 bool r;
217 218
218 viph_control = RREG32(RADEON_VIPH_CONTROL); 219 viph_control = RREG32(RADEON_VIPH_CONTROL);
219 bus_cntl = RREG32(RADEON_BUS_CNTL); 220 bus_cntl = RREG32(R600_BUS_CNTL);
220 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 221 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
221 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 222 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
222 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 223 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
@@ -231,7 +232,7 @@ static bool r600_read_disabled_bios(struct radeon_device *rdev)
231 /* disable VIP */ 232 /* disable VIP */
232 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 233 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
233 /* enable the rom */ 234 /* enable the rom */
234 WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); 235 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
235 /* Disable VGA mode */ 236 /* Disable VGA mode */
236 WREG32(AVIVO_D1VGA_CONTROL, 237 WREG32(AVIVO_D1VGA_CONTROL,
237 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 238 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
@@ -262,7 +263,7 @@ static bool r600_read_disabled_bios(struct radeon_device *rdev)
262 263
263 /* restore regs */ 264 /* restore regs */
264 WREG32(RADEON_VIPH_CONTROL, viph_control); 265 WREG32(RADEON_VIPH_CONTROL, viph_control);
265 WREG32(RADEON_BUS_CNTL, bus_cntl); 266 WREG32(R600_BUS_CNTL, bus_cntl);
266 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 267 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
267 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 268 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
268 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 269 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
diff --git a/drivers/gpu/drm/radeon/radeon_combios.c b/drivers/gpu/drm/radeon/radeon_combios.c
index 3bddea5b5295..137b8075f6e7 100644
--- a/drivers/gpu/drm/radeon/radeon_combios.c
+++ b/drivers/gpu/drm/radeon/radeon_combios.c
@@ -729,7 +729,7 @@ void radeon_combios_i2c_init(struct radeon_device *rdev)
729 clk = RBIOS8(offset + 3 + (i * 5) + 3); 729 clk = RBIOS8(offset + 3 + (i * 5) + 3);
730 data = RBIOS8(offset + 3 + (i * 5) + 4); 730 data = RBIOS8(offset + 3 + (i * 5) + 4);
731 i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 731 i2c = combios_setup_i2c_bus(rdev, DDC_MONID,
732 clk, data); 732 (1 << clk), (1 << data));
733 rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "GPIOPAD_MASK"); 733 rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "GPIOPAD_MASK");
734 break; 734 break;
735 } 735 }
diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c b/drivers/gpu/drm/radeon/radeon_connectors.c
index 3bef9f6d66fd..8afaf7a7459e 100644
--- a/drivers/gpu/drm/radeon/radeon_connectors.c
+++ b/drivers/gpu/drm/radeon/radeon_connectors.c
@@ -1175,6 +1175,8 @@ radeon_add_atom_connector(struct drm_device *dev,
1175 /* no HPD on analog connectors */ 1175 /* no HPD on analog connectors */
1176 radeon_connector->hpd.hpd = RADEON_HPD_NONE; 1176 radeon_connector->hpd.hpd = RADEON_HPD_NONE;
1177 connector->polled = DRM_CONNECTOR_POLL_CONNECT; 1177 connector->polled = DRM_CONNECTOR_POLL_CONNECT;
1178 connector->interlace_allowed = true;
1179 connector->doublescan_allowed = true;
1178 break; 1180 break;
1179 case DRM_MODE_CONNECTOR_DVIA: 1181 case DRM_MODE_CONNECTOR_DVIA:
1180 drm_connector_init(dev, &radeon_connector->base, &radeon_vga_connector_funcs, connector_type); 1182 drm_connector_init(dev, &radeon_connector->base, &radeon_vga_connector_funcs, connector_type);
@@ -1190,6 +1192,8 @@ radeon_add_atom_connector(struct drm_device *dev,
1190 1); 1192 1);
1191 /* no HPD on analog connectors */ 1193 /* no HPD on analog connectors */
1192 radeon_connector->hpd.hpd = RADEON_HPD_NONE; 1194 radeon_connector->hpd.hpd = RADEON_HPD_NONE;
1195 connector->interlace_allowed = true;
1196 connector->doublescan_allowed = true;
1193 break; 1197 break;
1194 case DRM_MODE_CONNECTOR_DVII: 1198 case DRM_MODE_CONNECTOR_DVII:
1195 case DRM_MODE_CONNECTOR_DVID: 1199 case DRM_MODE_CONNECTOR_DVID:
@@ -1226,6 +1230,11 @@ radeon_add_atom_connector(struct drm_device *dev,
1226 rdev->mode_info.load_detect_property, 1230 rdev->mode_info.load_detect_property,
1227 1); 1231 1);
1228 } 1232 }
1233 connector->interlace_allowed = true;
1234 if (connector_type == DRM_MODE_CONNECTOR_DVII)
1235 connector->doublescan_allowed = true;
1236 else
1237 connector->doublescan_allowed = false;
1229 break; 1238 break;
1230 case DRM_MODE_CONNECTOR_HDMIA: 1239 case DRM_MODE_CONNECTOR_HDMIA:
1231 case DRM_MODE_CONNECTOR_HDMIB: 1240 case DRM_MODE_CONNECTOR_HDMIB:
@@ -1256,6 +1265,11 @@ radeon_add_atom_connector(struct drm_device *dev,
1256 0); 1265 0);
1257 } 1266 }
1258 subpixel_order = SubPixelHorizontalRGB; 1267 subpixel_order = SubPixelHorizontalRGB;
1268 connector->interlace_allowed = true;
1269 if (connector_type == DRM_MODE_CONNECTOR_HDMIB)
1270 connector->doublescan_allowed = true;
1271 else
1272 connector->doublescan_allowed = false;
1259 break; 1273 break;
1260 case DRM_MODE_CONNECTOR_DisplayPort: 1274 case DRM_MODE_CONNECTOR_DisplayPort:
1261 case DRM_MODE_CONNECTOR_eDP: 1275 case DRM_MODE_CONNECTOR_eDP:
@@ -1293,6 +1307,9 @@ radeon_add_atom_connector(struct drm_device *dev,
1293 rdev->mode_info.underscan_vborder_property, 1307 rdev->mode_info.underscan_vborder_property,
1294 0); 1308 0);
1295 } 1309 }
1310 connector->interlace_allowed = true;
1311 /* in theory with a DP to VGA converter... */
1312 connector->doublescan_allowed = false;
1296 break; 1313 break;
1297 case DRM_MODE_CONNECTOR_SVIDEO: 1314 case DRM_MODE_CONNECTOR_SVIDEO:
1298 case DRM_MODE_CONNECTOR_Composite: 1315 case DRM_MODE_CONNECTOR_Composite:
@@ -1308,6 +1325,8 @@ radeon_add_atom_connector(struct drm_device *dev,
1308 radeon_atombios_get_tv_info(rdev)); 1325 radeon_atombios_get_tv_info(rdev));
1309 /* no HPD on analog connectors */ 1326 /* no HPD on analog connectors */
1310 radeon_connector->hpd.hpd = RADEON_HPD_NONE; 1327 radeon_connector->hpd.hpd = RADEON_HPD_NONE;
1328 connector->interlace_allowed = false;
1329 connector->doublescan_allowed = false;
1311 break; 1330 break;
1312 case DRM_MODE_CONNECTOR_LVDS: 1331 case DRM_MODE_CONNECTOR_LVDS:
1313 radeon_dig_connector = kzalloc(sizeof(struct radeon_connector_atom_dig), GFP_KERNEL); 1332 radeon_dig_connector = kzalloc(sizeof(struct radeon_connector_atom_dig), GFP_KERNEL);
@@ -1326,6 +1345,8 @@ radeon_add_atom_connector(struct drm_device *dev,
1326 dev->mode_config.scaling_mode_property, 1345 dev->mode_config.scaling_mode_property,
1327 DRM_MODE_SCALE_FULLSCREEN); 1346 DRM_MODE_SCALE_FULLSCREEN);
1328 subpixel_order = SubPixelHorizontalRGB; 1347 subpixel_order = SubPixelHorizontalRGB;
1348 connector->interlace_allowed = false;
1349 connector->doublescan_allowed = false;
1329 break; 1350 break;
1330 } 1351 }
1331 1352
@@ -1403,6 +1424,8 @@ radeon_add_legacy_connector(struct drm_device *dev,
1403 /* no HPD on analog connectors */ 1424 /* no HPD on analog connectors */
1404 radeon_connector->hpd.hpd = RADEON_HPD_NONE; 1425 radeon_connector->hpd.hpd = RADEON_HPD_NONE;
1405 connector->polled = DRM_CONNECTOR_POLL_CONNECT; 1426 connector->polled = DRM_CONNECTOR_POLL_CONNECT;
1427 connector->interlace_allowed = true;
1428 connector->doublescan_allowed = true;
1406 break; 1429 break;
1407 case DRM_MODE_CONNECTOR_DVIA: 1430 case DRM_MODE_CONNECTOR_DVIA:
1408 drm_connector_init(dev, &radeon_connector->base, &radeon_vga_connector_funcs, connector_type); 1431 drm_connector_init(dev, &radeon_connector->base, &radeon_vga_connector_funcs, connector_type);
@@ -1418,6 +1441,8 @@ radeon_add_legacy_connector(struct drm_device *dev,
1418 1); 1441 1);
1419 /* no HPD on analog connectors */ 1442 /* no HPD on analog connectors */
1420 radeon_connector->hpd.hpd = RADEON_HPD_NONE; 1443 radeon_connector->hpd.hpd = RADEON_HPD_NONE;
1444 connector->interlace_allowed = true;
1445 connector->doublescan_allowed = true;
1421 break; 1446 break;
1422 case DRM_MODE_CONNECTOR_DVII: 1447 case DRM_MODE_CONNECTOR_DVII:
1423 case DRM_MODE_CONNECTOR_DVID: 1448 case DRM_MODE_CONNECTOR_DVID:
@@ -1435,6 +1460,11 @@ radeon_add_legacy_connector(struct drm_device *dev,
1435 1); 1460 1);
1436 } 1461 }
1437 subpixel_order = SubPixelHorizontalRGB; 1462 subpixel_order = SubPixelHorizontalRGB;
1463 connector->interlace_allowed = true;
1464 if (connector_type == DRM_MODE_CONNECTOR_DVII)
1465 connector->doublescan_allowed = true;
1466 else
1467 connector->doublescan_allowed = false;
1438 break; 1468 break;
1439 case DRM_MODE_CONNECTOR_SVIDEO: 1469 case DRM_MODE_CONNECTOR_SVIDEO:
1440 case DRM_MODE_CONNECTOR_Composite: 1470 case DRM_MODE_CONNECTOR_Composite:
@@ -1457,6 +1487,8 @@ radeon_add_legacy_connector(struct drm_device *dev,
1457 radeon_combios_get_tv_info(rdev)); 1487 radeon_combios_get_tv_info(rdev));
1458 /* no HPD on analog connectors */ 1488 /* no HPD on analog connectors */
1459 radeon_connector->hpd.hpd = RADEON_HPD_NONE; 1489 radeon_connector->hpd.hpd = RADEON_HPD_NONE;
1490 connector->interlace_allowed = false;
1491 connector->doublescan_allowed = false;
1460 break; 1492 break;
1461 case DRM_MODE_CONNECTOR_LVDS: 1493 case DRM_MODE_CONNECTOR_LVDS:
1462 drm_connector_init(dev, &radeon_connector->base, &radeon_lvds_connector_funcs, connector_type); 1494 drm_connector_init(dev, &radeon_connector->base, &radeon_lvds_connector_funcs, connector_type);
@@ -1470,6 +1502,8 @@ radeon_add_legacy_connector(struct drm_device *dev,
1470 dev->mode_config.scaling_mode_property, 1502 dev->mode_config.scaling_mode_property,
1471 DRM_MODE_SCALE_FULLSCREEN); 1503 DRM_MODE_SCALE_FULLSCREEN);
1472 subpixel_order = SubPixelHorizontalRGB; 1504 subpixel_order = SubPixelHorizontalRGB;
1505 connector->interlace_allowed = false;
1506 connector->doublescan_allowed = false;
1473 break; 1507 break;
1474 } 1508 }
1475 1509
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index d8ac1849180d..501966a13f48 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -286,7 +286,7 @@ void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64
286 mc->mc_vram_size = mc->aper_size; 286 mc->mc_vram_size = mc->aper_size;
287 } 287 }
288 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; 288 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
289 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n", 289 dev_info(rdev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
290 mc->mc_vram_size >> 20, mc->vram_start, 290 mc->mc_vram_size >> 20, mc->vram_start,
291 mc->vram_end, mc->real_vram_size >> 20); 291 mc->vram_end, mc->real_vram_size >> 20);
292} 292}
@@ -323,7 +323,7 @@ void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
323 mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align; 323 mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align;
324 } 324 }
325 mc->gtt_end = mc->gtt_start + mc->gtt_size - 1; 325 mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
326 dev_info(rdev->dev, "GTT: %lluM 0x%08llX - 0x%08llX\n", 326 dev_info(rdev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
327 mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end); 327 mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
328} 328}
329 329
@@ -910,11 +910,6 @@ int radeon_resume_kms(struct drm_device *dev)
910 radeon_pm_resume(rdev); 910 radeon_pm_resume(rdev);
911 radeon_restore_bios_scratch_regs(rdev); 911 radeon_restore_bios_scratch_regs(rdev);
912 912
913 /* turn on display hw */
914 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
915 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
916 }
917
918 radeon_fbdev_set_suspend(rdev, 0); 913 radeon_fbdev_set_suspend(rdev, 0);
919 release_console_sem(); 914 release_console_sem();
920 915
@@ -922,6 +917,10 @@ int radeon_resume_kms(struct drm_device *dev)
922 radeon_hpd_init(rdev); 917 radeon_hpd_init(rdev);
923 /* blat the mode back in */ 918 /* blat the mode back in */
924 drm_helper_resume_force_mode(dev); 919 drm_helper_resume_force_mode(dev);
920 /* turn on display hw */
921 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
922 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
923 }
925 return 0; 924 return 0;
926} 925}
927 926
diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c
index 88e4ea925900..60e689f2d048 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.c
+++ b/drivers/gpu/drm/radeon/radeon_drv.c
@@ -232,9 +232,28 @@ static struct drm_driver driver_old = {
232 232
233static struct drm_driver kms_driver; 233static struct drm_driver kms_driver;
234 234
235static void radeon_kick_out_firmware_fb(struct pci_dev *pdev)
236{
237 struct apertures_struct *ap;
238 bool primary = false;
239
240 ap = alloc_apertures(1);
241 ap->ranges[0].base = pci_resource_start(pdev, 0);
242 ap->ranges[0].size = pci_resource_len(pdev, 0);
243
244#ifdef CONFIG_X86
245 primary = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
246#endif
247 remove_conflicting_framebuffers(ap, "radeondrmfb", primary);
248 kfree(ap);
249}
250
235static int __devinit 251static int __devinit
236radeon_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 252radeon_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
237{ 253{
254 /* Get rid of things like offb */
255 radeon_kick_out_firmware_fb(pdev);
256
238 return drm_get_pci_dev(pdev, ent, &kms_driver); 257 return drm_get_pci_dev(pdev, ent, &kms_driver);
239} 258}
240 259
diff --git a/drivers/gpu/drm/radeon/radeon_fb.c b/drivers/gpu/drm/radeon/radeon_fb.c
index efa211898fe6..6abea32be5e8 100644
--- a/drivers/gpu/drm/radeon/radeon_fb.c
+++ b/drivers/gpu/drm/radeon/radeon_fb.c
@@ -245,7 +245,7 @@ static int radeonfb_create(struct radeon_fbdev *rfbdev,
245 goto out_unref; 245 goto out_unref;
246 } 246 }
247 info->apertures->ranges[0].base = rdev->ddev->mode_config.fb_base; 247 info->apertures->ranges[0].base = rdev->ddev->mode_config.fb_base;
248 info->apertures->ranges[0].size = rdev->mc.real_vram_size; 248 info->apertures->ranges[0].size = rdev->mc.aper_size;
249 249
250 info->fix.mmio_start = 0; 250 info->fix.mmio_start = 0;
251 info->fix.mmio_len = 0; 251 info->fix.mmio_len = 0;
diff --git a/drivers/gpu/drm/radeon/radeon_object.c b/drivers/gpu/drm/radeon/radeon_object.c
index 1d067743fee0..a598d0049aa5 100644
--- a/drivers/gpu/drm/radeon/radeon_object.c
+++ b/drivers/gpu/drm/radeon/radeon_object.c
@@ -69,7 +69,7 @@ void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
69 u32 c = 0; 69 u32 c = 0;
70 70
71 rbo->placement.fpfn = 0; 71 rbo->placement.fpfn = 0;
72 rbo->placement.lpfn = rbo->rdev->mc.active_vram_size >> PAGE_SHIFT; 72 rbo->placement.lpfn = 0;
73 rbo->placement.placement = rbo->placements; 73 rbo->placement.placement = rbo->placements;
74 rbo->placement.busy_placement = rbo->placements; 74 rbo->placement.busy_placement = rbo->placements;
75 if (domain & RADEON_GEM_DOMAIN_VRAM) 75 if (domain & RADEON_GEM_DOMAIN_VRAM)
@@ -91,7 +91,8 @@ int radeon_bo_create(struct radeon_device *rdev, struct drm_gem_object *gobj,
91{ 91{
92 struct radeon_bo *bo; 92 struct radeon_bo *bo;
93 enum ttm_bo_type type; 93 enum ttm_bo_type type;
94 int page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT; 94 unsigned long page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT;
95 unsigned long max_size = 0;
95 int r; 96 int r;
96 97
97 if (unlikely(rdev->mman.bdev.dev_mapping == NULL)) { 98 if (unlikely(rdev->mman.bdev.dev_mapping == NULL)) {
@@ -104,6 +105,14 @@ int radeon_bo_create(struct radeon_device *rdev, struct drm_gem_object *gobj,
104 } 105 }
105 *bo_ptr = NULL; 106 *bo_ptr = NULL;
106 107
108 /* maximun bo size is the minimun btw visible vram and gtt size */
109 max_size = min(rdev->mc.visible_vram_size, rdev->mc.gtt_size);
110 if ((page_align << PAGE_SHIFT) >= max_size) {
111 printk(KERN_WARNING "%s:%d alloc size %ldM bigger than %ldMb limit\n",
112 __func__, __LINE__, page_align >> (20 - PAGE_SHIFT), max_size >> 20);
113 return -ENOMEM;
114 }
115
107retry: 116retry:
108 bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL); 117 bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL);
109 if (bo == NULL) 118 if (bo == NULL)
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-09 01:56:49 -0500