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authorJesse Barnes <jbarnes@virtuousgeek.org>2010-09-10 13:02:13 -0400
committerChris Wilson <chris@chris-wilson.co.uk>2010-09-11 05:49:34 -0400
commitea056c14a269be393468fe3734f6c2319eb23a3f (patch)
tree9b6bd67350af78d4ec646e39c1f71729d425087b /drivers/gpu
parent8b3016c4f4cded41d4d53da6f09f40efd6083f4f (diff)
drm/i915: enable thermal reporting for IPS
Thermal reporting may not be enabled by default on some machines, so enable the appropriate bits to allow IPS to get the data it needs from the CPU thermal device. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'drivers/gpu')
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h4
-rw-r--r--drivers/gpu/drm/i915/intel_display.c4
2 files changed, 8 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index db22a23c65a2..27d20177708f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -928,6 +928,8 @@
928#define CLKCFG_MEM_800 (3 << 4) 928#define CLKCFG_MEM_800 (3 << 4)
929#define CLKCFG_MEM_MASK (7 << 4) 929#define CLKCFG_MEM_MASK (7 << 4)
930 930
931#define TSC1 0x11001
932#define TSE (1<<0)
931#define TR1 0x11006 933#define TR1 0x11006
932#define TSFS 0x11020 934#define TSFS 0x11020
933#define TSFS_SLOPE_MASK 0x0000ff00 935#define TSFS_SLOPE_MASK 0x0000ff00
@@ -1072,6 +1074,8 @@
1072#define MEMSTAT_SRC_CTL_STDBY 3 1074#define MEMSTAT_SRC_CTL_STDBY 3
1073#define RCPREVBSYTUPAVG 0x113b8 1075#define RCPREVBSYTUPAVG 0x113b8
1074#define RCPREVBSYTDNAVG 0x113bc 1076#define RCPREVBSYTDNAVG 0x113bc
1077#define PMMISC 0x11214
1078#define MCPPCE_EN (1<<0) /* enable PM_MSG from PCH->MPC */
1075#define SDEW 0x1124c 1079#define SDEW 0x1124c
1076#define CSIEW0 0x11250 1080#define CSIEW0 0x11250
1077#define CSIEW1 0x11254 1081#define CSIEW1 0x11254
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 2e9191d77127..c6b8292c0708 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5635,6 +5635,10 @@ void ironlake_enable_drps(struct drm_device *dev)
5635 u32 rgvmodectl = I915_READ(MEMMODECTL); 5635 u32 rgvmodectl = I915_READ(MEMMODECTL);
5636 u8 fmax, fmin, fstart, vstart; 5636 u8 fmax, fmin, fstart, vstart;
5637 5637
5638 /* Enable temp reporting */
5639 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
5640 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
5641
5638 /* 100ms RC evaluation intervals */ 5642 /* 100ms RC evaluation intervals */
5639 I915_WRITE(RCUPEI, 100000); 5643 I915_WRITE(RCUPEI, 100000);
5640 I915_WRITE(RCDNEI, 100000); 5644 I915_WRITE(RCDNEI, 100000);