Merge branch 'drm-radeon-testing' of /ssd/git/drm-radeon-next into drm-next-stage

* 'drm-radeon-testing' of /ssd/git/drm-radeon-next:
  drm/radeon: r100/r200 ums: block ability for userspace app to trash 0 page and beyond
  drm/ttm: fix function prototype to match implementation
  drm/radeon: use ALIGN instead of open coding it
  drm/radeon/kms: initialize set_surface_reg reg for rs600 asic

6 files changed, 14 insertions, 3 deletions

diff --git a/drivers/gpu/drm/radeon/r600_blit.c b/drivers/gpu/drm/radeon/r600_blit.c
index 5ea432347589..f4fb88ece2bb 100644
--- a/drivers/gpu/drm/radeon/r600_blit.c
+++ b/drivers/gpu/drm/radeon/r600_blit.c
@@ -49,7 +49,7 @@ set_render_target(drm_radeon_private_t *dev_priv, int format, int w, int h, u64
         RING_LOCALS;
         DRM_DEBUG("\n");
 
-        h = (h + 7) & ~7;
+        h = ALIGN(h, 8);
         if (h < 8)
                 h = 8;
 
diff --git a/drivers/gpu/drm/radeon/r600_blit_kms.c b/drivers/gpu/drm/radeon/r600_blit_kms.c
index de8bbbcfe117..f6c6c77db7e0 100644
--- a/drivers/gpu/drm/radeon/r600_blit_kms.c
+++ b/drivers/gpu/drm/radeon/r600_blit_kms.c
@@ -25,7 +25,7 @@ set_render_target(struct radeon_device *rdev, int format,
         u32 cb_color_info;
         int pitch, slice;
 
-        h = (h + 7) & ~7;
+        h = ALIGN(h, 8);
         if (h < 8)
                 h = 8;
 
@@ -396,7 +396,7 @@ set_default_state(struct radeon_device *rdev)
                                     NUM_ES_STACK_ENTRIES(num_es_stack_entries));
 
         /* emit an IB pointing at default state */
-        dwords = (rdev->r600_blit.state_len + 0xf) & ~0xf;
+        dwords = ALIGN(rdev->r600_blit.state_len, 0x10);
         gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.state_offset;
         radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
         radeon_ring_write(rdev, gpu_addr & 0xFFFFFFFC);
diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h
index 4572a6699884..d3a157b2bcb7 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.h
+++ b/drivers/gpu/drm/radeon/radeon_asic.h
@@ -407,6 +407,8 @@ static struct radeon_asic rs600_asic = {
         .get_pcie_lanes = NULL,
         .set_pcie_lanes = NULL,
         .set_clock_gating = &radeon_atom_set_clock_gating,
+        .set_surface_reg = r100_set_surface_reg,
+        .clear_surface_reg = r100_clear_surface_reg,
         .bandwidth_update = &rs600_bandwidth_update,
         .hpd_init = &rs600_hpd_init,
         .hpd_fini = &rs600_hpd_fini,
diff --git a/drivers/gpu/drm/radeon/radeon_cp.c b/drivers/gpu/drm/radeon/radeon_cp.c
index 06123ba31d31..dc6eba6b96dd 100644
--- a/drivers/gpu/drm/radeon/radeon_cp.c
+++ b/drivers/gpu/drm/radeon/radeon_cp.c
@@ -1644,6 +1644,7 @@ static int radeon_do_resume_cp(struct drm_device *dev, struct drm_file *file_pri
         radeon_cp_load_microcode(dev_priv);
         radeon_cp_init_ring_buffer(dev, dev_priv, file_priv);
 
+        dev_priv->have_z_offset = 0;
         radeon_do_engine_reset(dev);
         radeon_irq_set_state(dev, RADEON_SW_INT_ENABLE, 1);
 
diff --git a/drivers/gpu/drm/radeon/radeon_drv.h b/drivers/gpu/drm/radeon/radeon_drv.h
index 88f4d8669d84..cf911859eac2 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.h
+++ b/drivers/gpu/drm/radeon/radeon_drv.h
@@ -268,6 +268,8 @@ typedef struct drm_radeon_private {
 
         u32 scratch_ages[5];
 
+        int have_z_offset;
+
         /* starting from here on, data is preserved accross an open */
         uint32_t flags;         /* see radeon_chip_flags */
         resource_size_t fb_aper_offset;
diff --git a/drivers/gpu/drm/radeon/radeon_state.c b/drivers/gpu/drm/radeon/radeon_state.c
index 32971b8272cf..3c32f840dcd2 100644
--- a/drivers/gpu/drm/radeon/radeon_state.c
+++ b/drivers/gpu/drm/radeon/radeon_state.c
@@ -105,6 +105,7 @@ static __inline__ int radeon_check_and_fixup_packets(drm_radeon_private_t *
                         DRM_ERROR("Invalid depth buffer offset\n");
                         return -EINVAL;
                 }
+                dev_priv->have_z_offset = 1;
                 break;
 
         case RADEON_EMIT_PP_CNTL:
@@ -898,6 +899,11 @@ static void radeon_cp_dispatch_clear(struct drm_device * dev,
                 if (tmp & RADEON_BACK)
                         flags |= RADEON_FRONT;
         }
+        if (flags & (RADEON_DEPTH|RADEON_STENCIL)) {
+                if (!dev_priv->have_z_offset)
+                        printk_once(KERN_ERR "radeon: illegal depth clear request. Buggy mesa detected - please update.\n");
+                flags &= ~(RADEON_DEPTH | RADEON_STENCIL);
+        }
 
         if (flags & (RADEON_FRONT | RADEON_BACK)) {