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authorAlex Deucher <alexdeucher@gmail.com>2010-09-30 19:16:03 -0400
committerDave Airlie <airlied@redhat.com>2010-10-05 21:46:21 -0400
commitf981d4633a29261587e46bbf77bf29aeb2f9666a (patch)
tree824d6eb684a31245f3cc9b1529dec118a010bd31 /drivers/gpu/drm
parent5bccf5e32f010ac4d99e1eafb8669cfb35a0889a (diff)
drm/radeon/kms: properly handle 40 bit MC addresses in the cursor code
Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm')
-rw-r--r--drivers/gpu/drm/radeon/radeon_cursor.c15
1 files changed, 9 insertions, 6 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_cursor.c b/drivers/gpu/drm/radeon/radeon_cursor.c
index 5731fc9b1ae3..4a8102512db5 100644
--- a/drivers/gpu/drm/radeon/radeon_cursor.c
+++ b/drivers/gpu/drm/radeon/radeon_cursor.c
@@ -118,22 +118,25 @@ static void radeon_show_cursor(struct drm_crtc *crtc)
118} 118}
119 119
120static void radeon_set_cursor(struct drm_crtc *crtc, struct drm_gem_object *obj, 120static void radeon_set_cursor(struct drm_crtc *crtc, struct drm_gem_object *obj,
121 uint32_t gpu_addr) 121 uint64_t gpu_addr)
122{ 122{
123 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 123 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
124 struct radeon_device *rdev = crtc->dev->dev_private; 124 struct radeon_device *rdev = crtc->dev->dev_private;
125 125
126 if (ASIC_IS_DCE4(rdev)) { 126 if (ASIC_IS_DCE4(rdev)) {
127 WREG32(EVERGREEN_CUR_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, 0); 127 WREG32(EVERGREEN_CUR_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
128 WREG32(EVERGREEN_CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset, gpu_addr); 128 upper_32_bits(gpu_addr));
129 WREG32(EVERGREEN_CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
130 gpu_addr & 0xffffffff);
129 } else if (ASIC_IS_AVIVO(rdev)) { 131 } else if (ASIC_IS_AVIVO(rdev)) {
130 if (rdev->family >= CHIP_RV770) { 132 if (rdev->family >= CHIP_RV770) {
131 if (radeon_crtc->crtc_id) 133 if (radeon_crtc->crtc_id)
132 WREG32(R700_D2CUR_SURFACE_ADDRESS_HIGH, 0); 134 WREG32(R700_D2CUR_SURFACE_ADDRESS_HIGH, upper_32_bits(gpu_addr));
133 else 135 else
134 WREG32(R700_D1CUR_SURFACE_ADDRESS_HIGH, 0); 136 WREG32(R700_D1CUR_SURFACE_ADDRESS_HIGH, upper_32_bits(gpu_addr));
135 } 137 }
136 WREG32(AVIVO_D1CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset, gpu_addr); 138 WREG32(AVIVO_D1CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
139 gpu_addr & 0xffffffff);
137 } else { 140 } else {
138 radeon_crtc->legacy_cursor_offset = gpu_addr - radeon_crtc->legacy_display_base_addr; 141 radeon_crtc->legacy_cursor_offset = gpu_addr - radeon_crtc->legacy_display_base_addr;
139 /* offset is from DISP(2)_BASE_ADDRESS */ 142 /* offset is from DISP(2)_BASE_ADDRESS */