diff options
author | Jesse Barnes <jbarnes@virtuousgeek.org> | 2013-03-28 12:55:40 -0400 |
---|---|---|
committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2013-04-02 14:49:18 -0400 |
commit | b2634017b2df5e45567811b5e82eb0c8ce8e5ebd (patch) | |
tree | 46dce4c6907ffbdf0f22f1d02948d5d9d720f413 /drivers/gpu/drm | |
parent | 19332d7aab1e38eb01fb387266f493d335d9931c (diff) |
drm/i915/dp: fix up VLV DP handling v2
Needed to handle pre/post enable/disable paths on VLV and avoid a few
fields that are marked reserved on VLV.
v2: don't set color range or DP PLL fields (Jani)
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm')
-rw-r--r-- | drivers/gpu/drm/i915/intel_dp.c | 11 |
1 files changed, 7 insertions, 4 deletions
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 879aff26ca12..eb783925b28c 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c | |||
@@ -936,7 +936,7 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, | |||
936 | else | 936 | else |
937 | intel_dp->DP |= DP_PLL_FREQ_270MHZ; | 937 | intel_dp->DP |= DP_PLL_FREQ_270MHZ; |
938 | } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) { | 938 | } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) { |
939 | if (!HAS_PCH_SPLIT(dev)) | 939 | if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev)) |
940 | intel_dp->DP |= intel_dp->color_range; | 940 | intel_dp->DP |= intel_dp->color_range; |
941 | 941 | ||
942 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) | 942 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
@@ -951,7 +951,7 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, | |||
951 | if (intel_crtc->pipe == 1) | 951 | if (intel_crtc->pipe == 1) |
952 | intel_dp->DP |= DP_PIPEB_SELECT; | 952 | intel_dp->DP |= DP_PIPEB_SELECT; |
953 | 953 | ||
954 | if (is_cpu_edp(intel_dp)) { | 954 | if (is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) { |
955 | /* don't miss out required setting for eDP */ | 955 | /* don't miss out required setting for eDP */ |
956 | if (adjusted_mode->clock < 200000) | 956 | if (adjusted_mode->clock < 200000) |
957 | intel_dp->DP |= DP_PLL_FREQ_160MHZ; | 957 | intel_dp->DP |= DP_PLL_FREQ_160MHZ; |
@@ -1383,10 +1383,12 @@ static void intel_disable_dp(struct intel_encoder *encoder) | |||
1383 | static void intel_post_disable_dp(struct intel_encoder *encoder) | 1383 | static void intel_post_disable_dp(struct intel_encoder *encoder) |
1384 | { | 1384 | { |
1385 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); | 1385 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
1386 | struct drm_device *dev = encoder->base.dev; | ||
1386 | 1387 | ||
1387 | if (is_cpu_edp(intel_dp)) { | 1388 | if (is_cpu_edp(intel_dp)) { |
1388 | intel_dp_link_down(intel_dp); | 1389 | intel_dp_link_down(intel_dp); |
1389 | ironlake_edp_pll_off(intel_dp); | 1390 | if (!IS_VALLEYVIEW(dev)) |
1391 | ironlake_edp_pll_off(intel_dp); | ||
1390 | } | 1392 | } |
1391 | } | 1393 | } |
1392 | 1394 | ||
@@ -1412,8 +1414,9 @@ static void intel_enable_dp(struct intel_encoder *encoder) | |||
1412 | static void intel_pre_enable_dp(struct intel_encoder *encoder) | 1414 | static void intel_pre_enable_dp(struct intel_encoder *encoder) |
1413 | { | 1415 | { |
1414 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); | 1416 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
1417 | struct drm_device *dev = encoder->base.dev; | ||
1415 | 1418 | ||
1416 | if (is_cpu_edp(intel_dp)) | 1419 | if (is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) |
1417 | ironlake_edp_pll_on(intel_dp); | 1420 | ironlake_edp_pll_on(intel_dp); |
1418 | } | 1421 | } |
1419 | 1422 | ||