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authorChristoph Bumiller <e0425955@student.tuwien.ac.at>2013-03-27 17:16:55 -0400
committerBen Skeggs <bskeggs@redhat.com>2013-04-26 01:37:42 -0400
commit9685482385001613cbed8788d217ec06adc6f711 (patch)
tree1ae68e41a5c1507f1fb66b5b0c0f306c9768db78 /drivers/gpu/drm
parent7e22e71e80fe35592fbc64a0e382108a8ce28495 (diff)
drm/nvc0/gr: add software methods to control some MP regs
Signed-off-by: Christoph Bumiller <e0425955@student.tuwien.ac.at> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm')
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/software/nvc0.c29
1 files changed, 29 insertions, 0 deletions
diff --git a/drivers/gpu/drm/nouveau/core/engine/software/nvc0.c b/drivers/gpu/drm/nouveau/core/engine/software/nvc0.c
index a523eaad47e3..d698e710ddd4 100644
--- a/drivers/gpu/drm/nouveau/core/engine/software/nvc0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/software/nvc0.c
@@ -94,6 +94,32 @@ nvc0_software_mthd_flip(struct nouveau_object *object, u32 mthd,
94 return -EINVAL; 94 return -EINVAL;
95} 95}
96 96
97static int
98nvc0_software_mthd_mp_control(struct nouveau_object *object, u32 mthd,
99 void *args, u32 size)
100{
101 struct nvc0_software_chan *chan = (void *)nv_engctx(object->parent);
102 struct nvc0_software_priv *priv = (void *)nv_object(chan)->engine;
103 u32 data = *(u32 *)args;
104
105 switch (mthd) {
106 case 0x600:
107 nv_wr32(priv, 0x419e00, data); /* MP.PM_UNK000 */
108 break;
109 case 0x644:
110 if (data & ~0x1ffffe)
111 return -EINVAL;
112 nv_wr32(priv, 0x419e44, data); /* MP.TRAP_WARP_ERROR_EN */
113 break;
114 case 0x6ac:
115 nv_wr32(priv, 0x419eac, data); /* MP.PM_UNK0AC */
116 break;
117 default:
118 return -EINVAL;
119 }
120 return 0;
121}
122
97static struct nouveau_omthds 123static struct nouveau_omthds
98nvc0_software_omthds[] = { 124nvc0_software_omthds[] = {
99 { 0x0400, 0x0400, nvc0_software_mthd_vblsem_offset }, 125 { 0x0400, 0x0400, nvc0_software_mthd_vblsem_offset },
@@ -101,6 +127,9 @@ nvc0_software_omthds[] = {
101 { 0x0408, 0x0408, nvc0_software_mthd_vblsem_value }, 127 { 0x0408, 0x0408, nvc0_software_mthd_vblsem_value },
102 { 0x040c, 0x040c, nvc0_software_mthd_vblsem_release }, 128 { 0x040c, 0x040c, nvc0_software_mthd_vblsem_release },
103 { 0x0500, 0x0500, nvc0_software_mthd_flip }, 129 { 0x0500, 0x0500, nvc0_software_mthd_flip },
130 { 0x0600, 0x0600, nvc0_software_mthd_mp_control },
131 { 0x0644, 0x0644, nvc0_software_mthd_mp_control },
132 { 0x06ac, 0x06ac, nvc0_software_mthd_mp_control },
104 {} 133 {}
105}; 134};
106 135