diff options
author | Paulo Zanoni <paulo.r.zanoni@intel.com> | 2013-02-18 17:00:23 -0500 |
---|---|---|
committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2013-02-19 19:33:45 -0500 |
commit | 22b8bf17c6c1db887e3e9adb0778d6f03e621e66 (patch) | |
tree | b2a45dbf777f5cc0d8c370128a81d1983781cdf3 /drivers/gpu/drm | |
parent | 9ed9809fbee47cb21c5d40e0a6f46101150cc4d4 (diff) |
drm/i915: use HAS_DDI on intel_hdmi.c and intel_display.c
Since basically every code called on these places comes from
intel_ddi.c
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm')
-rw-r--r-- | drivers/gpu/drm/i915/intel_dp.c | 12 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/intel_hdmi.c | 2 |
2 files changed, 7 insertions, 7 deletions
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 7b8bfe8982e6..770ec90e37a5 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c | |||
@@ -332,7 +332,7 @@ intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq) | |||
332 | uint32_t status; | 332 | uint32_t status; |
333 | bool done; | 333 | bool done; |
334 | 334 | ||
335 | if (IS_HASWELL(dev)) { | 335 | if (HAS_DDI(dev)) { |
336 | switch (intel_dig_port->port) { | 336 | switch (intel_dig_port->port) { |
337 | case PORT_A: | 337 | case PORT_A: |
338 | ch_ctl = DPA_AUX_CH_CTL; | 338 | ch_ctl = DPA_AUX_CH_CTL; |
@@ -387,7 +387,7 @@ intel_dp_aux_ch(struct intel_dp *intel_dp, | |||
387 | */ | 387 | */ |
388 | pm_qos_update_request(&dev_priv->pm_qos, 0); | 388 | pm_qos_update_request(&dev_priv->pm_qos, 0); |
389 | 389 | ||
390 | if (IS_HASWELL(dev)) { | 390 | if (HAS_DDI(dev)) { |
391 | switch (intel_dig_port->port) { | 391 | switch (intel_dig_port->port) { |
392 | case PORT_A: | 392 | case PORT_A: |
393 | ch_ctl = DPA_AUX_CH_CTL; | 393 | ch_ctl = DPA_AUX_CH_CTL; |
@@ -842,7 +842,7 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode, | |||
842 | intel_link_compute_m_n(intel_crtc->bpp, lane_count, | 842 | intel_link_compute_m_n(intel_crtc->bpp, lane_count, |
843 | mode->clock, adjusted_mode->clock, &m_n); | 843 | mode->clock, adjusted_mode->clock, &m_n); |
844 | 844 | ||
845 | if (IS_HASWELL(dev)) { | 845 | if (HAS_DDI(dev)) { |
846 | I915_WRITE(PIPE_DATA_M1(cpu_transcoder), | 846 | I915_WRITE(PIPE_DATA_M1(cpu_transcoder), |
847 | TU_SIZE(m_n.tu) | m_n.gmch_m); | 847 | TU_SIZE(m_n.tu) | m_n.gmch_m); |
848 | I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n); | 848 | I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n); |
@@ -1537,7 +1537,7 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing) | |||
1537 | { | 1537 | { |
1538 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | 1538 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1539 | 1539 | ||
1540 | if (IS_HASWELL(dev)) { | 1540 | if (HAS_DDI(dev)) { |
1541 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { | 1541 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
1542 | case DP_TRAIN_VOLTAGE_SWING_400: | 1542 | case DP_TRAIN_VOLTAGE_SWING_400: |
1543 | return DP_TRAIN_PRE_EMPHASIS_9_5; | 1543 | return DP_TRAIN_PRE_EMPHASIS_9_5; |
@@ -1745,7 +1745,7 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP) | |||
1745 | uint32_t signal_levels, mask; | 1745 | uint32_t signal_levels, mask; |
1746 | uint8_t train_set = intel_dp->train_set[0]; | 1746 | uint8_t train_set = intel_dp->train_set[0]; |
1747 | 1747 | ||
1748 | if (IS_HASWELL(dev)) { | 1748 | if (HAS_DDI(dev)) { |
1749 | signal_levels = intel_hsw_signal_levels(train_set); | 1749 | signal_levels = intel_hsw_signal_levels(train_set); |
1750 | mask = DDI_BUF_EMP_MASK; | 1750 | mask = DDI_BUF_EMP_MASK; |
1751 | } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) { | 1751 | } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) { |
@@ -1776,7 +1776,7 @@ intel_dp_set_link_train(struct intel_dp *intel_dp, | |||
1776 | int ret; | 1776 | int ret; |
1777 | uint32_t temp; | 1777 | uint32_t temp; |
1778 | 1778 | ||
1779 | if (IS_HASWELL(dev)) { | 1779 | if (HAS_DDI(dev)) { |
1780 | temp = I915_READ(DP_TP_CTL(port)); | 1780 | temp = I915_READ(DP_TP_CTL(port)); |
1781 | 1781 | ||
1782 | if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE) | 1782 | if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE) |
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index 5a6138c62fe9..ed65c6ddf5a2 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c | |||
@@ -1044,7 +1044,7 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, | |||
1044 | } else if (IS_VALLEYVIEW(dev)) { | 1044 | } else if (IS_VALLEYVIEW(dev)) { |
1045 | intel_hdmi->write_infoframe = vlv_write_infoframe; | 1045 | intel_hdmi->write_infoframe = vlv_write_infoframe; |
1046 | intel_hdmi->set_infoframes = vlv_set_infoframes; | 1046 | intel_hdmi->set_infoframes = vlv_set_infoframes; |
1047 | } else if (IS_HASWELL(dev)) { | 1047 | } else if (HAS_DDI(dev)) { |
1048 | intel_hdmi->write_infoframe = hsw_write_infoframe; | 1048 | intel_hdmi->write_infoframe = hsw_write_infoframe; |
1049 | intel_hdmi->set_infoframes = hsw_set_infoframes; | 1049 | intel_hdmi->set_infoframes = hsw_set_infoframes; |
1050 | } else if (HAS_PCH_IBX(dev)) { | 1050 | } else if (HAS_PCH_IBX(dev)) { |