diff options
author | Marek Olšák <maraeo@gmail.com> | 2011-05-06 19:09:57 -0400 |
---|---|---|
committer | Dave Airlie <airlied@redhat.com> | 2011-06-01 20:49:20 -0400 |
commit | fe6f0bd03d697835e76dd18d232ba476c65b8282 (patch) | |
tree | 3654e40f556022a71c905aa07d5f39801a20682f /drivers/gpu/drm/radeon | |
parent | adcfde516e10aad72d66f6fefd36e6d0e6bd7be7 (diff) |
drm/radeon/kms: add missing Evergreen texture formats to the CS parser
BC6 and BC7 are described in ARB_texture_compression_bptc.
No idea what FMT_32_AS_32_32_32_32 is good for.
Signed-off-by: Marek Olšák <maraeo@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon')
-rw-r--r-- | drivers/gpu/drm/radeon/r600_cs.c | 28 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/r600d.h | 3 |
2 files changed, 21 insertions, 10 deletions
diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c index fd18be9871ab..909bda8dd550 100644 --- a/drivers/gpu/drm/radeon/r600_cs.c +++ b/drivers/gpu/drm/radeon/r600_cs.c | |||
@@ -71,20 +71,21 @@ struct r600_cs_track { | |||
71 | u64 db_bo_mc; | 71 | u64 db_bo_mc; |
72 | }; | 72 | }; |
73 | 73 | ||
74 | #define FMT_8_BIT(fmt, vc) [fmt] = { 1, 1, 1, vc } | 74 | #define FMT_8_BIT(fmt, vc) [fmt] = { 1, 1, 1, vc, CHIP_R600 } |
75 | #define FMT_16_BIT(fmt, vc) [fmt] = { 1, 1, 2, vc } | 75 | #define FMT_16_BIT(fmt, vc) [fmt] = { 1, 1, 2, vc, CHIP_R600 } |
76 | #define FMT_24_BIT(fmt) [fmt] = { 1, 1, 3, 0 } | 76 | #define FMT_24_BIT(fmt) [fmt] = { 1, 1, 3, 0, CHIP_R600 } |
77 | #define FMT_32_BIT(fmt, vc) [fmt] = { 1, 1, 4, vc } | 77 | #define FMT_32_BIT(fmt, vc) [fmt] = { 1, 1, 4, vc, CHIP_R600 } |
78 | #define FMT_48_BIT(fmt) [fmt] = { 1, 1, 6, 0 } | 78 | #define FMT_48_BIT(fmt) [fmt] = { 1, 1, 6, 0, CHIP_R600 } |
79 | #define FMT_64_BIT(fmt, vc) [fmt] = { 1, 1, 8, vc } | 79 | #define FMT_64_BIT(fmt, vc) [fmt] = { 1, 1, 8, vc, CHIP_R600 } |
80 | #define FMT_96_BIT(fmt) [fmt] = { 1, 1, 12, 0 } | 80 | #define FMT_96_BIT(fmt) [fmt] = { 1, 1, 12, 0, CHIP_R600 } |
81 | #define FMT_128_BIT(fmt, vc) [fmt] = { 1, 1, 16, vc } | 81 | #define FMT_128_BIT(fmt, vc) [fmt] = { 1, 1, 16,vc, CHIP_R600 } |
82 | 82 | ||
83 | struct gpu_formats { | 83 | struct gpu_formats { |
84 | unsigned blockwidth; | 84 | unsigned blockwidth; |
85 | unsigned blockheight; | 85 | unsigned blockheight; |
86 | unsigned blocksize; | 86 | unsigned blocksize; |
87 | unsigned valid_color; | 87 | unsigned valid_color; |
88 | enum radeon_family min_family; | ||
88 | }; | 89 | }; |
89 | 90 | ||
90 | static const struct gpu_formats color_formats_table[] = { | 91 | static const struct gpu_formats color_formats_table[] = { |
@@ -154,7 +155,11 @@ static const struct gpu_formats color_formats_table[] = { | |||
154 | [V_038004_FMT_BC3] = { 4, 4, 16, 0 }, | 155 | [V_038004_FMT_BC3] = { 4, 4, 16, 0 }, |
155 | [V_038004_FMT_BC4] = { 4, 4, 8, 0 }, | 156 | [V_038004_FMT_BC4] = { 4, 4, 8, 0 }, |
156 | [V_038004_FMT_BC5] = { 4, 4, 16, 0}, | 157 | [V_038004_FMT_BC5] = { 4, 4, 16, 0}, |
158 | [V_038004_FMT_BC6] = { 4, 4, 16, 0, CHIP_CEDAR}, /* Evergreen-only */ | ||
159 | [V_038004_FMT_BC7] = { 4, 4, 16, 0, CHIP_CEDAR}, /* Evergreen-only */ | ||
157 | 160 | ||
161 | /* The other Evergreen formats */ | ||
162 | [V_038004_FMT_32_AS_32_32_32_32] = { 1, 1, 4, 0, CHIP_CEDAR}, | ||
158 | }; | 163 | }; |
159 | 164 | ||
160 | static inline bool fmt_is_valid_color(u32 format) | 165 | static inline bool fmt_is_valid_color(u32 format) |
@@ -168,11 +173,14 @@ static inline bool fmt_is_valid_color(u32 format) | |||
168 | return false; | 173 | return false; |
169 | } | 174 | } |
170 | 175 | ||
171 | static inline bool fmt_is_valid_texture(u32 format) | 176 | static inline bool fmt_is_valid_texture(u32 format, enum radeon_family family) |
172 | { | 177 | { |
173 | if (format >= ARRAY_SIZE(color_formats_table)) | 178 | if (format >= ARRAY_SIZE(color_formats_table)) |
174 | return false; | 179 | return false; |
175 | 180 | ||
181 | if (family < color_formats_table[format].min_family) | ||
182 | return false; | ||
183 | |||
176 | if (color_formats_table[format].blockwidth > 0) | 184 | if (color_formats_table[format].blockwidth > 0) |
177 | return true; | 185 | return true; |
178 | 186 | ||
@@ -1325,7 +1333,7 @@ static inline int r600_check_texture_resource(struct radeon_cs_parser *p, u32 i | |||
1325 | return -EINVAL; | 1333 | return -EINVAL; |
1326 | } | 1334 | } |
1327 | format = G_038004_DATA_FORMAT(word1); | 1335 | format = G_038004_DATA_FORMAT(word1); |
1328 | if (!fmt_is_valid_texture(format)) { | 1336 | if (!fmt_is_valid_texture(format, p->family)) { |
1329 | dev_warn(p->dev, "%s:%d texture invalid format %d\n", | 1337 | dev_warn(p->dev, "%s:%d texture invalid format %d\n", |
1330 | __func__, __LINE__, format); | 1338 | __func__, __LINE__, format); |
1331 | return -EINVAL; | 1339 | return -EINVAL; |
diff --git a/drivers/gpu/drm/radeon/r600d.h b/drivers/gpu/drm/radeon/r600d.h index b2b944bcd05a..f140a0d5cb54 100644 --- a/drivers/gpu/drm/radeon/r600d.h +++ b/drivers/gpu/drm/radeon/r600d.h | |||
@@ -1309,6 +1309,9 @@ | |||
1309 | #define V_038004_FMT_BC3 0x00000033 | 1309 | #define V_038004_FMT_BC3 0x00000033 |
1310 | #define V_038004_FMT_BC4 0x00000034 | 1310 | #define V_038004_FMT_BC4 0x00000034 |
1311 | #define V_038004_FMT_BC5 0x00000035 | 1311 | #define V_038004_FMT_BC5 0x00000035 |
1312 | #define V_038004_FMT_BC6 0x00000036 | ||
1313 | #define V_038004_FMT_BC7 0x00000037 | ||
1314 | #define V_038004_FMT_32_AS_32_32_32_32 0x00000038 | ||
1312 | #define R_038010_SQ_TEX_RESOURCE_WORD4_0 0x038010 | 1315 | #define R_038010_SQ_TEX_RESOURCE_WORD4_0 0x038010 |
1313 | #define S_038010_FORMAT_COMP_X(x) (((x) & 0x3) << 0) | 1316 | #define S_038010_FORMAT_COMP_X(x) (((x) & 0x3) << 0) |
1314 | #define G_038010_FORMAT_COMP_X(x) (((x) >> 0) & 0x3) | 1317 | #define G_038010_FORMAT_COMP_X(x) (((x) >> 0) & 0x3) |