drm/radeon: switch to a finer grained reset for SI (v2)

No change in functionality as we currently set all the reset
flags.

v2: fix typo

Reviewed-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

1 files changed, 65 insertions, 34 deletions

diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index 4bf17334927a..3240a3d64f30 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -2126,15 +2126,13 @@ bool si_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
         return radeon_ring_test_lockup(rdev, ring);
 }
 
-static int si_gpu_soft_reset(struct radeon_device *rdev)
+static void si_gpu_soft_reset_gfx(struct radeon_device *rdev)
 {
-        struct evergreen_mc_save save;
-        u32 grbm_reset = 0, tmp;
+        u32 grbm_reset = 0;
 
         if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
-                return 0;
+                return;
 
-        dev_info(rdev->dev, "GPU softreset \n");
         dev_info(rdev->dev, "  GRBM_STATUS=0x%08X\n",
                 RREG32(GRBM_STATUS));
         dev_info(rdev->dev, "  GRBM_STATUS2=0x%08X\n",
@@ -2145,36 +2143,10 @@ static int si_gpu_soft_reset(struct radeon_device *rdev)
                 RREG32(GRBM_STATUS_SE1));
         dev_info(rdev->dev, "  SRBM_STATUS=0x%08X\n",
                 RREG32(SRBM_STATUS));
-        dev_info(rdev->dev, "  DMA_STATUS_REG   = 0x%08X\n",
-                RREG32(DMA_STATUS_REG));
-        dev_info(rdev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
-                 RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR));
-        dev_info(rdev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
-                 RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS));
 
-        evergreen_mc_stop(rdev, &save);
-        if (radeon_mc_wait_for_idle(rdev)) {
-                dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
-        }
         /* Disable CP parsing/prefetching */
         WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT);
 
-        /* dma0 */
-        tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
-        tmp &= ~DMA_RB_ENABLE;
-        WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp);
-
-        /* dma1 */
-        tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);
-        tmp &= ~DMA_RB_ENABLE;
-        WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);
-
-        /* Reset dma */
-        WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA | SOFT_RESET_DMA1);
-        RREG32(SRBM_SOFT_RESET);
-        udelay(50);
-        WREG32(SRBM_SOFT_RESET, 0);
-
         /* reset all the gfx blocks */
         grbm_reset = (SOFT_RESET_CP |
                       SOFT_RESET_CB |
@@ -2196,8 +2168,7 @@ static int si_gpu_soft_reset(struct radeon_device *rdev)
         udelay(50);
         WREG32(GRBM_SOFT_RESET, 0);
         (void)RREG32(GRBM_SOFT_RESET);
-        /* Wait a little for things to settle down */
-        udelay(50);
+
         dev_info(rdev->dev, "  GRBM_STATUS=0x%08X\n",
                 RREG32(GRBM_STATUS));
         dev_info(rdev->dev, "  GRBM_STATUS2=0x%08X\n",
@@ -2208,15 +2179,75 @@ static int si_gpu_soft_reset(struct radeon_device *rdev)
                 RREG32(GRBM_STATUS_SE1));
         dev_info(rdev->dev, "  SRBM_STATUS=0x%08X\n",
                 RREG32(SRBM_STATUS));
+}
+
+static void si_gpu_soft_reset_dma(struct radeon_device *rdev)
+{
+        u32 tmp;
+
+        if (RREG32(DMA_STATUS_REG) & DMA_IDLE)
+                return;
+
         dev_info(rdev->dev, "  DMA_STATUS_REG   = 0x%08X\n",
                 RREG32(DMA_STATUS_REG));
+
+        /* dma0 */
+        tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
+        tmp &= ~DMA_RB_ENABLE;
+        WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp);
+
+        /* dma1 */
+        tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);
+        tmp &= ~DMA_RB_ENABLE;
+        WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);
+
+        /* Reset dma */
+        WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA | SOFT_RESET_DMA1);
+        RREG32(SRBM_SOFT_RESET);
+        udelay(50);
+        WREG32(SRBM_SOFT_RESET, 0);
+
+        dev_info(rdev->dev, "  DMA_STATUS_REG   = 0x%08X\n",
+                RREG32(DMA_STATUS_REG));
+}
+
+static int si_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
+{
+        struct evergreen_mc_save save;
+
+        if (reset_mask == 0)
+                return 0;
+
+        dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);
+
+        dev_info(rdev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
+                 RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR));
+        dev_info(rdev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
+                 RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS));
+
+        evergreen_mc_stop(rdev, &save);
+        if (radeon_mc_wait_for_idle(rdev)) {
+                dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
+        }
+
+        if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE))
+                si_gpu_soft_reset_gfx(rdev);
+
+        if (reset_mask & RADEON_RESET_DMA)
+                si_gpu_soft_reset_dma(rdev);
+
+        /* Wait a little for things to settle down */
+        udelay(50);
+
         evergreen_mc_resume(rdev, &save);
         return 0;
 }
 
 int si_asic_reset(struct radeon_device *rdev)
 {
-        return si_gpu_soft_reset(rdev);
+        return si_gpu_soft_reset(rdev, (RADEON_RESET_GFX |
+                                        RADEON_RESET_COMPUTE |
+                                        RADEON_RESET_DMA));
 }
 
 /* MC */