drm/radeon/kms: replace *REG32_PCIE_P with *REG32_PCIE_PORT

Avoid confusion with the *REG32_P mask macro.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

1 files changed, 16 insertions, 16 deletions

diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c
index 7bce3b8ba50b..777f537a32c7 100644
--- a/drivers/gpu/drm/radeon/rv770.c
+++ b/drivers/gpu/drm/radeon/rv770.c
@@ -1557,23 +1557,23 @@ static void rv770_pcie_gen2_enable(struct radeon_device *rdev)
         DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");
 
         /* advertise upconfig capability */
-        link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
+        link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
         link_width_cntl &= ~LC_UPCONFIGURE_DIS;
-        WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
-        link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
+        WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
+        link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
         if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) {
                 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT;
                 link_width_cntl &= ~(LC_LINK_WIDTH_MASK |
                                      LC_RECONFIG_ARC_MISSING_ESCAPE);
                 link_width_cntl |= lanes | LC_RECONFIG_NOW |
                         LC_RENEGOTIATE_EN | LC_UPCONFIGURE_SUPPORT;
-                WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
+                WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
         } else {
                 link_width_cntl |= LC_UPCONFIGURE_DIS;
-                WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
+                WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
         }
 
-        speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
+        speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
         if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
             (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
 
@@ -1586,29 +1586,29 @@ static void rv770_pcie_gen2_enable(struct radeon_device *rdev)
                 WREG16(0x4088, link_cntl2);
                 WREG32(MM_CFGREGS_CNTL, 0);
 
-                speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
+                speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
                 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
-                WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
+                WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
 
-                speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
+                speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
                 speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT;
-                WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
+                WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
 
-                speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
+                speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
                 speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;
-                WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
+                WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
 
-                speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
+                speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
                 speed_cntl |= LC_GEN2_EN_STRAP;
-                WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
+                WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
 
         } else {
-                link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
+                link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
                 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
                 if (1)
                         link_width_cntl |= LC_UPCONFIGURE_DIS;
                 else
                         link_width_cntl &= ~LC_UPCONFIGURE_DIS;
-                WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
+                WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
         }
 }