diff options
author | Paul Mundt <lethal@linux-sh.org> | 2010-08-03 22:56:17 -0400 |
---|---|---|
committer | Paul Mundt <lethal@linux-sh.org> | 2010-08-03 22:56:17 -0400 |
commit | 701ec7a7b04a62c74ab1b83b59a3fd35c0ba5fdb (patch) | |
tree | c07aa954f48ec45c422641052d46008697a4a6b1 /drivers/gpu/drm/radeon/rs400.c | |
parent | 285eba57db7bd7d7c3c5929fb8621fdcaaea1b00 (diff) | |
parent | 3a09b1be53d23df780a0cd0e4087a05e2ca4a00c (diff) |
Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
Conflicts:
arch/arm/configs/ap4evb_defconfig
arch/arm/configs/g3evm_defconfig
arch/arm/configs/g4evm_defconfig
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'drivers/gpu/drm/radeon/rs400.c')
-rw-r--r-- | drivers/gpu/drm/radeon/rs400.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/drivers/gpu/drm/radeon/rs400.c b/drivers/gpu/drm/radeon/rs400.c index 9e4240b3bf0b..f454c9a5e7f2 100644 --- a/drivers/gpu/drm/radeon/rs400.c +++ b/drivers/gpu/drm/radeon/rs400.c | |||
@@ -57,7 +57,9 @@ void rs400_gart_adjust_size(struct radeon_device *rdev) | |||
57 | } | 57 | } |
58 | if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) { | 58 | if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) { |
59 | /* FIXME: RS400 & RS480 seems to have issue with GART size | 59 | /* FIXME: RS400 & RS480 seems to have issue with GART size |
60 | * if 4G of system memory (needs more testing) */ | 60 | * if 4G of system memory (needs more testing) |
61 | */ | ||
62 | /* XXX is this still an issue with proper alignment? */ | ||
61 | rdev->mc.gtt_size = 32 * 1024 * 1024; | 63 | rdev->mc.gtt_size = 32 * 1024 * 1024; |
62 | DRM_ERROR("Forcing to 32M GART size (because of ASIC bug ?)\n"); | 64 | DRM_ERROR("Forcing to 32M GART size (because of ASIC bug ?)\n"); |
63 | } | 65 | } |
@@ -263,6 +265,7 @@ void rs400_mc_init(struct radeon_device *rdev) | |||
263 | r100_vram_init_sizes(rdev); | 265 | r100_vram_init_sizes(rdev); |
264 | base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16; | 266 | base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16; |
265 | radeon_vram_location(rdev, &rdev->mc, base); | 267 | radeon_vram_location(rdev, &rdev->mc, base); |
268 | rdev->mc.gtt_base_align = rdev->mc.gtt_size - 1; | ||
266 | radeon_gtt_location(rdev, &rdev->mc); | 269 | radeon_gtt_location(rdev, &rdev->mc); |
267 | radeon_update_bandwidth_info(rdev); | 270 | radeon_update_bandwidth_info(rdev); |
268 | } | 271 | } |