Merge branch 'drm-core-next' of git://people.freedesktop.org/~airlied/linux

* 'drm-core-next' of git://people.freedesktop.org/~airlied/linux: (307 commits)
  drm/nouveau/pm: fix build with HWMON off
  gma500: silence gcc warnings in mid_get_vbt_data()
  drm/ttm: fix condition (and vs or)
  drm/radeon: double lock typo in radeon_vm_bo_rmv()
  drm/radeon: use after free in radeon_vm_bo_add()
  drm/sis|via: don't return stack garbage from free_mem ioctl
  drm/radeon/kms: remove pointless CS flags priority struct
  drm/radeon/kms: check if vm is supported in VA ioctl
  drm: introduce drm_can_sleep and use in intel/radeon drivers. (v2)
  radeon: Fix disabling PCI bus mastering on big endian hosts.
  ttm: fix agp since ttm tt rework
  agp: Fix multi-line warning message whitespace
  drm/ttm/dma: Fix accounting error when calling ttm_mem_global_free_page and don't try to free freed pages.
  drm/ttm/dma: Only call set_pages_array_wb when the page is not in WB pool.
  drm/radeon/kms: sync across multiple rings when doing bo moves v3
  drm/radeon/kms: Add support for multi-ring sync in CS ioctl (v2)
  drm/radeon: GPU virtual memory support v22
  drm: make DRM_UNLOCKED ioctls with their own mutex
  drm: no need to hold global mutex for static data
  drm/radeon/benchmark: common modes sweep ignores 640x480@32
  ...

Fix up trivial conflicts in radeon/evergreen.c and vmwgfx/vmwgfx_kms.c

1 files changed, 146 insertions, 51 deletions

diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c
index a2e1eae114ef..36a6192ce862 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.c
+++ b/drivers/gpu/drm/radeon/radeon_asic.c
@@ -138,14 +138,18 @@ static struct radeon_asic r100_asic = {
         .asic_reset = &r100_asic_reset,
         .gart_tlb_flush = &r100_pci_gart_tlb_flush,
         .gart_set_page = &r100_pci_gart_set_page,
-        .cp_commit = &r100_cp_commit,
         .ring_start = &r100_ring_start,
         .ring_test = &r100_ring_test,
-        .ring_ib_execute = &r100_ring_ib_execute,
+        .ring = {
+                [RADEON_RING_TYPE_GFX_INDEX] = {
+                        .ib_execute = &r100_ring_ib_execute,
+                        .emit_fence = &r100_fence_ring_emit,
+                        .emit_semaphore = &r100_semaphore_ring_emit,
+                }
+        },
         .irq_set = &r100_irq_set,
         .irq_process = &r100_irq_process,
         .get_vblank_counter = &r100_get_vblank_counter,
-        .fence_ring_emit = &r100_fence_ring_emit,
         .cs_parse = &r100_cs_parse,
         .copy_blit = &r100_copy_blit,
         .copy_dma = NULL,
@@ -186,14 +190,18 @@ static struct radeon_asic r200_asic = {
         .asic_reset = &r100_asic_reset,
         .gart_tlb_flush = &r100_pci_gart_tlb_flush,
         .gart_set_page = &r100_pci_gart_set_page,
-        .cp_commit = &r100_cp_commit,
         .ring_start = &r100_ring_start,
         .ring_test = &r100_ring_test,
-        .ring_ib_execute = &r100_ring_ib_execute,
+        .ring = {
+                [RADEON_RING_TYPE_GFX_INDEX] = {
+                        .ib_execute = &r100_ring_ib_execute,
+                        .emit_fence = &r100_fence_ring_emit,
+                        .emit_semaphore = &r100_semaphore_ring_emit,
+                }
+        },
         .irq_set = &r100_irq_set,
         .irq_process = &r100_irq_process,
         .get_vblank_counter = &r100_get_vblank_counter,
-        .fence_ring_emit = &r100_fence_ring_emit,
         .cs_parse = &r100_cs_parse,
         .copy_blit = &r100_copy_blit,
         .copy_dma = &r200_copy_dma,
@@ -233,14 +241,18 @@ static struct radeon_asic r300_asic = {
         .asic_reset = &r300_asic_reset,
         .gart_tlb_flush = &r100_pci_gart_tlb_flush,
         .gart_set_page = &r100_pci_gart_set_page,
-        .cp_commit = &r100_cp_commit,
         .ring_start = &r300_ring_start,
         .ring_test = &r100_ring_test,
-        .ring_ib_execute = &r100_ring_ib_execute,
+        .ring = {
+                [RADEON_RING_TYPE_GFX_INDEX] = {
+                        .ib_execute = &r100_ring_ib_execute,
+                        .emit_fence = &r300_fence_ring_emit,
+                        .emit_semaphore = &r100_semaphore_ring_emit,
+                }
+        },
         .irq_set = &r100_irq_set,
         .irq_process = &r100_irq_process,
         .get_vblank_counter = &r100_get_vblank_counter,
-        .fence_ring_emit = &r300_fence_ring_emit,
         .cs_parse = &r300_cs_parse,
         .copy_blit = &r100_copy_blit,
         .copy_dma = &r200_copy_dma,
@@ -281,14 +293,18 @@ static struct radeon_asic r300_asic_pcie = {
         .asic_reset = &r300_asic_reset,
         .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
         .gart_set_page = &rv370_pcie_gart_set_page,
-        .cp_commit = &r100_cp_commit,
         .ring_start = &r300_ring_start,
         .ring_test = &r100_ring_test,
-        .ring_ib_execute = &r100_ring_ib_execute,
+        .ring = {
+                [RADEON_RING_TYPE_GFX_INDEX] = {
+                        .ib_execute = &r100_ring_ib_execute,
+                        .emit_fence = &r300_fence_ring_emit,
+                        .emit_semaphore = &r100_semaphore_ring_emit,
+                }
+        },
         .irq_set = &r100_irq_set,
         .irq_process = &r100_irq_process,
         .get_vblank_counter = &r100_get_vblank_counter,
-        .fence_ring_emit = &r300_fence_ring_emit,
         .cs_parse = &r300_cs_parse,
         .copy_blit = &r100_copy_blit,
         .copy_dma = &r200_copy_dma,
@@ -328,14 +344,18 @@ static struct radeon_asic r420_asic = {
         .asic_reset = &r300_asic_reset,
         .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
         .gart_set_page = &rv370_pcie_gart_set_page,
-        .cp_commit = &r100_cp_commit,
         .ring_start = &r300_ring_start,
         .ring_test = &r100_ring_test,
-        .ring_ib_execute = &r100_ring_ib_execute,
+        .ring = {
+                [RADEON_RING_TYPE_GFX_INDEX] = {
+                        .ib_execute = &r100_ring_ib_execute,
+                        .emit_fence = &r300_fence_ring_emit,
+                        .emit_semaphore = &r100_semaphore_ring_emit,
+                }
+        },
         .irq_set = &r100_irq_set,
         .irq_process = &r100_irq_process,
         .get_vblank_counter = &r100_get_vblank_counter,
-        .fence_ring_emit = &r300_fence_ring_emit,
         .cs_parse = &r300_cs_parse,
         .copy_blit = &r100_copy_blit,
         .copy_dma = &r200_copy_dma,
@@ -376,14 +396,18 @@ static struct radeon_asic rs400_asic = {
         .asic_reset = &r300_asic_reset,
         .gart_tlb_flush = &rs400_gart_tlb_flush,
         .gart_set_page = &rs400_gart_set_page,
-        .cp_commit = &r100_cp_commit,
         .ring_start = &r300_ring_start,
         .ring_test = &r100_ring_test,
-        .ring_ib_execute = &r100_ring_ib_execute,
+        .ring = {
+                [RADEON_RING_TYPE_GFX_INDEX] = {
+                        .ib_execute = &r100_ring_ib_execute,
+                        .emit_fence = &r300_fence_ring_emit,
+                        .emit_semaphore = &r100_semaphore_ring_emit,
+                }
+        },
         .irq_set = &r100_irq_set,
         .irq_process = &r100_irq_process,
         .get_vblank_counter = &r100_get_vblank_counter,
-        .fence_ring_emit = &r300_fence_ring_emit,
         .cs_parse = &r300_cs_parse,
         .copy_blit = &r100_copy_blit,
         .copy_dma = &r200_copy_dma,
@@ -424,14 +448,18 @@ static struct radeon_asic rs600_asic = {
         .asic_reset = &rs600_asic_reset,
         .gart_tlb_flush = &rs600_gart_tlb_flush,
         .gart_set_page = &rs600_gart_set_page,
-        .cp_commit = &r100_cp_commit,
         .ring_start = &r300_ring_start,
         .ring_test = &r100_ring_test,
-        .ring_ib_execute = &r100_ring_ib_execute,
+        .ring = {
+                [RADEON_RING_TYPE_GFX_INDEX] = {
+                        .ib_execute = &r100_ring_ib_execute,
+                        .emit_fence = &r300_fence_ring_emit,
+                        .emit_semaphore = &r100_semaphore_ring_emit,
+                }
+        },
         .irq_set = &rs600_irq_set,
         .irq_process = &rs600_irq_process,
         .get_vblank_counter = &rs600_get_vblank_counter,
-        .fence_ring_emit = &r300_fence_ring_emit,
         .cs_parse = &r300_cs_parse,
         .copy_blit = &r100_copy_blit,
         .copy_dma = &r200_copy_dma,
@@ -472,14 +500,18 @@ static struct radeon_asic rs690_asic = {
         .asic_reset = &rs600_asic_reset,
         .gart_tlb_flush = &rs400_gart_tlb_flush,
         .gart_set_page = &rs400_gart_set_page,
-        .cp_commit = &r100_cp_commit,
         .ring_start = &r300_ring_start,
         .ring_test = &r100_ring_test,
-        .ring_ib_execute = &r100_ring_ib_execute,
+        .ring = {
+                [RADEON_RING_TYPE_GFX_INDEX] = {
+                        .ib_execute = &r100_ring_ib_execute,
+                        .emit_fence = &r300_fence_ring_emit,
+                        .emit_semaphore = &r100_semaphore_ring_emit,
+                }
+        },
         .irq_set = &rs600_irq_set,
         .irq_process = &rs600_irq_process,
         .get_vblank_counter = &rs600_get_vblank_counter,
-        .fence_ring_emit = &r300_fence_ring_emit,
         .cs_parse = &r300_cs_parse,
         .copy_blit = &r100_copy_blit,
         .copy_dma = &r200_copy_dma,
@@ -520,14 +552,18 @@ static struct radeon_asic rv515_asic = {
         .asic_reset = &rs600_asic_reset,
         .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
         .gart_set_page = &rv370_pcie_gart_set_page,
-        .cp_commit = &r100_cp_commit,
         .ring_start = &rv515_ring_start,
         .ring_test = &r100_ring_test,
-        .ring_ib_execute = &r100_ring_ib_execute,
+        .ring = {
+                [RADEON_RING_TYPE_GFX_INDEX] = {
+                        .ib_execute = &r100_ring_ib_execute,
+                        .emit_fence = &r300_fence_ring_emit,
+                        .emit_semaphore = &r100_semaphore_ring_emit,
+                }
+        },
         .irq_set = &rs600_irq_set,
         .irq_process = &rs600_irq_process,
         .get_vblank_counter = &rs600_get_vblank_counter,
-        .fence_ring_emit = &r300_fence_ring_emit,
         .cs_parse = &r300_cs_parse,
         .copy_blit = &r100_copy_blit,
         .copy_dma = &r200_copy_dma,
@@ -568,14 +604,18 @@ static struct radeon_asic r520_asic = {
         .asic_reset = &rs600_asic_reset,
         .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
         .gart_set_page = &rv370_pcie_gart_set_page,
-        .cp_commit = &r100_cp_commit,
         .ring_start = &rv515_ring_start,
         .ring_test = &r100_ring_test,
-        .ring_ib_execute = &r100_ring_ib_execute,
+        .ring = {
+                [RADEON_RING_TYPE_GFX_INDEX] = {
+                        .ib_execute = &r100_ring_ib_execute,
+                        .emit_fence = &r300_fence_ring_emit,
+                        .emit_semaphore = &r100_semaphore_ring_emit,
+                }
+        },
         .irq_set = &rs600_irq_set,
         .irq_process = &rs600_irq_process,
         .get_vblank_counter = &rs600_get_vblank_counter,
-        .fence_ring_emit = &r300_fence_ring_emit,
         .cs_parse = &r300_cs_parse,
         .copy_blit = &r100_copy_blit,
         .copy_dma = &r200_copy_dma,
@@ -611,18 +651,22 @@ static struct radeon_asic r600_asic = {
         .fini = &r600_fini,
         .suspend = &r600_suspend,
         .resume = &r600_resume,
-        .cp_commit = &r600_cp_commit,
         .vga_set_state = &r600_vga_set_state,
         .gpu_is_lockup = &r600_gpu_is_lockup,
         .asic_reset = &r600_asic_reset,
         .gart_tlb_flush = &r600_pcie_gart_tlb_flush,
         .gart_set_page = &rs600_gart_set_page,
         .ring_test = &r600_ring_test,
-        .ring_ib_execute = &r600_ring_ib_execute,
+        .ring = {
+                [RADEON_RING_TYPE_GFX_INDEX] = {
+                        .ib_execute = &r600_ring_ib_execute,
+                        .emit_fence = &r600_fence_ring_emit,
+                        .emit_semaphore = &r600_semaphore_ring_emit,
+                }
+        },
         .irq_set = &r600_irq_set,
         .irq_process = &r600_irq_process,
         .get_vblank_counter = &rs600_get_vblank_counter,
-        .fence_ring_emit = &r600_fence_ring_emit,
         .cs_parse = &r600_cs_parse,
         .copy_blit = &r600_copy_blit,
         .copy_dma = NULL,
@@ -658,18 +702,22 @@ static struct radeon_asic rs780_asic = {
         .fini = &r600_fini,
         .suspend = &r600_suspend,
         .resume = &r600_resume,
-        .cp_commit = &r600_cp_commit,
         .gpu_is_lockup = &r600_gpu_is_lockup,
         .vga_set_state = &r600_vga_set_state,
         .asic_reset = &r600_asic_reset,
         .gart_tlb_flush = &r600_pcie_gart_tlb_flush,
         .gart_set_page = &rs600_gart_set_page,
         .ring_test = &r600_ring_test,
-        .ring_ib_execute = &r600_ring_ib_execute,
+        .ring = {
+                [RADEON_RING_TYPE_GFX_INDEX] = {
+                        .ib_execute = &r600_ring_ib_execute,
+                        .emit_fence = &r600_fence_ring_emit,
+                        .emit_semaphore = &r600_semaphore_ring_emit,
+                }
+        },
         .irq_set = &r600_irq_set,
         .irq_process = &r600_irq_process,
         .get_vblank_counter = &rs600_get_vblank_counter,
-        .fence_ring_emit = &r600_fence_ring_emit,
         .cs_parse = &r600_cs_parse,
         .copy_blit = &r600_copy_blit,
         .copy_dma = NULL,
@@ -705,18 +753,22 @@ static struct radeon_asic rv770_asic = {
         .fini = &rv770_fini,
         .suspend = &rv770_suspend,
         .resume = &rv770_resume,
-        .cp_commit = &r600_cp_commit,
         .asic_reset = &r600_asic_reset,
         .gpu_is_lockup = &r600_gpu_is_lockup,
         .vga_set_state = &r600_vga_set_state,
         .gart_tlb_flush = &r600_pcie_gart_tlb_flush,
         .gart_set_page = &rs600_gart_set_page,
         .ring_test = &r600_ring_test,
-        .ring_ib_execute = &r600_ring_ib_execute,
+        .ring = {
+                [RADEON_RING_TYPE_GFX_INDEX] = {
+                        .ib_execute = &r600_ring_ib_execute,
+                        .emit_fence = &r600_fence_ring_emit,
+                        .emit_semaphore = &r600_semaphore_ring_emit,
+                }
+        },
         .irq_set = &r600_irq_set,
         .irq_process = &r600_irq_process,
         .get_vblank_counter = &rs600_get_vblank_counter,
-        .fence_ring_emit = &r600_fence_ring_emit,
         .cs_parse = &r600_cs_parse,
         .copy_blit = &r600_copy_blit,
         .copy_dma = NULL,
@@ -752,18 +804,22 @@ static struct radeon_asic evergreen_asic = {
         .fini = &evergreen_fini,
         .suspend = &evergreen_suspend,
         .resume = &evergreen_resume,
-        .cp_commit = &r600_cp_commit,
         .gpu_is_lockup = &evergreen_gpu_is_lockup,
         .asic_reset = &evergreen_asic_reset,
         .vga_set_state = &r600_vga_set_state,
         .gart_tlb_flush = &evergreen_pcie_gart_tlb_flush,
         .gart_set_page = &rs600_gart_set_page,
         .ring_test = &r600_ring_test,
-        .ring_ib_execute = &evergreen_ring_ib_execute,
+        .ring = {
+                [RADEON_RING_TYPE_GFX_INDEX] = {
+                        .ib_execute = &evergreen_ring_ib_execute,
+                        .emit_fence = &r600_fence_ring_emit,
+                        .emit_semaphore = &r600_semaphore_ring_emit,
+                }
+        },
         .irq_set = &evergreen_irq_set,
         .irq_process = &evergreen_irq_process,
         .get_vblank_counter = &evergreen_get_vblank_counter,
-        .fence_ring_emit = &r600_fence_ring_emit,
         .cs_parse = &evergreen_cs_parse,
         .copy_blit = &r600_copy_blit,
         .copy_dma = NULL,
@@ -799,18 +855,22 @@ static struct radeon_asic sumo_asic = {
         .fini = &evergreen_fini,
         .suspend = &evergreen_suspend,
         .resume = &evergreen_resume,
-        .cp_commit = &r600_cp_commit,
         .gpu_is_lockup = &evergreen_gpu_is_lockup,
         .asic_reset = &evergreen_asic_reset,
         .vga_set_state = &r600_vga_set_state,
         .gart_tlb_flush = &evergreen_pcie_gart_tlb_flush,
         .gart_set_page = &rs600_gart_set_page,
         .ring_test = &r600_ring_test,
-        .ring_ib_execute = &evergreen_ring_ib_execute,
+        .ring = {
+                [RADEON_RING_TYPE_GFX_INDEX] = {
+                        .ib_execute = &evergreen_ring_ib_execute,
+                        .emit_fence = &r600_fence_ring_emit,
+                        .emit_semaphore = &r600_semaphore_ring_emit,
+                }
+        },
         .irq_set = &evergreen_irq_set,
         .irq_process = &evergreen_irq_process,
         .get_vblank_counter = &evergreen_get_vblank_counter,
-        .fence_ring_emit = &r600_fence_ring_emit,
         .cs_parse = &evergreen_cs_parse,
         .copy_blit = &r600_copy_blit,
         .copy_dma = NULL,
@@ -846,18 +906,22 @@ static struct radeon_asic btc_asic = {
         .fini = &evergreen_fini,
         .suspend = &evergreen_suspend,
         .resume = &evergreen_resume,
-        .cp_commit = &r600_cp_commit,
         .gpu_is_lockup = &evergreen_gpu_is_lockup,
         .asic_reset = &evergreen_asic_reset,
         .vga_set_state = &r600_vga_set_state,
         .gart_tlb_flush = &evergreen_pcie_gart_tlb_flush,
         .gart_set_page = &rs600_gart_set_page,
         .ring_test = &r600_ring_test,
-        .ring_ib_execute = &evergreen_ring_ib_execute,
+        .ring = {
+                [RADEON_RING_TYPE_GFX_INDEX] = {
+                        .ib_execute = &evergreen_ring_ib_execute,
+                        .emit_fence = &r600_fence_ring_emit,
+                        .emit_semaphore = &r600_semaphore_ring_emit,
+                }
+        },
         .irq_set = &evergreen_irq_set,
         .irq_process = &evergreen_irq_process,
         .get_vblank_counter = &evergreen_get_vblank_counter,
-        .fence_ring_emit = &r600_fence_ring_emit,
         .cs_parse = &evergreen_cs_parse,
         .copy_blit = &r600_copy_blit,
         .copy_dma = NULL,
@@ -888,23 +952,50 @@ static struct radeon_asic btc_asic = {
         .post_page_flip = &evergreen_post_page_flip,
 };
 
+static const struct radeon_vm_funcs cayman_vm_funcs = {
+        .init = &cayman_vm_init,
+        .fini = &cayman_vm_fini,
+        .bind = &cayman_vm_bind,
+        .unbind = &cayman_vm_unbind,
+        .tlb_flush = &cayman_vm_tlb_flush,
+        .page_flags = &cayman_vm_page_flags,
+        .set_page = &cayman_vm_set_page,
+};
+
 static struct radeon_asic cayman_asic = {
         .init = &cayman_init,
         .fini = &cayman_fini,
         .suspend = &cayman_suspend,
         .resume = &cayman_resume,
-        .cp_commit = &r600_cp_commit,
         .gpu_is_lockup = &cayman_gpu_is_lockup,
         .asic_reset = &cayman_asic_reset,
         .vga_set_state = &r600_vga_set_state,
         .gart_tlb_flush = &cayman_pcie_gart_tlb_flush,
         .gart_set_page = &rs600_gart_set_page,
         .ring_test = &r600_ring_test,
-        .ring_ib_execute = &evergreen_ring_ib_execute,
+        .ring = {
+                [RADEON_RING_TYPE_GFX_INDEX] = {
+                        .ib_execute = &cayman_ring_ib_execute,
+                        .ib_parse = &evergreen_ib_parse,
+                        .emit_fence = &cayman_fence_ring_emit,
+                        .emit_semaphore = &r600_semaphore_ring_emit,
+                },
+                [CAYMAN_RING_TYPE_CP1_INDEX] = {
+                        .ib_execute = &cayman_ring_ib_execute,
+                        .ib_parse = &evergreen_ib_parse,
+                        .emit_fence = &cayman_fence_ring_emit,
+                        .emit_semaphore = &r600_semaphore_ring_emit,
+                },
+                [CAYMAN_RING_TYPE_CP2_INDEX] = {
+                        .ib_execute = &cayman_ring_ib_execute,
+                        .ib_parse = &evergreen_ib_parse,
+                        .emit_fence = &cayman_fence_ring_emit,
+                        .emit_semaphore = &r600_semaphore_ring_emit,
+                }
+        },
         .irq_set = &evergreen_irq_set,
         .irq_process = &evergreen_irq_process,
         .get_vblank_counter = &evergreen_get_vblank_counter,
-        .fence_ring_emit = &r600_fence_ring_emit,
         .cs_parse = &evergreen_cs_parse,
         .copy_blit = &r600_copy_blit,
         .copy_dma = NULL,
@@ -945,6 +1036,9 @@ int radeon_asic_init(struct radeon_device *rdev)
         else
                 rdev->num_crtc = 2;
 
+        /* set the ring used for bo copies */
+        rdev->copy_ring = RADEON_RING_TYPE_GFX_INDEX;
+
         switch (rdev->family) {
         case CHIP_R100:
         case CHIP_RV100:
@@ -1050,6 +1144,7 @@ int radeon_asic_init(struct radeon_device *rdev)
                 rdev->asic = &cayman_asic;
                 /* set num crtcs */
                 rdev->num_crtc = 6;
+                rdev->vm_manager.funcs = &cayman_vm_funcs;
                 break;
         default:
                 /* FIXME: not supported yet */