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authorJerome Glisse <jglisse@redhat.com>2011-11-20 15:45:34 -0500
committerDave Airlie <airlied@redhat.com>2011-12-20 14:51:19 -0500
commit30eb77f4e6ba20f797af4ff79807fae7cb67429e (patch)
tree0143bb70c00f3080d70cf8e2a966cf8d7f137dfc /drivers/gpu/drm/radeon/r600.c
parentaf9720f4907e0a4a4341a015efe08026b3d3eb2e (diff)
drm/radeon: precompute fence cpu/gpu addr once v3
Add a start fence driver helper function which will be call once for each ring and will compute cpu/gpu addr for fence depending on wether to use wb buffer or scratch reg. This patch replace initialize fence driver separately which was broken in regard of GPU lockup. The fence list for created, emited, signaled must be initialize once and only from the asic init callback not from the startup call back which is call from the gpu reset. v2: With this in place we no longer need to know the number of rings in fence_driver_init, also writing to the scratch reg before knowing its offset is a bad idea. v3: rebase on top of change to previous patch in the serie Signed-off-by: Christian König <deathsimple@vodafone.de> Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/r600.c')
-rw-r--r--drivers/gpu/drm/radeon/r600.c11
1 files changed, 8 insertions, 3 deletions
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index 17538926cc47..f2deadfcd88f 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -2313,8 +2313,7 @@ void r600_fence_ring_emit(struct radeon_device *rdev,
2313 struct radeon_ring *ring = &rdev->ring[fence->ring]; 2313 struct radeon_ring *ring = &rdev->ring[fence->ring];
2314 2314
2315 if (rdev->wb.use_event) { 2315 if (rdev->wb.use_event) {
2316 u64 addr = rdev->wb.gpu_addr + R600_WB_EVENT_OFFSET + 2316 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
2317 (u64)(rdev->fence_drv[fence->ring].scratch_reg - rdev->scratch.reg_base);
2318 /* flush read cache over gart */ 2317 /* flush read cache over gart */
2319 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); 2318 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
2320 radeon_ring_write(ring, PACKET3_TC_ACTION_ENA | 2319 radeon_ring_write(ring, PACKET3_TC_ACTION_ENA |
@@ -2459,6 +2458,12 @@ int r600_startup(struct radeon_device *rdev)
2459 if (r) 2458 if (r)
2460 return r; 2459 return r;
2461 2460
2461 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
2462 if (r) {
2463 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
2464 return r;
2465 }
2466
2462 /* Enable IRQ */ 2467 /* Enable IRQ */
2463 r = r600_irq_init(rdev); 2468 r = r600_irq_init(rdev);
2464 if (r) { 2469 if (r) {
@@ -2589,7 +2594,7 @@ int r600_init(struct radeon_device *rdev)
2589 /* Initialize clocks */ 2594 /* Initialize clocks */
2590 radeon_get_clock_info(rdev->ddev); 2595 radeon_get_clock_info(rdev->ddev);
2591 /* Fence driver */ 2596 /* Fence driver */
2592 r = radeon_fence_driver_init(rdev, 1); 2597 r = radeon_fence_driver_init(rdev);
2593 if (r) 2598 if (r)
2594 return r; 2599 return r;
2595 if (rdev->flags & RADEON_IS_AGP) { 2600 if (rdev->flags & RADEON_IS_AGP) {