diff options
author | Jerome Glisse <jglisse@redhat.com> | 2009-09-14 12:29:49 -0400 |
---|---|---|
committer | Dave Airlie <airlied@redhat.com> | 2009-09-14 18:53:14 -0400 |
commit | 4aac047323e3082d0866b8ad3784236632105af4 (patch) | |
tree | af4c118e42b9ea55c961c4f5bbb02998dc2cc4fe /drivers/gpu/drm/radeon/r420.c | |
parent | 21f9a437222e92adb3abc68584a5f04801b92739 (diff) |
drm/radeon/kms: clear confusion in GART init/deinit path
GART static one time initialization was mixed up with GART
enabling/disabling which could happen several time for instance
during suspend/resume cycles. This patch splits all GART
handling into 4 differents function. gart_init is for one
time initialization, gart_deinit is called upon module unload
to free resources allocated by gart_init, gart_enable enable
the GART and is intented to be call after first initialization
and at each resume cycle or reset cycle. Finaly gart_disable
stop the GART and is intended to be call at suspend time or
when unloading the module.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/r420.c')
-rw-r--r-- | drivers/gpu/drm/radeon/r420.c | 57 |
1 files changed, 36 insertions, 21 deletions
diff --git a/drivers/gpu/drm/radeon/r420.c b/drivers/gpu/drm/radeon/r420.c index e57b9ba4aaf3..33a25a4377b8 100644 --- a/drivers/gpu/drm/radeon/r420.c +++ b/drivers/gpu/drm/radeon/r420.c | |||
@@ -161,6 +161,11 @@ int r420_resume(struct radeon_device *rdev) | |||
161 | { | 161 | { |
162 | int r; | 162 | int r; |
163 | 163 | ||
164 | /* Make sur GART are not working */ | ||
165 | if (rdev->flags & RADEON_IS_PCIE) | ||
166 | rv370_pcie_gart_disable(rdev); | ||
167 | if (rdev->flags & RADEON_IS_PCI) | ||
168 | r100_pci_gart_disable(rdev); | ||
164 | /* Resume clock before doing reset */ | 169 | /* Resume clock before doing reset */ |
165 | r420_clock_resume(rdev); | 170 | r420_clock_resume(rdev); |
166 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ | 171 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ |
@@ -180,10 +185,15 @@ int r420_resume(struct radeon_device *rdev) | |||
180 | r300_mc_program(rdev); | 185 | r300_mc_program(rdev); |
181 | /* Initialize GART (initialize after TTM so we can allocate | 186 | /* Initialize GART (initialize after TTM so we can allocate |
182 | * memory through TTM but finalize after TTM) */ | 187 | * memory through TTM but finalize after TTM) */ |
183 | r = radeon_gart_enable(rdev); | 188 | if (rdev->flags & RADEON_IS_PCIE) { |
184 | if (r) { | 189 | r = rv370_pcie_gart_enable(rdev); |
185 | dev_err(rdev->dev, "failled initializing GART (%d).\n", r); | 190 | if (r) |
186 | return r; | 191 | return r; |
192 | } | ||
193 | if (rdev->flags & RADEON_IS_PCI) { | ||
194 | r = r100_pci_gart_enable(rdev); | ||
195 | if (r) | ||
196 | return r; | ||
187 | } | 197 | } |
188 | r420_pipes_init(rdev); | 198 | r420_pipes_init(rdev); |
189 | /* Enable IRQ */ | 199 | /* Enable IRQ */ |
@@ -212,7 +222,10 @@ int r420_suspend(struct radeon_device *rdev) | |||
212 | r100_cp_disable(rdev); | 222 | r100_cp_disable(rdev); |
213 | r100_wb_disable(rdev); | 223 | r100_wb_disable(rdev); |
214 | r100_irq_disable(rdev); | 224 | r100_irq_disable(rdev); |
215 | radeon_gart_disable(rdev); | 225 | if (rdev->flags & RADEON_IS_PCIE) |
226 | rv370_pcie_gart_disable(rdev); | ||
227 | if (rdev->flags & RADEON_IS_PCI) | ||
228 | r100_pci_gart_disable(rdev); | ||
216 | return 0; | 229 | return 0; |
217 | } | 230 | } |
218 | 231 | ||
@@ -222,14 +235,10 @@ void r420_fini(struct radeon_device *rdev) | |||
222 | r100_wb_fini(rdev); | 235 | r100_wb_fini(rdev); |
223 | r100_ib_fini(rdev); | 236 | r100_ib_fini(rdev); |
224 | radeon_gem_fini(rdev); | 237 | radeon_gem_fini(rdev); |
225 | if (rdev->flags & RADEON_IS_PCIE) { | 238 | if (rdev->flags & RADEON_IS_PCIE) |
226 | rv370_pcie_gart_disable(rdev); | 239 | rv370_pcie_gart_fini(rdev); |
227 | radeon_gart_table_vram_free(rdev); | 240 | if (rdev->flags & RADEON_IS_PCI) |
228 | } else { | 241 | r100_pci_gart_fini(rdev); |
229 | r100_pci_gart_disable(rdev); | ||
230 | radeon_gart_table_ram_free(rdev); | ||
231 | } | ||
232 | radeon_gart_fini(rdev); | ||
233 | radeon_agp_fini(rdev); | 242 | radeon_agp_fini(rdev); |
234 | radeon_irq_kms_fini(rdev); | 243 | radeon_irq_kms_fini(rdev); |
235 | radeon_fence_driver_fini(rdev); | 244 | radeon_fence_driver_fini(rdev); |
@@ -309,6 +318,16 @@ int r420_init(struct radeon_device *rdev) | |||
309 | if (r) { | 318 | if (r) { |
310 | return r; | 319 | return r; |
311 | } | 320 | } |
321 | if (rdev->flags & RADEON_IS_PCIE) { | ||
322 | r = rv370_pcie_gart_init(rdev); | ||
323 | if (r) | ||
324 | return r; | ||
325 | } | ||
326 | if (rdev->flags & RADEON_IS_PCI) { | ||
327 | r = r100_pci_gart_init(rdev); | ||
328 | if (r) | ||
329 | return r; | ||
330 | } | ||
312 | r300_set_reg_safe(rdev); | 331 | r300_set_reg_safe(rdev); |
313 | r = r420_resume(rdev); | 332 | r = r420_resume(rdev); |
314 | if (r) { | 333 | if (r) { |
@@ -318,14 +337,10 @@ int r420_init(struct radeon_device *rdev) | |||
318 | r100_cp_fini(rdev); | 337 | r100_cp_fini(rdev); |
319 | r100_wb_fini(rdev); | 338 | r100_wb_fini(rdev); |
320 | r100_ib_fini(rdev); | 339 | r100_ib_fini(rdev); |
321 | if (rdev->flags & RADEON_IS_PCIE) { | 340 | if (rdev->flags & RADEON_IS_PCIE) |
322 | rv370_pcie_gart_disable(rdev); | 341 | rv370_pcie_gart_fini(rdev); |
323 | radeon_gart_table_vram_free(rdev); | 342 | if (rdev->flags & RADEON_IS_PCI) |
324 | } else { | 343 | r100_pci_gart_fini(rdev); |
325 | r100_pci_gart_disable(rdev); | ||
326 | radeon_gart_table_ram_free(rdev); | ||
327 | } | ||
328 | radeon_gart_fini(rdev); | ||
329 | radeon_agp_fini(rdev); | 344 | radeon_agp_fini(rdev); |
330 | radeon_irq_kms_fini(rdev); | 345 | radeon_irq_kms_fini(rdev); |
331 | } | 346 | } |