diff options
| author | Alex Deucher <alexdeucher@gmail.com> | 2010-03-24 13:26:36 -0400 |
|---|---|---|
| committer | Dave Airlie <airlied@redhat.com> | 2010-04-08 20:15:35 -0400 |
| commit | 747943ea187e5acceb7ffc762ff2c84cb3449745 (patch) | |
| tree | 9db964f6ff1883b7b1e902cde1073494956b0ff1 /drivers/gpu/drm/radeon/evergreend.h | |
| parent | 0fcdb61e78050f8f0b31029eeafa5ae013ce0f35 (diff) | |
drm/radeon/kms/evergreen: add soft reset function
Works pretty similarly to r6xx/r7xx.
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/evergreend.h')
| -rw-r--r-- | drivers/gpu/drm/radeon/evergreend.h | 63 |
1 files changed, 61 insertions, 2 deletions
diff --git a/drivers/gpu/drm/radeon/evergreend.h b/drivers/gpu/drm/radeon/evergreend.h index 5cf707a54562..7c290a6dd0e3 100644 --- a/drivers/gpu/drm/radeon/evergreend.h +++ b/drivers/gpu/drm/radeon/evergreend.h | |||
| @@ -78,10 +78,53 @@ | |||
| 78 | #define GRBM_CNTL 0x8000 | 78 | #define GRBM_CNTL 0x8000 |
| 79 | #define GRBM_READ_TIMEOUT(x) ((x) << 0) | 79 | #define GRBM_READ_TIMEOUT(x) ((x) << 0) |
| 80 | #define GRBM_SOFT_RESET 0x8020 | 80 | #define GRBM_SOFT_RESET 0x8020 |
| 81 | #define SOFT_RESET_CP (1<<0) | 81 | #define SOFT_RESET_CP (1 << 0) |
| 82 | #define SOFT_RESET_CB (1 << 1) | ||
| 83 | #define SOFT_RESET_DB (1 << 3) | ||
| 84 | #define SOFT_RESET_PA (1 << 5) | ||
| 85 | #define SOFT_RESET_SC (1 << 6) | ||
| 86 | #define SOFT_RESET_SPI (1 << 8) | ||
| 87 | #define SOFT_RESET_SH (1 << 9) | ||
| 88 | #define SOFT_RESET_SX (1 << 10) | ||
| 89 | #define SOFT_RESET_TC (1 << 11) | ||
| 90 | #define SOFT_RESET_TA (1 << 12) | ||
| 91 | #define SOFT_RESET_VC (1 << 13) | ||
| 92 | #define SOFT_RESET_VGT (1 << 14) | ||
| 93 | |||
| 82 | #define GRBM_STATUS 0x8010 | 94 | #define GRBM_STATUS 0x8010 |
| 83 | #define CMDFIFO_AVAIL_MASK 0x0000000F | 95 | #define CMDFIFO_AVAIL_MASK 0x0000000F |
| 84 | #define GUI_ACTIVE (1<<31) | 96 | #define SRBM_RQ_PENDING (1 << 5) |
| 97 | #define CF_RQ_PENDING (1 << 7) | ||
| 98 | #define PF_RQ_PENDING (1 << 8) | ||
| 99 | #define GRBM_EE_BUSY (1 << 10) | ||
| 100 | #define SX_CLEAN (1 << 11) | ||
| 101 | #define DB_CLEAN (1 << 12) | ||
| 102 | #define CB_CLEAN (1 << 13) | ||
| 103 | #define TA_BUSY (1 << 14) | ||
| 104 | #define VGT_BUSY_NO_DMA (1 << 16) | ||
| 105 | #define VGT_BUSY (1 << 17) | ||
| 106 | #define SX_BUSY (1 << 20) | ||
| 107 | #define SH_BUSY (1 << 21) | ||
| 108 | #define SPI_BUSY (1 << 22) | ||
| 109 | #define SC_BUSY (1 << 24) | ||
| 110 | #define PA_BUSY (1 << 25) | ||
| 111 | #define DB_BUSY (1 << 26) | ||
| 112 | #define CP_COHERENCY_BUSY (1 << 28) | ||
| 113 | #define CP_BUSY (1 << 29) | ||
| 114 | #define CB_BUSY (1 << 30) | ||
| 115 | #define GUI_ACTIVE (1 << 31) | ||
| 116 | #define GRBM_STATUS_SE0 0x8014 | ||
| 117 | #define GRBM_STATUS_SE1 0x8018 | ||
| 118 | #define SE_SX_CLEAN (1 << 0) | ||
| 119 | #define SE_DB_CLEAN (1 << 1) | ||
| 120 | #define SE_CB_CLEAN (1 << 2) | ||
| 121 | #define SE_TA_BUSY (1 << 25) | ||
| 122 | #define SE_SX_BUSY (1 << 26) | ||
| 123 | #define SE_SPI_BUSY (1 << 27) | ||
| 124 | #define SE_SH_BUSY (1 << 28) | ||
| 125 | #define SE_SC_BUSY (1 << 29) | ||
| 126 | #define SE_DB_BUSY (1 << 30) | ||
| 127 | #define SE_CB_BUSY (1 << 31) | ||
| 85 | 128 | ||
| 86 | #define HDP_HOST_PATH_CNTL 0x2C00 | 129 | #define HDP_HOST_PATH_CNTL 0x2C00 |
| 87 | #define HDP_NONSURFACE_BASE 0x2C04 | 130 | #define HDP_NONSURFACE_BASE 0x2C04 |
| @@ -266,5 +309,21 @@ | |||
| 266 | #define WAIT_UNTIL 0x8040 | 309 | #define WAIT_UNTIL 0x8040 |
| 267 | 310 | ||
| 268 | #define SRBM_STATUS 0x0E50 | 311 | #define SRBM_STATUS 0x0E50 |
| 312 | #define SRBM_SOFT_RESET 0x0E60 | ||
| 313 | #define SRBM_SOFT_RESET_ALL_MASK 0x00FEEFA6 | ||
| 314 | #define SOFT_RESET_BIF (1 << 1) | ||
| 315 | #define SOFT_RESET_CG (1 << 2) | ||
| 316 | #define SOFT_RESET_DC (1 << 5) | ||
| 317 | #define SOFT_RESET_GRBM (1 << 8) | ||
| 318 | #define SOFT_RESET_HDP (1 << 9) | ||
| 319 | #define SOFT_RESET_IH (1 << 10) | ||
| 320 | #define SOFT_RESET_MC (1 << 11) | ||
| 321 | #define SOFT_RESET_RLC (1 << 13) | ||
| 322 | #define SOFT_RESET_ROM (1 << 14) | ||
| 323 | #define SOFT_RESET_SEM (1 << 15) | ||
| 324 | #define SOFT_RESET_VMC (1 << 17) | ||
| 325 | #define SOFT_RESET_TST (1 << 21) | ||
| 326 | #define SOFT_RESET_REGBB (1 << 22) | ||
| 327 | #define SOFT_RESET_ORB (1 << 23) | ||
| 269 | 328 | ||
| 270 | #endif | 329 | #endif |