Merge branch 'drm-next' of git://people.freedesktop.org/~airlied/linux

Pull drm merge (part 1) from Dave Airlie:
 "So first of all my tree and uapi stuff has a conflict mess, its my
  fault as the nouveau stuff didn't hit -next as were trying to rebase
  regressions out of it before we merged.

  Highlights:
   - SH mobile modesetting driver and associated helpers
   - some DRM core documentation
   - i915 modesetting rework, haswell hdmi, haswell and vlv fixes, write
     combined pte writing, ilk rc6 support,
   - nouveau: major driver rework into a hw core driver, makes features
     like SLI a lot saner to implement,
   - psb: add eDP/DP support for Cedarview
   - radeon: 2 layer page tables, async VM pte updates, better PLL
     selection for > 2 screens, better ACPI interactions

  The rest is general grab bag of fixes.

  So why part 1? well I have the exynos pull req which came in a bit
  late but was waiting for me to do something they shouldn't have and it
  looks fairly safe, and David Howells has some more header cleanups
  he'd like me to pull, that seem like a good idea, but I'd like to get
  this merge out of the way so -next dosen't get blocked."

Tons of conflicts mostly due to silly include line changes, but mostly
mindless.  A few other small semantic conflicts too, noted from Dave's
pre-merged branch.

* 'drm-next' of git://people.freedesktop.org/~airlied/linux: (447 commits)
  drm/nv98/crypt: fix fuc build with latest envyas
  drm/nouveau/devinit: fixup various issues with subdev ctor/init ordering
  drm/nv41/vm: fix and enable use of "real" pciegart
  drm/nv44/vm: fix and enable use of "real" pciegart
  drm/nv04/dmaobj: fixup vm target handling in preparation for nv4x pcie
  drm/nouveau: store supported dma mask in vmmgr
  drm/nvc0/ibus: initial implementation of subdev
  drm/nouveau/therm: add support for fan-control modes
  drm/nouveau/hwmon: rename pwm0* to pmw1* to follow hwmon's rules
  drm/nouveau/therm: calculate the pwm divisor on nv50+
  drm/nouveau/fan: rewrite the fan tachometer driver to get more precision, faster
  drm/nouveau/therm: move thermal-related functions to the therm subdev
  drm/nouveau/bios: parse the pwm divisor from the perf table
  drm/nouveau/therm: use the EXTDEV table to detect i2c monitoring devices
  drm/nouveau/therm: rework thermal table parsing
  drm/nouveau/gpio: expose the PWM/TOGGLE parameter found in the gpio vbios table
  drm/nouveau: fix pm initialization order
  drm/nouveau/bios: check that fixed tvdac gpio data is valid before using it
  drm/nouveau: log channel debug/error messages from client object rather than drm client
  drm/nouveau: have drm debugging macros build on top of core macros
  ...

1 files changed, 53 insertions, 8 deletions

diff --git a/drivers/gpu/drm/radeon/evergreen_cs.c b/drivers/gpu/drm/radeon/evergreen_cs.c
index 101acd618f67..573ed1bc6cf7 100644
--- a/drivers/gpu/drm/radeon/evergreen_cs.c
+++ b/drivers/gpu/drm/radeon/evergreen_cs.c
@@ -846,6 +846,16 @@ static int evergreen_cs_track_validate_texture(struct radeon_cs_parser *p,
                 return -EINVAL;
         }
 
+        if (!mipmap) {
+                if (llevel) {
+                        dev_warn(p->dev, "%s:%i got NULL MIP_ADDRESS relocation\n",
+                                 __func__, __LINE__);
+                        return -EINVAL;
+                } else {
+                        return 0; /* everything's ok */
+                }
+        }
+
         /* check mipmap size */
         for (i = 1; i <= llevel; i++) {
                 unsigned w, h, d;
@@ -995,7 +1005,7 @@ static int evergreen_cs_track_check(struct radeon_cs_parser *p)
  * Assume that chunk_ib_index is properly set. Will return -EINVAL
  * if packet is bigger than remaining ib size. or if packets is unknown.
  **/
-int evergreen_cs_packet_parse(struct radeon_cs_parser *p,
+static int evergreen_cs_packet_parse(struct radeon_cs_parser *p,
                               struct radeon_cs_packet *pkt,
                               unsigned idx)
 {
@@ -1081,6 +1091,27 @@ static int evergreen_cs_packet_next_reloc(struct radeon_cs_parser *p,
 }
 
 /**
+ * evergreen_cs_packet_next_is_pkt3_nop() - test if the next packet is NOP
+ * @p:          structure holding the parser context.
+ *
+ * Check if the next packet is a relocation packet3.
+ **/
+static bool evergreen_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p)
+{
+        struct radeon_cs_packet p3reloc;
+        int r;
+
+        r = evergreen_cs_packet_parse(p, &p3reloc, p->idx);
+        if (r) {
+                return false;
+        }
+        if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
+                return false;
+        }
+        return true;
+}
+
+/**
  * evergreen_cs_packet_next_vline() - parse userspace VLINE packet
  * @parser:             parser structure holding parsing context.
  *
@@ -2330,7 +2361,7 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p,
                 for (i = 0; i < (pkt->count / 8); i++) {
                         struct radeon_bo *texture, *mipmap;
                         u32 toffset, moffset;
-                        u32 size, offset;
+                        u32 size, offset, mip_address, tex_dim;
 
                         switch (G__SQ_CONSTANT_TYPE(radeon_get_ib_value(p, idx+1+(i*8)+7))) {
                         case SQ_TEX_VTX_VALID_TEXTURE:
@@ -2359,14 +2390,28 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p,
                                 }
                                 texture = reloc->robj;
                                 toffset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
+
                                 /* tex mip base */
-                                r = evergreen_cs_packet_next_reloc(p, &reloc);
-                                if (r) {
-                                        DRM_ERROR("bad SET_RESOURCE (tex)\n");
-                                        return -EINVAL;
+                                tex_dim = ib[idx+1+(i*8)+0] & 0x7;
+                                mip_address = ib[idx+1+(i*8)+3];
+
+                                if ((tex_dim == SQ_TEX_DIM_2D_MSAA || tex_dim == SQ_TEX_DIM_2D_ARRAY_MSAA) &&
+                                    !mip_address &&
+                                    !evergreen_cs_packet_next_is_pkt3_nop(p)) {
+                                        /* MIP_ADDRESS should point to FMASK for an MSAA texture.
+                                         * It should be 0 if FMASK is disabled. */
+                                        moffset = 0;
+                                        mipmap = NULL;
+                                } else {
+                                        r = evergreen_cs_packet_next_reloc(p, &reloc);
+                                        if (r) {
+                                                DRM_ERROR("bad SET_RESOURCE (tex)\n");
+                                                return -EINVAL;
+                                        }
+                                        moffset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
+                                        mipmap = reloc->robj;
                                 }
-                                moffset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
-                                mipmap = reloc->robj;
+
                                 r = evergreen_cs_track_validate_texture(p, texture, mipmap, idx+1+(i*8));
                                 if (r)
                                         return r;