drm/radeon/kms: rework texture cache flush in r6xx+ blit code

Move the TC flush before the texture setup to match mesa and
the ddx. Also, move the TC flush into the texture setup
function.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

1 files changed, 4 insertions, 1 deletions

diff --git a/drivers/gpu/drm/radeon/evergreen_blit_kms.c b/drivers/gpu/drm/radeon/evergreen_blit_kms.c
index dcf11bbc06d9..879f7335029e 100644
--- a/drivers/gpu/drm/radeon/evergreen_blit_kms.c
+++ b/drivers/gpu/drm/radeon/evergreen_blit_kms.c
@@ -174,7 +174,7 @@ set_vtx_resource(struct radeon_device *rdev, u64 gpu_addr)
 static void
 set_tex_resource(struct radeon_device *rdev,
                  int format, int w, int h, int pitch,
-                 u64 gpu_addr)
+                 u64 gpu_addr, u32 size)
 {
         u32 sq_tex_resource_word0, sq_tex_resource_word1;
         u32 sq_tex_resource_word4, sq_tex_resource_word7;
@@ -196,6 +196,9 @@ set_tex_resource(struct radeon_device *rdev,
         sq_tex_resource_word7 = format |
                 S__SQ_CONSTANT_TYPE(SQ_TEX_VTX_VALID_TEXTURE);
 
+        cp_set_surface_sync(rdev,
+                            PACKET3_TC_ACTION_ENA, size, gpu_addr);
+
         radeon_ring_write(rdev, PACKET3(PACKET3_SET_RESOURCE, 8));
         radeon_ring_write(rdev, 0);
         radeon_ring_write(rdev, sq_tex_resource_word0);