drm/nouveau/pm: some more delays for ddr3 reclocking

These numbers from the binary driver's daemon scripts, and fix the transition
to perflvl 3 on my T510.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

1 files changed, 1 insertions, 0 deletions

diff --git a/drivers/gpu/drm/nouveau/nva3_pm.c b/drivers/gpu/drm/nouveau/nva3_pm.c
index d51e8f86b4d5..798829353fb6 100644
--- a/drivers/gpu/drm/nouveau/nva3_pm.c
+++ b/drivers/gpu/drm/nouveau/nva3_pm.c
@@ -344,6 +344,7 @@ mclk_refresh_self(struct nouveau_mem_exec_func *exec, bool enable)
 static void
 mclk_wait(struct nouveau_mem_exec_func *exec, u32 nsec)
 {
+        volatile u32 post = nv_rd32(exec->dev, 0); (void)post;
         udelay((nsec + 500) / 1000);
 }