diff options
author | Ben Skeggs <bskeggs@redhat.com> | 2011-11-04 21:55:39 -0400 |
---|---|---|
committer | Ben Skeggs <bskeggs@redhat.com> | 2011-12-21 04:01:30 -0500 |
commit | 971fa6b46df2edc02c9937938d9ba1d6d6724e74 (patch) | |
tree | 52417eea301426aec1421275ec188db212d903fd /drivers/gpu/drm/nouveau/nva3_copy.fuc | |
parent | d2491567cdbcb87b2682e0948a69d73c4dd8987e (diff) |
drm/nva3/copy: update fuc source for latest envytools
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau/nva3_copy.fuc')
-rw-r--r-- | drivers/gpu/drm/nouveau/nva3_copy.fuc | 260 |
1 files changed, 131 insertions, 129 deletions
diff --git a/drivers/gpu/drm/nouveau/nva3_copy.fuc b/drivers/gpu/drm/nouveau/nva3_copy.fuc index eaf35f8321ee..0cec534f03e9 100644 --- a/drivers/gpu/drm/nouveau/nva3_copy.fuc +++ b/drivers/gpu/drm/nouveau/nva3_copy.fuc | |||
@@ -31,8 +31,9 @@ | |||
31 | */ | 31 | */ |
32 | 32 | ||
33 | ifdef(`NVA3', | 33 | ifdef(`NVA3', |
34 | .section nva3_pcopy_data, | 34 | .section #nva3_pcopy_data |
35 | .section nvc0_pcopy_data | 35 | , |
36 | .section #nvc0_pcopy_data | ||
36 | ) | 37 | ) |
37 | 38 | ||
38 | ctx_object: .b32 0 | 39 | ctx_object: .b32 0 |
@@ -42,7 +43,7 @@ ctx_dma_query: .b32 0 | |||
42 | ctx_dma_src: .b32 0 | 43 | ctx_dma_src: .b32 0 |
43 | ctx_dma_dst: .b32 0 | 44 | ctx_dma_dst: .b32 0 |
44 | ,) | 45 | ,) |
45 | .equ ctx_dma_count 3 | 46 | .equ #ctx_dma_count 3 |
46 | ctx_query_address_high: .b32 0 | 47 | ctx_query_address_high: .b32 0 |
47 | ctx_query_address_low: .b32 0 | 48 | ctx_query_address_low: .b32 0 |
48 | ctx_query_counter: .b32 0 | 49 | ctx_query_counter: .b32 0 |
@@ -78,64 +79,65 @@ ctx_ycnt: .b32 0 | |||
78 | dispatch_table: | 79 | dispatch_table: |
79 | // mthd 0x0000, NAME | 80 | // mthd 0x0000, NAME |
80 | .b16 0x000 1 | 81 | .b16 0x000 1 |
81 | .b32 ctx_object ~0xffffffff | 82 | .b32 #ctx_object ~0xffffffff |
82 | // mthd 0x0100, NOP | 83 | // mthd 0x0100, NOP |
83 | .b16 0x040 1 | 84 | .b16 0x040 1 |
84 | .b32 0x00010000 + cmd_nop ~0xffffffff | 85 | .b32 0x00010000 + #cmd_nop ~0xffffffff |
85 | // mthd 0x0140, PM_TRIGGER | 86 | // mthd 0x0140, PM_TRIGGER |
86 | .b16 0x050 1 | 87 | .b16 0x050 1 |
87 | .b32 0x00010000 + cmd_pm_trigger ~0xffffffff | 88 | .b32 0x00010000 + #cmd_pm_trigger ~0xffffffff |
88 | ifdef(`NVA3', ` | 89 | ifdef(`NVA3', ` |
89 | // mthd 0x0180-0x018c, DMA_ | 90 | // mthd 0x0180-0x018c, DMA_ |
90 | .b16 0x060 ctx_dma_count | 91 | .b16 0x060 #ctx_dma_count |
91 | dispatch_dma: | 92 | dispatch_dma: |
92 | .b32 0x00010000 + cmd_dma ~0xffffffff | 93 | .b32 0x00010000 + #cmd_dma ~0xffffffff |
93 | .b32 0x00010000 + cmd_dma ~0xffffffff | 94 | .b32 0x00010000 + #cmd_dma ~0xffffffff |
94 | .b32 0x00010000 + cmd_dma ~0xffffffff | 95 | .b32 0x00010000 + #cmd_dma ~0xffffffff |
95 | ',) | 96 | ',) |
96 | // mthd 0x0200-0x0218, SRC_TILE | 97 | // mthd 0x0200-0x0218, SRC_TILE |
97 | .b16 0x80 7 | 98 | .b16 0x80 7 |
98 | .b32 ctx_src_tile_mode ~0x00000fff | 99 | .b32 #ctx_src_tile_mode ~0x00000fff |
99 | .b32 ctx_src_xsize ~0x0007ffff | 100 | .b32 #ctx_src_xsize ~0x0007ffff |
100 | .b32 ctx_src_ysize ~0x00001fff | 101 | .b32 #ctx_src_ysize ~0x00001fff |
101 | .b32 ctx_src_zsize ~0x000007ff | 102 | .b32 #ctx_src_zsize ~0x000007ff |
102 | .b32 ctx_src_zoff ~0x00000fff | 103 | .b32 #ctx_src_zoff ~0x00000fff |
103 | .b32 ctx_src_xoff ~0x0007ffff | 104 | .b32 #ctx_src_xoff ~0x0007ffff |
104 | .b32 ctx_src_yoff ~0x00001fff | 105 | .b32 #ctx_src_yoff ~0x00001fff |
105 | // mthd 0x0220-0x0238, DST_TILE | 106 | // mthd 0x0220-0x0238, DST_TILE |
106 | .b16 0x88 7 | 107 | .b16 0x88 7 |
107 | .b32 ctx_dst_tile_mode ~0x00000fff | 108 | .b32 #ctx_dst_tile_mode ~0x00000fff |
108 | .b32 ctx_dst_xsize ~0x0007ffff | 109 | .b32 #ctx_dst_xsize ~0x0007ffff |
109 | .b32 ctx_dst_ysize ~0x00001fff | 110 | .b32 #ctx_dst_ysize ~0x00001fff |
110 | .b32 ctx_dst_zsize ~0x000007ff | 111 | .b32 #ctx_dst_zsize ~0x000007ff |
111 | .b32 ctx_dst_zoff ~0x00000fff | 112 | .b32 #ctx_dst_zoff ~0x00000fff |
112 | .b32 ctx_dst_xoff ~0x0007ffff | 113 | .b32 #ctx_dst_xoff ~0x0007ffff |
113 | .b32 ctx_dst_yoff ~0x00001fff | 114 | .b32 #ctx_dst_yoff ~0x00001fff |
114 | // mthd 0x0300-0x0304, EXEC, WRCACHE_FLUSH | 115 | // mthd 0x0300-0x0304, EXEC, WRCACHE_FLUSH |
115 | .b16 0xc0 2 | 116 | .b16 0xc0 2 |
116 | .b32 0x00010000 + cmd_exec ~0xffffffff | 117 | .b32 0x00010000 + #cmd_exec ~0xffffffff |
117 | .b32 0x00010000 + cmd_wrcache_flush ~0xffffffff | 118 | .b32 0x00010000 + #cmd_wrcache_flush ~0xffffffff |
118 | // mthd 0x030c-0x0340, various stuff | 119 | // mthd 0x030c-0x0340, various stuff |
119 | .b16 0xc3 14 | 120 | .b16 0xc3 14 |
120 | .b32 ctx_src_address_high ~0x000000ff | 121 | .b32 #ctx_src_address_high ~0x000000ff |
121 | .b32 ctx_src_address_low ~0xfffffff0 | 122 | .b32 #ctx_src_address_low ~0xfffffff0 |
122 | .b32 ctx_dst_address_high ~0x000000ff | 123 | .b32 #ctx_dst_address_high ~0x000000ff |
123 | .b32 ctx_dst_address_low ~0xfffffff0 | 124 | .b32 #ctx_dst_address_low ~0xfffffff0 |
124 | .b32 ctx_src_pitch ~0x0007ffff | 125 | .b32 #ctx_src_pitch ~0x0007ffff |
125 | .b32 ctx_dst_pitch ~0x0007ffff | 126 | .b32 #ctx_dst_pitch ~0x0007ffff |
126 | .b32 ctx_xcnt ~0x0000ffff | 127 | .b32 #ctx_xcnt ~0x0000ffff |
127 | .b32 ctx_ycnt ~0x00001fff | 128 | .b32 #ctx_ycnt ~0x00001fff |
128 | .b32 ctx_format ~0x0333ffff | 129 | .b32 #ctx_format ~0x0333ffff |
129 | .b32 ctx_swz_const0 ~0xffffffff | 130 | .b32 #ctx_swz_const0 ~0xffffffff |
130 | .b32 ctx_swz_const1 ~0xffffffff | 131 | .b32 #ctx_swz_const1 ~0xffffffff |
131 | .b32 ctx_query_address_high ~0x000000ff | 132 | .b32 #ctx_query_address_high ~0x000000ff |
132 | .b32 ctx_query_address_low ~0xffffffff | 133 | .b32 #ctx_query_address_low ~0xffffffff |
133 | .b32 ctx_query_counter ~0xffffffff | 134 | .b32 #ctx_query_counter ~0xffffffff |
134 | .b16 0x800 0 | 135 | .b16 0x800 0 |
135 | 136 | ||
136 | ifdef(`NVA3', | 137 | ifdef(`NVA3', |
137 | .section nva3_pcopy_code, | 138 | .section #nva3_pcopy_code |
138 | .section nvc0_pcopy_code | 139 | , |
140 | .section #nvc0_pcopy_code | ||
139 | ) | 141 | ) |
140 | 142 | ||
141 | main: | 143 | main: |
@@ -143,7 +145,7 @@ main: | |||
143 | mov $sp $r0 | 145 | mov $sp $r0 |
144 | 146 | ||
145 | // setup i0 handler and route fifo and ctxswitch to it | 147 | // setup i0 handler and route fifo and ctxswitch to it |
146 | mov $r1 ih | 148 | mov $r1 #ih |
147 | mov $iv0 $r1 | 149 | mov $iv0 $r1 |
148 | mov $r1 0x400 | 150 | mov $r1 0x400 |
149 | movw $r2 0xfff3 | 151 | movw $r2 0xfff3 |
@@ -164,19 +166,19 @@ main: | |||
164 | bset $flags $p0 | 166 | bset $flags $p0 |
165 | spin: | 167 | spin: |
166 | sleep $p0 | 168 | sleep $p0 |
167 | bra spin | 169 | bra #spin |
168 | 170 | ||
169 | // i0 handler | 171 | // i0 handler |
170 | ih: | 172 | ih: |
171 | iord $r1 I[$r0 + 0x200] | 173 | iord $r1 I[$r0 + 0x200] |
172 | 174 | ||
173 | and $r2 $r1 0x00000008 | 175 | and $r2 $r1 0x00000008 |
174 | bra e ih_no_chsw | 176 | bra e #ih_no_chsw |
175 | call chsw | 177 | call #chsw |
176 | ih_no_chsw: | 178 | ih_no_chsw: |
177 | and $r2 $r1 0x00000004 | 179 | and $r2 $r1 0x00000004 |
178 | bra e ih_no_cmd | 180 | bra e #ih_no_cmd |
179 | call dispatch | 181 | call #dispatch |
180 | 182 | ||
181 | ih_no_cmd: | 183 | ih_no_cmd: |
182 | and $r1 $r1 0x0000000c | 184 | and $r1 $r1 0x0000000c |
@@ -235,9 +237,9 @@ ifdef(`NVA3', ` | |||
235 | sethi $r4 0x60000 | 237 | sethi $r4 0x60000 |
236 | 238 | ||
237 | // swap! | 239 | // swap! |
238 | bra $p1 swctx_load | 240 | bra $p1 #swctx_load |
239 | xdst $r0 $r4 | 241 | xdst $r0 $r4 |
240 | bra swctx_done | 242 | bra #swctx_done |
241 | swctx_load: | 243 | swctx_load: |
242 | xdld $r0 $r4 | 244 | xdld $r0 $r4 |
243 | swctx_done: | 245 | swctx_done: |
@@ -251,9 +253,9 @@ chsw: | |||
251 | 253 | ||
252 | // if it's active, unload it and return | 254 | // if it's active, unload it and return |
253 | xbit $r15 $r3 0x1e | 255 | xbit $r15 $r3 0x1e |
254 | bra e chsw_no_unload | 256 | bra e #chsw_no_unload |
255 | bclr $flags $p1 | 257 | bclr $flags $p1 |
256 | call swctx | 258 | call #swctx |
257 | bclr $r3 0x1e | 259 | bclr $r3 0x1e |
258 | iowr I[$r2] $r3 | 260 | iowr I[$r2] $r3 |
259 | mov $r4 1 | 261 | mov $r4 1 |
@@ -266,20 +268,20 @@ chsw: | |||
266 | 268 | ||
267 | // is there a channel waiting to be loaded? | 269 | // is there a channel waiting to be loaded? |
268 | xbit $r13 $r3 0x1e | 270 | xbit $r13 $r3 0x1e |
269 | bra e chsw_finish_load | 271 | bra e #chsw_finish_load |
270 | bset $flags $p1 | 272 | bset $flags $p1 |
271 | call swctx | 273 | call #swctx |
272 | ifdef(`NVA3', | 274 | ifdef(`NVA3', |
273 | // load dma objects back into TARGET regs | 275 | // load dma objects back into TARGET regs |
274 | mov $r5 ctx_dma | 276 | mov $r5 #ctx_dma |
275 | mov $r6 ctx_dma_count | 277 | mov $r6 #ctx_dma_count |
276 | chsw_load_ctx_dma: | 278 | chsw_load_ctx_dma: |
277 | ld b32 $r7 D[$r5 + $r6 * 4] | 279 | ld b32 $r7 D[$r5 + $r6 * 4] |
278 | add b32 $r8 $r6 0x180 | 280 | add b32 $r8 $r6 0x180 |
279 | shl b32 $r8 8 | 281 | shl b32 $r8 8 |
280 | iowr I[$r8] $r7 | 282 | iowr I[$r8] $r7 |
281 | sub b32 $r6 1 | 283 | sub b32 $r6 1 |
282 | bra nc chsw_load_ctx_dma | 284 | bra nc #chsw_load_ctx_dma |
283 | ,) | 285 | ,) |
284 | 286 | ||
285 | chsw_finish_load: | 287 | chsw_finish_load: |
@@ -297,7 +299,7 @@ dispatch: | |||
297 | shl b32 $r2 0x10 | 299 | shl b32 $r2 0x10 |
298 | 300 | ||
299 | // lookup method in the dispatch table, ILLEGAL_MTHD if not found | 301 | // lookup method in the dispatch table, ILLEGAL_MTHD if not found |
300 | mov $r5 dispatch_table | 302 | mov $r5 #dispatch_table |
301 | clear b32 $r6 | 303 | clear b32 $r6 |
302 | clear b32 $r7 | 304 | clear b32 $r7 |
303 | dispatch_loop: | 305 | dispatch_loop: |
@@ -305,14 +307,14 @@ dispatch: | |||
305 | ld b16 $r7 D[$r5 + 2] | 307 | ld b16 $r7 D[$r5 + 2] |
306 | add b32 $r5 4 | 308 | add b32 $r5 4 |
307 | cmpu b32 $r4 $r6 | 309 | cmpu b32 $r4 $r6 |
308 | bra c dispatch_illegal_mthd | 310 | bra c #dispatch_illegal_mthd |
309 | add b32 $r7 $r6 | 311 | add b32 $r7 $r6 |
310 | cmpu b32 $r4 $r7 | 312 | cmpu b32 $r4 $r7 |
311 | bra c dispatch_valid_mthd | 313 | bra c #dispatch_valid_mthd |
312 | sub b32 $r7 $r6 | 314 | sub b32 $r7 $r6 |
313 | shl b32 $r7 3 | 315 | shl b32 $r7 3 |
314 | add b32 $r5 $r7 | 316 | add b32 $r5 $r7 |
315 | bra dispatch_loop | 317 | bra #dispatch_loop |
316 | 318 | ||
317 | // ensure no bits set in reserved fields, INVALID_BITFIELD | 319 | // ensure no bits set in reserved fields, INVALID_BITFIELD |
318 | dispatch_valid_mthd: | 320 | dispatch_valid_mthd: |
@@ -322,20 +324,20 @@ dispatch: | |||
322 | ld b32 $r5 D[$r4 + 4] | 324 | ld b32 $r5 D[$r4 + 4] |
323 | and $r5 $r3 | 325 | and $r5 $r3 |
324 | cmpu b32 $r5 0 | 326 | cmpu b32 $r5 0 |
325 | bra ne dispatch_invalid_bitfield | 327 | bra ne #dispatch_invalid_bitfield |
326 | 328 | ||
327 | // depending on dispatch flags: execute method, or save data as state | 329 | // depending on dispatch flags: execute method, or save data as state |
328 | ld b16 $r5 D[$r4 + 0] | 330 | ld b16 $r5 D[$r4 + 0] |
329 | ld b16 $r6 D[$r4 + 2] | 331 | ld b16 $r6 D[$r4 + 2] |
330 | cmpu b32 $r6 0 | 332 | cmpu b32 $r6 0 |
331 | bra ne dispatch_cmd | 333 | bra ne #dispatch_cmd |
332 | st b32 D[$r5] $r3 | 334 | st b32 D[$r5] $r3 |
333 | bra dispatch_done | 335 | bra #dispatch_done |
334 | dispatch_cmd: | 336 | dispatch_cmd: |
335 | bclr $flags $p1 | 337 | bclr $flags $p1 |
336 | call $r5 | 338 | call $r5 |
337 | bra $p1 dispatch_error | 339 | bra $p1 #dispatch_error |
338 | bra dispatch_done | 340 | bra #dispatch_done |
339 | 341 | ||
340 | dispatch_invalid_bitfield: | 342 | dispatch_invalid_bitfield: |
341 | or $r2 2 | 343 | or $r2 2 |
@@ -353,7 +355,7 @@ dispatch: | |||
353 | iord $r2 I[$r0 + 0x200] | 355 | iord $r2 I[$r0 + 0x200] |
354 | and $r2 0x40 | 356 | and $r2 0x40 |
355 | cmpu b32 $r2 0 | 357 | cmpu b32 $r2 0 |
356 | bra ne hostirq_wait | 358 | bra ne #hostirq_wait |
357 | 359 | ||
358 | dispatch_done: | 360 | dispatch_done: |
359 | mov $r2 0x1d00 | 361 | mov $r2 0x1d00 |
@@ -409,10 +411,10 @@ ifdef(`NVA3', | |||
409 | // $r2: hostirq state | 411 | // $r2: hostirq state |
410 | // $r3: data | 412 | // $r3: data |
411 | cmd_dma: | 413 | cmd_dma: |
412 | sub b32 $r4 dispatch_dma | 414 | sub b32 $r4 #dispatch_dma |
413 | shr b32 $r4 1 | 415 | shr b32 $r4 1 |
414 | bset $r3 0x1e | 416 | bset $r3 0x1e |
415 | st b32 D[$r4 + ctx_dma] $r3 | 417 | st b32 D[$r4 + #ctx_dma] $r3 |
416 | add b32 $r4 0x600 | 418 | add b32 $r4 0x600 |
417 | shl b32 $r4 6 | 419 | shl b32 $r4 6 |
418 | iowr I[$r4] $r3 | 420 | iowr I[$r4] $r3 |
@@ -430,7 +432,7 @@ cmd_exec_set_format: | |||
430 | st b32 D[$sp + 0x0c] $r0 | 432 | st b32 D[$sp + 0x0c] $r0 |
431 | 433 | ||
432 | // extract cpp, src_ncomp and dst_ncomp from FORMAT | 434 | // extract cpp, src_ncomp and dst_ncomp from FORMAT |
433 | ld b32 $r4 D[$r0 + ctx_format] | 435 | ld b32 $r4 D[$r0 + #ctx_format] |
434 | extr $r5 $r4 16:17 | 436 | extr $r5 $r4 16:17 |
435 | add b32 $r5 1 | 437 | add b32 $r5 1 |
436 | extr $r6 $r4 20:21 | 438 | extr $r6 $r4 20:21 |
@@ -448,22 +450,22 @@ cmd_exec_set_format: | |||
448 | clear b32 $r11 | 450 | clear b32 $r11 |
449 | bpc_loop: | 451 | bpc_loop: |
450 | cmpu b8 $r10 4 | 452 | cmpu b8 $r10 4 |
451 | bra nc cmp_c0 | 453 | bra nc #cmp_c0 |
452 | mulu $r12 $r10 $r5 | 454 | mulu $r12 $r10 $r5 |
453 | add b32 $r12 $r11 | 455 | add b32 $r12 $r11 |
454 | bset $flags $p2 | 456 | bset $flags $p2 |
455 | bra bpc_next | 457 | bra #bpc_next |
456 | cmp_c0: | 458 | cmp_c0: |
457 | bra ne cmp_c1 | 459 | bra ne #cmp_c1 |
458 | mov $r12 0x10 | 460 | mov $r12 0x10 |
459 | add b32 $r12 $r11 | 461 | add b32 $r12 $r11 |
460 | bra bpc_next | 462 | bra #bpc_next |
461 | cmp_c1: | 463 | cmp_c1: |
462 | cmpu b8 $r10 6 | 464 | cmpu b8 $r10 6 |
463 | bra nc cmp_zero | 465 | bra nc #cmp_zero |
464 | mov $r12 0x14 | 466 | mov $r12 0x14 |
465 | add b32 $r12 $r11 | 467 | add b32 $r12 $r11 |
466 | bra bpc_next | 468 | bra #bpc_next |
467 | cmp_zero: | 469 | cmp_zero: |
468 | mov $r12 0x80 | 470 | mov $r12 0x80 |
469 | bpc_next: | 471 | bpc_next: |
@@ -471,22 +473,22 @@ cmd_exec_set_format: | |||
471 | add b32 $r8 1 | 473 | add b32 $r8 1 |
472 | add b32 $r11 1 | 474 | add b32 $r11 1 |
473 | cmpu b32 $r11 $r5 | 475 | cmpu b32 $r11 $r5 |
474 | bra c bpc_loop | 476 | bra c #bpc_loop |
475 | add b32 $r9 1 | 477 | add b32 $r9 1 |
476 | cmpu b32 $r9 $r7 | 478 | cmpu b32 $r9 $r7 |
477 | bra c ncomp_loop | 479 | bra c #ncomp_loop |
478 | 480 | ||
479 | // SRC_XCNT = (xcnt * src_cpp), or 0 if no src ref in swz (hw will hang) | 481 | // SRC_XCNT = (xcnt * src_cpp), or 0 if no src ref in swz (hw will hang) |
480 | mulu $r6 $r5 | 482 | mulu $r6 $r5 |
481 | st b32 D[$r0 + ctx_src_cpp] $r6 | 483 | st b32 D[$r0 + #ctx_src_cpp] $r6 |
482 | ld b32 $r8 D[$r0 + ctx_xcnt] | 484 | ld b32 $r8 D[$r0 + #ctx_xcnt] |
483 | mulu $r6 $r8 | 485 | mulu $r6 $r8 |
484 | bra $p2 dst_xcnt | 486 | bra $p2 #dst_xcnt |
485 | clear b32 $r6 | 487 | clear b32 $r6 |
486 | 488 | ||
487 | dst_xcnt: | 489 | dst_xcnt: |
488 | mulu $r7 $r5 | 490 | mulu $r7 $r5 |
489 | st b32 D[$r0 + ctx_dst_cpp] $r7 | 491 | st b32 D[$r0 + #ctx_dst_cpp] $r7 |
490 | mulu $r7 $r8 | 492 | mulu $r7 $r8 |
491 | 493 | ||
492 | mov $r5 0x810 | 494 | mov $r5 0x810 |
@@ -494,10 +496,10 @@ cmd_exec_set_format: | |||
494 | iowr I[$r5 + 0x000] $r6 | 496 | iowr I[$r5 + 0x000] $r6 |
495 | iowr I[$r5 + 0x100] $r7 | 497 | iowr I[$r5 + 0x100] $r7 |
496 | add b32 $r5 0x800 | 498 | add b32 $r5 0x800 |
497 | ld b32 $r6 D[$r0 + ctx_dst_cpp] | 499 | ld b32 $r6 D[$r0 + #ctx_dst_cpp] |
498 | sub b32 $r6 1 | 500 | sub b32 $r6 1 |
499 | shl b32 $r6 8 | 501 | shl b32 $r6 8 |
500 | ld b32 $r7 D[$r0 + ctx_src_cpp] | 502 | ld b32 $r7 D[$r0 + #ctx_src_cpp] |
501 | sub b32 $r7 1 | 503 | sub b32 $r7 1 |
502 | or $r6 $r7 | 504 | or $r6 $r7 |
503 | iowr I[$r5 + 0x000] $r6 | 505 | iowr I[$r5 + 0x000] $r6 |
@@ -511,9 +513,9 @@ cmd_exec_set_format: | |||
511 | ld b32 $r6 D[$sp + 0x0c] | 513 | ld b32 $r6 D[$sp + 0x0c] |
512 | iowr I[$r5 + 0x300] $r6 | 514 | iowr I[$r5 + 0x300] $r6 |
513 | add b32 $r5 0x400 | 515 | add b32 $r5 0x400 |
514 | ld b32 $r6 D[$r0 + ctx_swz_const0] | 516 | ld b32 $r6 D[$r0 + #ctx_swz_const0] |
515 | iowr I[$r5 + 0x000] $r6 | 517 | iowr I[$r5 + 0x000] $r6 |
516 | ld b32 $r6 D[$r0 + ctx_swz_const1] | 518 | ld b32 $r6 D[$r0 + #ctx_swz_const1] |
517 | iowr I[$r5 + 0x100] $r6 | 519 | iowr I[$r5 + 0x100] $r6 |
518 | add $sp 0x10 | 520 | add $sp 0x10 |
519 | ret | 521 | ret |
@@ -543,7 +545,7 @@ cmd_exec_set_format: | |||
543 | // | 545 | // |
544 | cmd_exec_set_surface_tiled: | 546 | cmd_exec_set_surface_tiled: |
545 | // translate TILE_MODE into Tp, Th, Td shift values | 547 | // translate TILE_MODE into Tp, Th, Td shift values |
546 | ld b32 $r7 D[$r5 + ctx_src_tile_mode] | 548 | ld b32 $r7 D[$r5 + #ctx_src_tile_mode] |
547 | extr $r9 $r7 8:11 | 549 | extr $r9 $r7 8:11 |
548 | extr $r8 $r7 4:7 | 550 | extr $r8 $r7 4:7 |
549 | ifdef(`NVA3', | 551 | ifdef(`NVA3', |
@@ -553,9 +555,9 @@ ifdef(`NVA3', | |||
553 | ) | 555 | ) |
554 | extr $r7 $r7 0:3 | 556 | extr $r7 $r7 0:3 |
555 | cmp b32 $r7 0xe | 557 | cmp b32 $r7 0xe |
556 | bra ne xtile64 | 558 | bra ne #xtile64 |
557 | mov $r7 4 | 559 | mov $r7 4 |
558 | bra xtileok | 560 | bra #xtileok |
559 | xtile64: | 561 | xtile64: |
560 | xbit $r7 $flags $p2 | 562 | xbit $r7 $flags $p2 |
561 | add b32 $r7 17 | 563 | add b32 $r7 17 |
@@ -565,8 +567,8 @@ ifdef(`NVA3', | |||
565 | 567 | ||
566 | // Op = (x * cpp) & ((1 << Tp) - 1) | 568 | // Op = (x * cpp) & ((1 << Tp) - 1) |
567 | // Tx = (x * cpp) >> Tp | 569 | // Tx = (x * cpp) >> Tp |
568 | ld b32 $r10 D[$r5 + ctx_src_xoff] | 570 | ld b32 $r10 D[$r5 + #ctx_src_xoff] |
569 | ld b32 $r11 D[$r5 + ctx_src_cpp] | 571 | ld b32 $r11 D[$r5 + #ctx_src_cpp] |
570 | mulu $r10 $r11 | 572 | mulu $r10 $r11 |
571 | mov $r11 1 | 573 | mov $r11 1 |
572 | shl b32 $r11 $r7 | 574 | shl b32 $r11 $r7 |
@@ -576,7 +578,7 @@ ifdef(`NVA3', | |||
576 | 578 | ||
577 | // Tyo = y & ((1 << Th) - 1) | 579 | // Tyo = y & ((1 << Th) - 1) |
578 | // Ty = y >> Th | 580 | // Ty = y >> Th |
579 | ld b32 $r13 D[$r5 + ctx_src_yoff] | 581 | ld b32 $r13 D[$r5 + #ctx_src_yoff] |
580 | mov $r14 1 | 582 | mov $r14 1 |
581 | shl b32 $r14 $r8 | 583 | shl b32 $r14 $r8 |
582 | sub b32 $r14 1 | 584 | sub b32 $r14 1 |
@@ -598,8 +600,8 @@ ifdef(`NVA3', | |||
598 | add b32 $r12 $r11 | 600 | add b32 $r12 $r11 |
599 | 601 | ||
600 | // nTx = ((w * cpp) + ((1 << Tp) - 1) >> Tp) | 602 | // nTx = ((w * cpp) + ((1 << Tp) - 1) >> Tp) |
601 | ld b32 $r15 D[$r5 + ctx_src_xsize] | 603 | ld b32 $r15 D[$r5 + #ctx_src_xsize] |
602 | ld b32 $r11 D[$r5 + ctx_src_cpp] | 604 | ld b32 $r11 D[$r5 + #ctx_src_cpp] |
603 | mulu $r15 $r11 | 605 | mulu $r15 $r11 |
604 | mov $r11 1 | 606 | mov $r11 1 |
605 | shl b32 $r11 $r7 | 607 | shl b32 $r11 $r7 |
@@ -609,7 +611,7 @@ ifdef(`NVA3', | |||
609 | push $r15 | 611 | push $r15 |
610 | 612 | ||
611 | // nTy = (h + ((1 << Th) - 1)) >> Th | 613 | // nTy = (h + ((1 << Th) - 1)) >> Th |
612 | ld b32 $r15 D[$r5 + ctx_src_ysize] | 614 | ld b32 $r15 D[$r5 + #ctx_src_ysize] |
613 | mov $r11 1 | 615 | mov $r11 1 |
614 | shl b32 $r11 $r8 | 616 | shl b32 $r11 $r8 |
615 | sub b32 $r11 1 | 617 | sub b32 $r11 1 |
@@ -629,7 +631,7 @@ ifdef(`NVA3', | |||
629 | // Tz = z >> Td | 631 | // Tz = z >> Td |
630 | // Op += Tzo << Tys | 632 | // Op += Tzo << Tys |
631 | // Ts = Tys + Td | 633 | // Ts = Tys + Td |
632 | ld b32 $r8 D[$r5 + ctx_src_zoff] | 634 | ld b32 $r8 D[$r5 + #ctx_src_zoff] |
633 | mov $r14 1 | 635 | mov $r14 1 |
634 | shl b32 $r14 $r9 | 636 | shl b32 $r14 $r9 |
635 | sub b32 $r14 1 | 637 | sub b32 $r14 1 |
@@ -656,8 +658,8 @@ ifdef(`NVA3', | |||
656 | 658 | ||
657 | // SRC_ADDRESS_LOW = (Ot + Op) & 0xffffffff | 659 | // SRC_ADDRESS_LOW = (Ot + Op) & 0xffffffff |
658 | // CFG_ADDRESS_HIGH |= ((Ot + Op) >> 32) << 16 | 660 | // CFG_ADDRESS_HIGH |= ((Ot + Op) >> 32) << 16 |
659 | ld b32 $r7 D[$r5 + ctx_src_address_low] | 661 | ld b32 $r7 D[$r5 + #ctx_src_address_low] |
660 | ld b32 $r8 D[$r5 + ctx_src_address_high] | 662 | ld b32 $r8 D[$r5 + #ctx_src_address_high] |
661 | add b32 $r10 $r12 | 663 | add b32 $r10 $r12 |
662 | add b32 $r7 $r10 | 664 | add b32 $r7 $r10 |
663 | adc b32 $r8 0 | 665 | adc b32 $r8 0 |
@@ -677,14 +679,14 @@ cmd_exec_set_surface_linear: | |||
677 | xbit $r6 $flags $p2 | 679 | xbit $r6 $flags $p2 |
678 | add b32 $r6 0x202 | 680 | add b32 $r6 0x202 |
679 | shl b32 $r6 8 | 681 | shl b32 $r6 8 |
680 | ld b32 $r7 D[$r5 + ctx_src_address_low] | 682 | ld b32 $r7 D[$r5 + #ctx_src_address_low] |
681 | iowr I[$r6 + 0x000] $r7 | 683 | iowr I[$r6 + 0x000] $r7 |
682 | add b32 $r6 0x400 | 684 | add b32 $r6 0x400 |
683 | ld b32 $r7 D[$r5 + ctx_src_address_high] | 685 | ld b32 $r7 D[$r5 + #ctx_src_address_high] |
684 | shl b32 $r7 16 | 686 | shl b32 $r7 16 |
685 | iowr I[$r6 + 0x000] $r7 | 687 | iowr I[$r6 + 0x000] $r7 |
686 | add b32 $r6 0x400 | 688 | add b32 $r6 0x400 |
687 | ld b32 $r7 D[$r5 + ctx_src_pitch] | 689 | ld b32 $r7 D[$r5 + #ctx_src_pitch] |
688 | iowr I[$r6 + 0x000] $r7 | 690 | iowr I[$r6 + 0x000] $r7 |
689 | ret | 691 | ret |
690 | 692 | ||
@@ -697,7 +699,7 @@ cmd_exec_wait: | |||
697 | loop: | 699 | loop: |
698 | iord $r1 I[$r0] | 700 | iord $r1 I[$r0] |
699 | and $r1 1 | 701 | and $r1 1 |
700 | bra ne loop | 702 | bra ne #loop |
701 | pop $r1 | 703 | pop $r1 |
702 | pop $r0 | 704 | pop $r0 |
703 | ret | 705 | ret |
@@ -705,18 +707,18 @@ cmd_exec_wait: | |||
705 | cmd_exec_query: | 707 | cmd_exec_query: |
706 | // if QUERY_SHORT not set, write out { -, 0, TIME_LO, TIME_HI } | 708 | // if QUERY_SHORT not set, write out { -, 0, TIME_LO, TIME_HI } |
707 | xbit $r4 $r3 13 | 709 | xbit $r4 $r3 13 |
708 | bra ne query_counter | 710 | bra ne #query_counter |
709 | call cmd_exec_wait | 711 | call #cmd_exec_wait |
710 | mov $r4 0x80c | 712 | mov $r4 0x80c |
711 | shl b32 $r4 6 | 713 | shl b32 $r4 6 |
712 | ld b32 $r5 D[$r0 + ctx_query_address_low] | 714 | ld b32 $r5 D[$r0 + #ctx_query_address_low] |
713 | add b32 $r5 4 | 715 | add b32 $r5 4 |
714 | iowr I[$r4 + 0x000] $r5 | 716 | iowr I[$r4 + 0x000] $r5 |
715 | iowr I[$r4 + 0x100] $r0 | 717 | iowr I[$r4 + 0x100] $r0 |
716 | mov $r5 0xc | 718 | mov $r5 0xc |
717 | iowr I[$r4 + 0x200] $r5 | 719 | iowr I[$r4 + 0x200] $r5 |
718 | add b32 $r4 0x400 | 720 | add b32 $r4 0x400 |
719 | ld b32 $r5 D[$r0 + ctx_query_address_high] | 721 | ld b32 $r5 D[$r0 + #ctx_query_address_high] |
720 | shl b32 $r5 16 | 722 | shl b32 $r5 16 |
721 | iowr I[$r4 + 0x000] $r5 | 723 | iowr I[$r4 + 0x000] $r5 |
722 | add b32 $r4 0x500 | 724 | add b32 $r4 0x500 |
@@ -741,16 +743,16 @@ cmd_exec_query: | |||
741 | 743 | ||
742 | // write COUNTER | 744 | // write COUNTER |
743 | query_counter: | 745 | query_counter: |
744 | call cmd_exec_wait | 746 | call #cmd_exec_wait |
745 | mov $r4 0x80c | 747 | mov $r4 0x80c |
746 | shl b32 $r4 6 | 748 | shl b32 $r4 6 |
747 | ld b32 $r5 D[$r0 + ctx_query_address_low] | 749 | ld b32 $r5 D[$r0 + #ctx_query_address_low] |
748 | iowr I[$r4 + 0x000] $r5 | 750 | iowr I[$r4 + 0x000] $r5 |
749 | iowr I[$r4 + 0x100] $r0 | 751 | iowr I[$r4 + 0x100] $r0 |
750 | mov $r5 0x4 | 752 | mov $r5 0x4 |
751 | iowr I[$r4 + 0x200] $r5 | 753 | iowr I[$r4 + 0x200] $r5 |
752 | add b32 $r4 0x400 | 754 | add b32 $r4 0x400 |
753 | ld b32 $r5 D[$r0 + ctx_query_address_high] | 755 | ld b32 $r5 D[$r0 + #ctx_query_address_high] |
754 | shl b32 $r5 16 | 756 | shl b32 $r5 16 |
755 | iowr I[$r4 + 0x000] $r5 | 757 | iowr I[$r4 + 0x000] $r5 |
756 | add b32 $r4 0x500 | 758 | add b32 $r4 0x500 |
@@ -759,7 +761,7 @@ cmd_exec_query: | |||
759 | mov $r5 0x00001110 | 761 | mov $r5 0x00001110 |
760 | sethi $r5 0x13120000 | 762 | sethi $r5 0x13120000 |
761 | iowr I[$r4 + 0x100] $r5 | 763 | iowr I[$r4 + 0x100] $r5 |
762 | ld b32 $r5 D[$r0 + ctx_query_counter] | 764 | ld b32 $r5 D[$r0 + #ctx_query_counter] |
763 | add b32 $r4 0x500 | 765 | add b32 $r4 0x500 |
764 | iowr I[$r4 + 0x000] $r5 | 766 | iowr I[$r4 + 0x000] $r5 |
765 | mov $r5 0x00002601 | 767 | mov $r5 0x00002601 |
@@ -787,22 +789,22 @@ cmd_exec_query: | |||
787 | // $r2: hostirq state | 789 | // $r2: hostirq state |
788 | // $r3: data | 790 | // $r3: data |
789 | cmd_exec: | 791 | cmd_exec: |
790 | call cmd_exec_wait | 792 | call #cmd_exec_wait |
791 | 793 | ||
792 | // if format requested, call function to calculate it, otherwise | 794 | // if format requested, call function to calculate it, otherwise |
793 | // fill in cpp/xcnt for both surfaces as if (cpp == 1) | 795 | // fill in cpp/xcnt for both surfaces as if (cpp == 1) |
794 | xbit $r15 $r3 0 | 796 | xbit $r15 $r3 0 |
795 | bra e cmd_exec_no_format | 797 | bra e #cmd_exec_no_format |
796 | call cmd_exec_set_format | 798 | call #cmd_exec_set_format |
797 | mov $r4 0x200 | 799 | mov $r4 0x200 |
798 | bra cmd_exec_init_src_surface | 800 | bra #cmd_exec_init_src_surface |
799 | cmd_exec_no_format: | 801 | cmd_exec_no_format: |
800 | mov $r6 0x810 | 802 | mov $r6 0x810 |
801 | shl b32 $r6 6 | 803 | shl b32 $r6 6 |
802 | mov $r7 1 | 804 | mov $r7 1 |
803 | st b32 D[$r0 + ctx_src_cpp] $r7 | 805 | st b32 D[$r0 + #ctx_src_cpp] $r7 |
804 | st b32 D[$r0 + ctx_dst_cpp] $r7 | 806 | st b32 D[$r0 + #ctx_dst_cpp] $r7 |
805 | ld b32 $r7 D[$r0 + ctx_xcnt] | 807 | ld b32 $r7 D[$r0 + #ctx_xcnt] |
806 | iowr I[$r6 + 0x000] $r7 | 808 | iowr I[$r6 + 0x000] $r7 |
807 | iowr I[$r6 + 0x100] $r7 | 809 | iowr I[$r6 + 0x100] $r7 |
808 | clear b32 $r4 | 810 | clear b32 $r4 |
@@ -811,28 +813,28 @@ cmd_exec: | |||
811 | bclr $flags $p2 | 813 | bclr $flags $p2 |
812 | clear b32 $r5 | 814 | clear b32 $r5 |
813 | xbit $r15 $r3 4 | 815 | xbit $r15 $r3 4 |
814 | bra e src_tiled | 816 | bra e #src_tiled |
815 | call cmd_exec_set_surface_linear | 817 | call #cmd_exec_set_surface_linear |
816 | bra cmd_exec_init_dst_surface | 818 | bra #cmd_exec_init_dst_surface |
817 | src_tiled: | 819 | src_tiled: |
818 | call cmd_exec_set_surface_tiled | 820 | call #cmd_exec_set_surface_tiled |
819 | bset $r4 7 | 821 | bset $r4 7 |
820 | 822 | ||
821 | cmd_exec_init_dst_surface: | 823 | cmd_exec_init_dst_surface: |
822 | bset $flags $p2 | 824 | bset $flags $p2 |
823 | mov $r5 ctx_dst_address_high - ctx_src_address_high | 825 | mov $r5 #ctx_dst_address_high - #ctx_src_address_high |
824 | xbit $r15 $r3 8 | 826 | xbit $r15 $r3 8 |
825 | bra e dst_tiled | 827 | bra e #dst_tiled |
826 | call cmd_exec_set_surface_linear | 828 | call #cmd_exec_set_surface_linear |
827 | bra cmd_exec_kick | 829 | bra #cmd_exec_kick |
828 | dst_tiled: | 830 | dst_tiled: |
829 | call cmd_exec_set_surface_tiled | 831 | call #cmd_exec_set_surface_tiled |
830 | bset $r4 8 | 832 | bset $r4 8 |
831 | 833 | ||
832 | cmd_exec_kick: | 834 | cmd_exec_kick: |
833 | mov $r5 0x800 | 835 | mov $r5 0x800 |
834 | shl b32 $r5 6 | 836 | shl b32 $r5 6 |
835 | ld b32 $r6 D[$r0 + ctx_ycnt] | 837 | ld b32 $r6 D[$r0 + #ctx_ycnt] |
836 | iowr I[$r5 + 0x100] $r6 | 838 | iowr I[$r5 + 0x100] $r6 |
837 | mov $r6 0x0041 | 839 | mov $r6 0x0041 |
838 | // SRC_TARGET = 1, DST_TARGET = 2 | 840 | // SRC_TARGET = 1, DST_TARGET = 2 |
@@ -842,8 +844,8 @@ cmd_exec: | |||
842 | 844 | ||
843 | // if requested, queue up a QUERY write after the copy has completed | 845 | // if requested, queue up a QUERY write after the copy has completed |
844 | xbit $r15 $r3 12 | 846 | xbit $r15 $r3 12 |
845 | bra e cmd_exec_done | 847 | bra e #cmd_exec_done |
846 | call cmd_exec_query | 848 | call #cmd_exec_query |
847 | 849 | ||
848 | cmd_exec_done: | 850 | cmd_exec_done: |
849 | ret | 851 | ret |