diff options
author | Ben Skeggs <bskeggs@redhat.com> | 2010-09-01 01:24:31 -0400 |
---|---|---|
committer | Ben Skeggs <bskeggs@redhat.com> | 2010-09-24 02:20:14 -0400 |
commit | a8eaebc6c52bb0cd243b4cb421068f42d378be9c (patch) | |
tree | 12f796e5210d51f78b9fc6ddd4750cf1421373c2 /drivers/gpu/drm/nouveau/nv50_graph.c | |
parent | de3a6c0a3b642c0c350414d63298a1b19a009290 (diff) |
drm/nouveau: remove nouveau_gpuobj_ref completely, replace with sanity
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau/nv50_graph.c')
-rw-r--r-- | drivers/gpu/drm/nouveau/nv50_graph.c | 39 |
1 files changed, 19 insertions, 20 deletions
diff --git a/drivers/gpu/drm/nouveau/nv50_graph.c b/drivers/gpu/drm/nouveau/nv50_graph.c index 17a8d788a494..7db0d627c1b9 100644 --- a/drivers/gpu/drm/nouveau/nv50_graph.c +++ b/drivers/gpu/drm/nouveau/nv50_graph.c | |||
@@ -27,7 +27,7 @@ | |||
27 | #include "drmP.h" | 27 | #include "drmP.h" |
28 | #include "drm.h" | 28 | #include "drm.h" |
29 | #include "nouveau_drv.h" | 29 | #include "nouveau_drv.h" |
30 | 30 | #include "nouveau_ramht.h" | |
31 | #include "nouveau_grctx.h" | 31 | #include "nouveau_grctx.h" |
32 | 32 | ||
33 | static void | 33 | static void |
@@ -192,7 +192,7 @@ nv50_graph_channel(struct drm_device *dev) | |||
192 | for (i = 0; i < dev_priv->engine.fifo.channels; i++) { | 192 | for (i = 0; i < dev_priv->engine.fifo.channels; i++) { |
193 | struct nouveau_channel *chan = dev_priv->fifos[i]; | 193 | struct nouveau_channel *chan = dev_priv->fifos[i]; |
194 | 194 | ||
195 | if (chan && chan->ramin && chan->ramin->instance == inst) | 195 | if (chan && chan->ramin && chan->ramin->vinst == inst) |
196 | return chan; | 196 | return chan; |
197 | } | 197 | } |
198 | 198 | ||
@@ -204,36 +204,34 @@ nv50_graph_create_context(struct nouveau_channel *chan) | |||
204 | { | 204 | { |
205 | struct drm_device *dev = chan->dev; | 205 | struct drm_device *dev = chan->dev; |
206 | struct drm_nouveau_private *dev_priv = dev->dev_private; | 206 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
207 | struct nouveau_gpuobj *ramin = chan->ramin->gpuobj; | 207 | struct nouveau_gpuobj *ramin = chan->ramin; |
208 | struct nouveau_gpuobj *obj; | ||
209 | struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph; | 208 | struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph; |
210 | struct nouveau_grctx ctx = {}; | 209 | struct nouveau_grctx ctx = {}; |
211 | int hdr, ret; | 210 | int hdr, ret; |
212 | 211 | ||
213 | NV_DEBUG(dev, "ch%d\n", chan->id); | 212 | NV_DEBUG(dev, "ch%d\n", chan->id); |
214 | 213 | ||
215 | ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, pgraph->grctx_size, | 214 | ret = nouveau_gpuobj_new(dev, chan, pgraph->grctx_size, 0x1000, |
216 | 0x1000, NVOBJ_FLAG_ZERO_ALLOC | | 215 | NVOBJ_FLAG_ZERO_ALLOC | |
217 | NVOBJ_FLAG_ZERO_FREE, &chan->ramin_grctx); | 216 | NVOBJ_FLAG_ZERO_FREE, &chan->ramin_grctx); |
218 | if (ret) | 217 | if (ret) |
219 | return ret; | 218 | return ret; |
220 | obj = chan->ramin_grctx->gpuobj; | ||
221 | 219 | ||
222 | hdr = (dev_priv->chipset == 0x50) ? 0x200 : 0x20; | 220 | hdr = (dev_priv->chipset == 0x50) ? 0x200 : 0x20; |
223 | nv_wo32(ramin, hdr + 0x00, 0x00190002); | 221 | nv_wo32(ramin, hdr + 0x00, 0x00190002); |
224 | nv_wo32(ramin, hdr + 0x04, chan->ramin_grctx->instance + | 222 | nv_wo32(ramin, hdr + 0x04, chan->ramin_grctx->vinst + |
225 | pgraph->grctx_size - 1); | 223 | pgraph->grctx_size - 1); |
226 | nv_wo32(ramin, hdr + 0x08, chan->ramin_grctx->instance); | 224 | nv_wo32(ramin, hdr + 0x08, chan->ramin_grctx->vinst); |
227 | nv_wo32(ramin, hdr + 0x0c, 0); | 225 | nv_wo32(ramin, hdr + 0x0c, 0); |
228 | nv_wo32(ramin, hdr + 0x10, 0); | 226 | nv_wo32(ramin, hdr + 0x10, 0); |
229 | nv_wo32(ramin, hdr + 0x14, 0x00010000); | 227 | nv_wo32(ramin, hdr + 0x14, 0x00010000); |
230 | 228 | ||
231 | ctx.dev = chan->dev; | 229 | ctx.dev = chan->dev; |
232 | ctx.mode = NOUVEAU_GRCTX_VALS; | 230 | ctx.mode = NOUVEAU_GRCTX_VALS; |
233 | ctx.data = obj; | 231 | ctx.data = chan->ramin_grctx; |
234 | nv50_grctx_init(&ctx); | 232 | nv50_grctx_init(&ctx); |
235 | 233 | ||
236 | nv_wo32(obj, 0x00000, chan->ramin->instance >> 12); | 234 | nv_wo32(chan->ramin_grctx, 0x00000, chan->ramin->vinst >> 12); |
237 | 235 | ||
238 | dev_priv->engine.instmem.flush(dev); | 236 | dev_priv->engine.instmem.flush(dev); |
239 | return 0; | 237 | return 0; |
@@ -248,14 +246,14 @@ nv50_graph_destroy_context(struct nouveau_channel *chan) | |||
248 | 246 | ||
249 | NV_DEBUG(dev, "ch%d\n", chan->id); | 247 | NV_DEBUG(dev, "ch%d\n", chan->id); |
250 | 248 | ||
251 | if (!chan->ramin || !chan->ramin->gpuobj) | 249 | if (!chan->ramin) |
252 | return; | 250 | return; |
253 | 251 | ||
254 | for (i = hdr; i < hdr + 24; i += 4) | 252 | for (i = hdr; i < hdr + 24; i += 4) |
255 | nv_wo32(chan->ramin->gpuobj, i, 0); | 253 | nv_wo32(chan->ramin, i, 0); |
256 | dev_priv->engine.instmem.flush(dev); | 254 | dev_priv->engine.instmem.flush(dev); |
257 | 255 | ||
258 | nouveau_gpuobj_ref_del(dev, &chan->ramin_grctx); | 256 | nouveau_gpuobj_ref(NULL, &chan->ramin_grctx); |
259 | } | 257 | } |
260 | 258 | ||
261 | static int | 259 | static int |
@@ -282,7 +280,7 @@ nv50_graph_do_load_context(struct drm_device *dev, uint32_t inst) | |||
282 | int | 280 | int |
283 | nv50_graph_load_context(struct nouveau_channel *chan) | 281 | nv50_graph_load_context(struct nouveau_channel *chan) |
284 | { | 282 | { |
285 | uint32_t inst = chan->ramin->instance >> 12; | 283 | uint32_t inst = chan->ramin->vinst >> 12; |
286 | 284 | ||
287 | NV_DEBUG(chan->dev, "ch%d\n", chan->id); | 285 | NV_DEBUG(chan->dev, "ch%d\n", chan->id); |
288 | return nv50_graph_do_load_context(chan->dev, inst); | 286 | return nv50_graph_do_load_context(chan->dev, inst); |
@@ -327,15 +325,16 @@ static int | |||
327 | nv50_graph_nvsw_dma_vblsem(struct nouveau_channel *chan, int grclass, | 325 | nv50_graph_nvsw_dma_vblsem(struct nouveau_channel *chan, int grclass, |
328 | int mthd, uint32_t data) | 326 | int mthd, uint32_t data) |
329 | { | 327 | { |
330 | struct nouveau_gpuobj_ref *ref = NULL; | 328 | struct nouveau_gpuobj *gpuobj; |
331 | 329 | ||
332 | if (nouveau_gpuobj_ref_find(chan, data, &ref)) | 330 | gpuobj = nouveau_ramht_find(chan, data); |
331 | if (!gpuobj) | ||
333 | return -ENOENT; | 332 | return -ENOENT; |
334 | 333 | ||
335 | if (nouveau_notifier_offset(ref->gpuobj, NULL)) | 334 | if (nouveau_notifier_offset(gpuobj, NULL)) |
336 | return -EINVAL; | 335 | return -EINVAL; |
337 | 336 | ||
338 | chan->nvsw.vblsem = ref->gpuobj; | 337 | chan->nvsw.vblsem = gpuobj; |
339 | chan->nvsw.vblsem_offset = ~0; | 338 | chan->nvsw.vblsem_offset = ~0; |
340 | return 0; | 339 | return 0; |
341 | } | 340 | } |