drm/nouveau/fifo: turn all fifo modules into engine modules

Been tested on each major revision that's relevant here, but I'm sure there are still bugs waiting to be ironed out. This is a *very* invasive change. There's a couple of pieces left that I don't like much (eg. other engines using fifo_priv for the channel count), but that's an artefact of there being a master channel list still. This is changing, slowly. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
author: Ben Skeggs <bskeggs@redhat.com> 2012-05-01 06:48:08 -0400
committer: Ben Skeggs <bskeggs@redhat.com> 2012-05-24 02:56:11 -0400
commit: c420b2dc8dc3cdd507214f4df5c5f96f08812cbe (patch)
tree: 6dca9f0aba3de22a2bda5fe647d6945d4f4e986e /drivers/gpu/drm/nouveau/nv40_fifo.c
parent: a226c32a386bca0426e500954b79e3fd46afc0d9 (diff)
1 files changed, 127 insertions, 225 deletions
diff --git a/drivers/gpu/drm/nouveau/nv40_fifo.c b/drivers/gpu/drm/nouveau/nv40_fifo.c
index 8d346617f55f..cdc818479b0a 100644
--- a/drivers/gpu/drm/nouveau/nv40_fifo.c
+++ b/drivers/gpu/drm/nouveau/nv40_fifo.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2007 Ben Skeggs.
+ * Copyright (C) 2012 Ben Skeggs.
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining
@@ -25,215 +25,123 @@
 */
 #include "drmP.h"
+#include "drm.h"
 #include "nouveau_drv.h"
-#include "nouveau_drm.h"
+#include "nouveau_fifo.h"
+#include "nouveau_util.h"
 #include "nouveau_ramht.h"
-#define NV40_RAMFC(c) (dev_priv->ramfc->pinst + ((c) * NV40_RAMFC__SIZE))
+static struct ramfc_desc {
-#define NV40_RAMFC__SIZE 128
+        unsigned bits:6;
+        unsigned ctxs:5;
-int
+        unsigned ctxp:8;
-nv40_fifo_create_context(struct nouveau_channel *chan)
+        unsigned regs:5;
+        unsigned regp;
+} nv40_ramfc[] = {
+        { 32,  0, 0x00,  0, NV04_PFIFO_CACHE1_DMA_PUT },
+        { 32,  0, 0x04,  0, NV04_PFIFO_CACHE1_DMA_GET },
+        { 32,  0, 0x08,  0, NV10_PFIFO_CACHE1_REF_CNT },
+        { 32,  0, 0x0c,  0, NV04_PFIFO_CACHE1_DMA_INSTANCE },
+        { 32,  0, 0x10,  0, NV04_PFIFO_CACHE1_DMA_DCOUNT },
+        { 32,  0, 0x14,  0, NV04_PFIFO_CACHE1_DMA_STATE },
+        { 28,  0, 0x18,  0, NV04_PFIFO_CACHE1_DMA_FETCH },
+        {  2, 28, 0x18, 28, 0x002058 },
+        { 32,  0, 0x1c,  0, NV04_PFIFO_CACHE1_ENGINE },
+        { 32,  0, 0x20,  0, NV04_PFIFO_CACHE1_PULL1 },
+        { 32,  0, 0x24,  0, NV10_PFIFO_CACHE1_ACQUIRE_VALUE },
+        { 32,  0, 0x28,  0, NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP },
+        { 32,  0, 0x2c,  0, NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT },
+        { 32,  0, 0x30,  0, NV10_PFIFO_CACHE1_SEMAPHORE },
+        { 32,  0, 0x34,  0, NV10_PFIFO_CACHE1_DMA_SUBROUTINE },
+        { 32,  0, 0x38,  0, NV40_PFIFO_GRCTX_INSTANCE },
+        { 17,  0, 0x3c,  0, NV04_PFIFO_DMA_TIMESLICE },
+        { 32,  0, 0x40,  0, 0x0032e4 },
+        { 32,  0, 0x44,  0, 0x0032e8 },
+        { 32,  0, 0x4c,  0, 0x002088 },
+        { 32,  0, 0x50,  0, 0x003300 },
+        { 32,  0, 0x54,  0, 0x00330c },
+        {}
+};
+struct nv40_fifo_priv {
+        struct nouveau_fifo_priv base;
+        struct ramfc_desc *ramfc_desc;
+};
+struct nv40_fifo_chan {
+        struct nouveau_fifo_chan base;
+        struct nouveau_gpuobj *ramfc;
+};
+static int
+nv40_fifo_context_new(struct nouveau_channel *chan, int engine)
 {
        struct drm_device *dev = chan->dev;
        struct drm_nouveau_private *dev_priv = dev->dev_private;
-        uint32_t fc = NV40_RAMFC(chan->id);
+        struct nv40_fifo_priv *priv = nv_engine(dev, engine);
+        struct nv40_fifo_chan *fctx;
        unsigned long flags;
        int ret;
-        ret = nouveau_gpuobj_new_fake(dev, NV40_RAMFC(chan->id), ~0,
+        fctx = chan->engctx[engine] = kzalloc(sizeof(*fctx), GFP_KERNEL);
-                                      NV40_RAMFC__SIZE, NVOBJ_FLAG_ZERO_ALLOC |
+        if (!fctx)
-                                      NVOBJ_FLAG_ZERO_FREE, &chan->ramfc);
-        if (ret)
-                return ret;
-        chan->user = ioremap(pci_resource_start(dev->pdev, 0) +
-                             NV40_USER(chan->id), PAGE_SIZE);
-        if (!chan->user)
                return -ENOMEM;
-        spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
+        /* map channel control registers */
+        chan->user = ioremap(pci_resource_start(dev->pdev, 0) +
+                             NV03_USER(chan->id), PAGE_SIZE);
+        if (!chan->user) {
+                ret = -ENOMEM;
+                goto error;
+        }
-        nv_wi32(dev, fc +  0, chan->pushbuf_base);
+        /* initialise default fifo context */
-        nv_wi32(dev, fc +  4, chan->pushbuf_base);
+        ret = nouveau_gpuobj_new_fake(dev, dev_priv->ramfc->pinst +
-        nv_wi32(dev, fc + 12, chan->pushbuf->pinst >> 4);
+                                      chan->id * 128, ~0, 128,
-        nv_wi32(dev, fc + 24, NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES |
+                                      NVOBJ_FLAG_ZERO_ALLOC |
-                              NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES |
+                                      NVOBJ_FLAG_ZERO_FREE, &fctx->ramfc);
-                              NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8 |
+        if (ret)
+                goto error;
+        nv_wo32(fctx->ramfc, 0x00, chan->pushbuf_base);
+        nv_wo32(fctx->ramfc, 0x04, chan->pushbuf_base);
+        nv_wo32(fctx->ramfc, 0x0c, chan->pushbuf->pinst >> 4);
+        nv_wo32(fctx->ramfc, 0x18, 0x30000000 |
+                                   NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES |
+                                   NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES |
 #ifdef __BIG_ENDIAN
-                              NV_PFIFO_CACHE1_BIG_ENDIAN |
+                                   NV_PFIFO_CACHE1_BIG_ENDIAN |
 #endif
-                              0x30000000 /* no idea.. */);
+                                   NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8);
-        nv_wi32(dev, fc + 60, 0x0001FFFF);
+        nv_wo32(fctx->ramfc, 0x3c, 0x0001ffff);
-        /* enable the fifo dma operation */
-        nv_wr32(dev, NV04_PFIFO_MODE,
-                nv_rd32(dev, NV04_PFIFO_MODE) | (1 << chan->id));
+        /* enable dma mode on the channel */
+        spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
+        nv_mask(dev, NV04_PFIFO_MODE, (1 << chan->id), (1 << chan->id));
        spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
-        return 0;
-}
-static void
-nv40_fifo_do_load_context(struct drm_device *dev, int chid)
-{
-        struct drm_nouveau_private *dev_priv = dev->dev_private;
-        uint32_t fc = NV40_RAMFC(chid), tmp, tmp2;
-        nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_PUT, nv_ri32(dev, fc + 0));
-        nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_GET, nv_ri32(dev, fc + 4));
-        nv_wr32(dev, NV10_PFIFO_CACHE1_REF_CNT, nv_ri32(dev, fc + 8));
-        nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_INSTANCE, nv_ri32(dev, fc + 12));
-        nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_DCOUNT, nv_ri32(dev, fc + 16));
-        nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_STATE, nv_ri32(dev, fc + 20));
-        /* No idea what 0x2058 is.. */
-        tmp   = nv_ri32(dev, fc + 24);
-        tmp2  = nv_rd32(dev, 0x2058) & 0xFFF;
-        tmp2 |= (tmp & 0x30000000);
-        nv_wr32(dev, 0x2058, tmp2);
-        tmp  &= ~0x30000000;
-        nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_FETCH, tmp);
-        nv_wr32(dev, NV04_PFIFO_CACHE1_ENGINE, nv_ri32(dev, fc + 28));
-        nv_wr32(dev, NV04_PFIFO_CACHE1_PULL1, nv_ri32(dev, fc + 32));
-        nv_wr32(dev, NV10_PFIFO_CACHE1_ACQUIRE_VALUE, nv_ri32(dev, fc + 36));
-        tmp = nv_ri32(dev, fc + 40);
-        nv_wr32(dev, NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP, tmp);
-        nv_wr32(dev, NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT, nv_ri32(dev, fc + 44));
-        nv_wr32(dev, NV10_PFIFO_CACHE1_SEMAPHORE, nv_ri32(dev, fc + 48));
-        nv_wr32(dev, NV10_PFIFO_CACHE1_DMA_SUBROUTINE, nv_ri32(dev, fc + 52));
-        nv_wr32(dev, NV40_PFIFO_GRCTX_INSTANCE, nv_ri32(dev, fc + 56));
-        /* Don't clobber the TIMEOUT_ENABLED flag when restoring from RAMFC */
-        tmp  = nv_rd32(dev, NV04_PFIFO_DMA_TIMESLICE) & ~0x1FFFF;
-        tmp |= nv_ri32(dev, fc + 60) & 0x1FFFF;
-        nv_wr32(dev, NV04_PFIFO_DMA_TIMESLICE, tmp);
-        nv_wr32(dev, 0x32e4, nv_ri32(dev, fc + 64));
+        /*XXX: remove this later, need fifo engine context commit hook */
-        /* NVIDIA does this next line twice... */
+        nouveau_gpuobj_ref(fctx->ramfc, &chan->ramfc);
-        nv_wr32(dev, 0x32e8, nv_ri32(dev, fc + 68));
-        nv_wr32(dev, 0x2088, nv_ri32(dev, fc + 76));
-        nv_wr32(dev, 0x3300, nv_ri32(dev, fc + 80));
-        nv_wr32(dev, 0x330c, nv_ri32(dev, fc + 84));
-        nv_wr32(dev, NV03_PFIFO_CACHE1_GET, 0);
+error:
-        nv_wr32(dev, NV03_PFIFO_CACHE1_PUT, 0);
+        if (ret)
-}
+                priv->base.base.context_del(chan, engine);
+        return ret;
-int
-nv40_fifo_load_context(struct nouveau_channel *chan)
-{
-        struct drm_device *dev = chan->dev;
-        uint32_t tmp;
-        nv40_fifo_do_load_context(dev, chan->id);
-        /* Set channel active, and in DMA mode */
-        nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1,
-                     NV40_PFIFO_CACHE1_PUSH1_DMA | chan->id);
-        nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_PUSH, 1);
-        /* Reset DMA_CTL_AT_INFO to INVALID */
-        tmp = nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_CTL) & ~(1 << 31);
-        nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_CTL, tmp);
-        return 0;
 }
-int
+static int
-nv40_fifo_unload_context(struct drm_device *dev)
+nv40_fifo_init(struct drm_device *dev, int engine)
 {
        struct drm_nouveau_private *dev_priv = dev->dev_private;
-        struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
+        struct nv40_fifo_priv *priv = nv_engine(dev, engine);
-        uint32_t fc, tmp;
-        int chid;
-        chid = nv_rd32(dev, NV03_PFIFO_CACHE1_PUSH1) & 0x1f;
-        if (chid < 0 || chid >= dev_priv->engine.fifo.channels)
-                return 0;
-        fc = NV40_RAMFC(chid);
-        nv_wi32(dev, fc + 0, nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_PUT));
-        nv_wi32(dev, fc + 4, nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_GET));
-        nv_wi32(dev, fc + 8, nv_rd32(dev, NV10_PFIFO_CACHE1_REF_CNT));
-        nv_wi32(dev, fc + 12, nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_INSTANCE));
-        nv_wi32(dev, fc + 16, nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_DCOUNT));
-        nv_wi32(dev, fc + 20, nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_STATE));
-        tmp  = nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_FETCH);
-        tmp |= nv_rd32(dev, 0x2058) & 0x30000000;
-        nv_wi32(dev, fc + 24, tmp);
-        nv_wi32(dev, fc + 28, nv_rd32(dev, NV04_PFIFO_CACHE1_ENGINE));
-        nv_wi32(dev, fc + 32, nv_rd32(dev, NV04_PFIFO_CACHE1_PULL1));
-        nv_wi32(dev, fc + 36, nv_rd32(dev, NV10_PFIFO_CACHE1_ACQUIRE_VALUE));
-        tmp = nv_rd32(dev, NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP);
-        nv_wi32(dev, fc + 40, tmp);
-        nv_wi32(dev, fc + 44, nv_rd32(dev, NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT));
-        nv_wi32(dev, fc + 48, nv_rd32(dev, NV10_PFIFO_CACHE1_SEMAPHORE));
-        /* NVIDIA read 0x3228 first, then write DMA_GET here.. maybe something
-         * more involved depending on the value of 0x3228?
-         */
-        nv_wi32(dev, fc + 52, nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_GET));
-        nv_wi32(dev, fc + 56, nv_rd32(dev, NV40_PFIFO_GRCTX_INSTANCE));
-        nv_wi32(dev, fc + 60, nv_rd32(dev, NV04_PFIFO_DMA_TIMESLICE) & 0x1ffff);
-        /* No idea what the below is for exactly, ripped from a mmio-trace */
-        nv_wi32(dev, fc + 64, nv_rd32(dev, NV40_PFIFO_UNK32E4));
-        /* NVIDIA do this next line twice.. bug? */
-        nv_wi32(dev, fc + 68, nv_rd32(dev, 0x32e8));
-        nv_wi32(dev, fc + 76, nv_rd32(dev, 0x2088));
-        nv_wi32(dev, fc + 80, nv_rd32(dev, 0x3300));
-#if 0 /* no real idea which is PUT/GET in UNK_48.. */
-        tmp  = nv_rd32(dev, NV04_PFIFO_CACHE1_GET);
-        tmp |= (nv_rd32(dev, NV04_PFIFO_CACHE1_PUT) << 16);
-        nv_wi32(dev, fc + 72, tmp);
-#endif
-        nv_wi32(dev, fc + 84, nv_rd32(dev, 0x330c));
-        nv40_fifo_do_load_context(dev, pfifo->channels - 1);
-        nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1,
-                     NV40_PFIFO_CACHE1_PUSH1_DMA | (pfifo->channels - 1));
-        return 0;
-}
-static void
-nv40_fifo_init_reset(struct drm_device *dev)
-{
        int i;
-        nv_wr32(dev, NV03_PMC_ENABLE,
+        nv_mask(dev, NV03_PMC_ENABLE, NV_PMC_ENABLE_PFIFO, 0);
-                nv_rd32(dev, NV03_PMC_ENABLE) & ~NV_PMC_ENABLE_PFIFO);
+        nv_mask(dev, NV03_PMC_ENABLE, NV_PMC_ENABLE_PFIFO, NV_PMC_ENABLE_PFIFO);
-        nv_wr32(dev, NV03_PMC_ENABLE,
-                nv_rd32(dev, NV03_PMC_ENABLE) |  NV_PMC_ENABLE_PFIFO);
-        nv_wr32(dev, 0x003224, 0x000f0078);
-        nv_wr32(dev, 0x003210, 0x00000000);
-        nv_wr32(dev, 0x003270, 0x00000000);
-        nv_wr32(dev, 0x003240, 0x00000000);
-        nv_wr32(dev, 0x003244, 0x00000000);
-        nv_wr32(dev, 0x003258, 0x00000000);
-        nv_wr32(dev, 0x002504, 0x00000000);
-        for (i = 0; i < 16; i++)
-                nv_wr32(dev, 0x002510 + (i * 4), 0x00000000);
-        nv_wr32(dev, 0x00250c, 0x0000ffff);
-        nv_wr32(dev, 0x002048, 0x00000000);
-        nv_wr32(dev, 0x003228, 0x00000000);
-        nv_wr32(dev, 0x0032e8, 0x00000000);
-        nv_wr32(dev, 0x002410, 0x00000000);
-        nv_wr32(dev, 0x002420, 0x00000000);
-        nv_wr32(dev, 0x002058, 0x00000001);
-        nv_wr32(dev, 0x00221c, 0x00000000);
-        /* something with 0x2084, read/modify/write, no change */
        nv_wr32(dev, 0x002040, 0x000000ff);
-        nv_wr32(dev, 0x002500, 0x00000000);
+        nv_wr32(dev, 0x002044, 0x2101ffff);
-        nv_wr32(dev, 0x003200, 0x00000000);
+        nv_wr32(dev, 0x002058, 0x00000001);
-        nv_wr32(dev, NV04_PFIFO_DMA_TIMESLICE, 0x2101ffff);
-}
-static void
-nv40_fifo_init_ramxx(struct drm_device *dev)
-{
-        struct drm_nouveau_private *dev_priv = dev->dev_private;
        nv_wr32(dev, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ |
                                       ((dev_priv->ramht->bits - 9) << 16) |
@@ -244,65 +152,59 @@ nv40_fifo_init_ramxx(struct drm_device *dev)
        case 0x47:
        case 0x49:
        case 0x4b:
-                nv_wr32(dev, 0x2230, 1);
+                nv_wr32(dev, 0x002230, 0x00000001);
-                break;
-        default:
-                break;
-        }
-        switch (dev_priv->chipset) {
        case 0x40:
        case 0x41:
        case 0x42:
        case 0x43:
        case 0x45:
-        case 0x47:
        case 0x48:
-        case 0x49:
+                nv_wr32(dev, 0x002220, 0x00030002);
-        case 0x4b:
-                nv_wr32(dev, NV40_PFIFO_RAMFC, 0x30002);
                break;
        default:
-                nv_wr32(dev, 0x2230, 0);
+                nv_wr32(dev, 0x002230, 0x00000000);
-                nv_wr32(dev, NV40_PFIFO_RAMFC,
+                nv_wr32(dev, 0x002220, ((dev_priv->vram_size - 512 * 1024 +
-                        ((dev_priv->vram_size - 512 * 1024 +
+                                         dev_priv->ramfc->pinst) >> 16) |
-                          dev_priv->ramfc->pinst) >> 16) | (3 << 16));
+                                       0x00030000);
                break;
        }
-}
-static void
-nv40_fifo_init_intr(struct drm_device *dev)
-{
-        nouveau_irq_register(dev, 8, nv04_fifo_isr);
-        nv_wr32(dev, 0x002100, 0xffffffff);
-        nv_wr32(dev, 0x002140, 0xffffffff);
-}
-int
-nv40_fifo_init(struct drm_device *dev)
-{
-        struct drm_nouveau_private *dev_priv = dev->dev_private;
-        struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
-        int i;
-        nv40_fifo_init_reset(dev);
+        nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1, priv->base.channels);
-        nv40_fifo_init_ramxx(dev);
-        nv40_fifo_do_load_context(dev, pfifo->channels - 1);
+        nv_wr32(dev, NV03_PFIFO_INTR_0, 0xffffffff);
-        nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1, pfifo->channels - 1);
+        nv_wr32(dev, NV03_PFIFO_INTR_EN_0, 0xffffffff);
-        nv40_fifo_init_intr(dev);
        nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH0, 1);
        nv_wr32(dev, NV04_PFIFO_CACHE1_PULL0, 1);
        nv_wr32(dev, NV03_PFIFO_CACHES, 1);
-        for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
+        for (i = 0; i < priv->base.channels; i++) {
-                if (dev_priv->channels.ptr[i]) {
+                if (dev_priv->channels.ptr[i])
-                        uint32_t mode = nv_rd32(dev, NV04_PFIFO_MODE);
+                        nv_mask(dev, NV04_PFIFO_MODE, (1 << i), (1 << i));
-                        nv_wr32(dev, NV04_PFIFO_MODE, mode | (1 << i));
-                }
        }
        return 0;
 }
+int
+nv40_fifo_create(struct drm_device *dev)
+{
+        struct drm_nouveau_private *dev_priv = dev->dev_private;
+        struct nv40_fifo_priv *priv;
+        priv = kzalloc(sizeof(*priv), GFP_KERNEL);
+        if (!priv)
+                return -ENOMEM;
+        priv->base.base.destroy = nv04_fifo_destroy;
+        priv->base.base.init = nv40_fifo_init;
+        priv->base.base.fini = nv04_fifo_fini;
+        priv->base.base.context_new = nv40_fifo_context_new;
+        priv->base.base.context_del = nv04_fifo_context_del;
+        priv->base.channels = 31;
+        priv->ramfc_desc = nv40_ramfc;
+        dev_priv->eng[NVOBJ_ENGINE_FIFO] = &priv->base.base;
+        nouveau_irq_register(dev, 8, nv04_fifo_isr);
+        return 0;
+}
author	Ben Skeggs <bskeggs@redhat.com>	2012-05-01 06:48:08 -0400
committer	Ben Skeggs <bskeggs@redhat.com>	2012-05-24 02:56:11 -0400
commit	c420b2dc8dc3cdd507214f4df5c5f96f08812cbe (patch)
tree	6dca9f0aba3de22a2bda5fe647d6945d4f4e986e /drivers/gpu/drm/nouveau/nv40_fifo.c
parent	a226c32a386bca0426e500954b79e3fd46afc0d9 (diff)

diff --git a/drivers/gpu/drm/nouveau/nv40_fifo.c b/drivers/gpu/drm/nouveau/nv40_fifo.c index 8d346617f55f..cdc818479b0a 100644 --- a/drivers/gpu/drm/nouveau/nv40_fifo.c +++ b/drivers/gpu/drm/nouveau/nv40_fifo.c
@@ -1,5 +1,5 @@
1	/*	1	/*
2	* Copyright (C) 2007 Ben Skeggs.	2	* Copyright (C) 2012 Ben Skeggs.
3	* All Rights Reserved.	3	* All Rights Reserved.
4	*	4	*
5	* Permission is hereby granted, free of charge, to any person obtaining	5	* Permission is hereby granted, free of charge, to any person obtaining
@@ -25,215 +25,123 @@
25	*/	25	*/
26		26
27	#include "drmP.h"	27	#include "drmP.h"
		28	#include "drm.h"
28	#include "nouveau_drv.h"	29	#include "nouveau_drv.h"
29	#include "nouveau_drm.h"	30	#include "nouveau_fifo.h"
		31	#include "nouveau_util.h"
30	#include "nouveau_ramht.h"	32	#include "nouveau_ramht.h"
31		33
32	#define NV40_RAMFC(c) (dev_priv->ramfc->pinst + ((c) * NV40_RAMFC__SIZE))	34	static struct ramfc_desc {
33	#define NV40_RAMFC__SIZE 128	35	unsigned bits:6;
34		36	unsigned ctxs:5;
35	int	37	unsigned ctxp:8;
36	nv40_fifo_create_context(struct nouveau_channel *chan)	38	unsigned regs:5;
		39	unsigned regp;
		40	} nv40_ramfc[] = {
		41	{ 32, 0, 0x00, 0, NV04_PFIFO_CACHE1_DMA_PUT },
		42	{ 32, 0, 0x04, 0, NV04_PFIFO_CACHE1_DMA_GET },
		43	{ 32, 0, 0x08, 0, NV10_PFIFO_CACHE1_REF_CNT },
		44	{ 32, 0, 0x0c, 0, NV04_PFIFO_CACHE1_DMA_INSTANCE },
		45	{ 32, 0, 0x10, 0, NV04_PFIFO_CACHE1_DMA_DCOUNT },
		46	{ 32, 0, 0x14, 0, NV04_PFIFO_CACHE1_DMA_STATE },
		47	{ 28, 0, 0x18, 0, NV04_PFIFO_CACHE1_DMA_FETCH },
		48	{ 2, 28, 0x18, 28, 0x002058 },
		49	{ 32, 0, 0x1c, 0, NV04_PFIFO_CACHE1_ENGINE },
		50	{ 32, 0, 0x20, 0, NV04_PFIFO_CACHE1_PULL1 },
		51	{ 32, 0, 0x24, 0, NV10_PFIFO_CACHE1_ACQUIRE_VALUE },
		52	{ 32, 0, 0x28, 0, NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP },
		53	{ 32, 0, 0x2c, 0, NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT },
		54	{ 32, 0, 0x30, 0, NV10_PFIFO_CACHE1_SEMAPHORE },
		55	{ 32, 0, 0x34, 0, NV10_PFIFO_CACHE1_DMA_SUBROUTINE },
		56	{ 32, 0, 0x38, 0, NV40_PFIFO_GRCTX_INSTANCE },
		57	{ 17, 0, 0x3c, 0, NV04_PFIFO_DMA_TIMESLICE },
		58	{ 32, 0, 0x40, 0, 0x0032e4 },
		59	{ 32, 0, 0x44, 0, 0x0032e8 },
		60	{ 32, 0, 0x4c, 0, 0x002088 },
		61	{ 32, 0, 0x50, 0, 0x003300 },
		62	{ 32, 0, 0x54, 0, 0x00330c },
		63	{}
		64	};
		65
		66	struct nv40_fifo_priv {
		67	struct nouveau_fifo_priv base;
		68	struct ramfc_desc *ramfc_desc;
		69	};
		70
		71	struct nv40_fifo_chan {
		72	struct nouveau_fifo_chan base;
		73	struct nouveau_gpuobj *ramfc;
		74	};
		75
		76	static int
		77	nv40_fifo_context_new(struct nouveau_channel *chan, int engine)
37	{	78	{
38	struct drm_device *dev = chan->dev;	79	struct drm_device *dev = chan->dev;
39	struct drm_nouveau_private *dev_priv = dev->dev_private;	80	struct drm_nouveau_private *dev_priv = dev->dev_private;
40	uint32_t fc = NV40_RAMFC(chan->id);	81	struct nv40_fifo_priv *priv = nv_engine(dev, engine);
		82	struct nv40_fifo_chan *fctx;
41	unsigned long flags;	83	unsigned long flags;
42	int ret;	84	int ret;
43		85
44	ret = nouveau_gpuobj_new_fake(dev, NV40_RAMFC(chan->id), ~0,	86	fctx = chan->engctx[engine] = kzalloc(sizeof(*fctx), GFP_KERNEL);
45	NV40_RAMFC__SIZE, NVOBJ_FLAG_ZERO_ALLOC \|	87	if (!fctx)
46	NVOBJ_FLAG_ZERO_FREE, &chan->ramfc);
47	if (ret)
48	return ret;
49
50	chan->user = ioremap(pci_resource_start(dev->pdev, 0) +
51	NV40_USER(chan->id), PAGE_SIZE);
52	if (!chan->user)
53	return -ENOMEM;	88	return -ENOMEM;
54		89
55	spin_lock_irqsave(&dev_priv->context_switch_lock, flags);	90	/* map channel control registers */
		91	chan->user = ioremap(pci_resource_start(dev->pdev, 0) +
		92	NV03_USER(chan->id), PAGE_SIZE);
		93	if (!chan->user) {
		94	ret = -ENOMEM;
		95	goto error;
		96	}
56		97
57	nv_wi32(dev, fc + 0, chan->pushbuf_base);	98	/* initialise default fifo context */
58	nv_wi32(dev, fc + 4, chan->pushbuf_base);	99	ret = nouveau_gpuobj_new_fake(dev, dev_priv->ramfc->pinst +
59	nv_wi32(dev, fc + 12, chan->pushbuf->pinst >> 4);	100	chan->id * 128, ~0, 128,
60	nv_wi32(dev, fc + 24, NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES \|	101	NVOBJ_FLAG_ZERO_ALLOC \|
61	NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES \|	102	NVOBJ_FLAG_ZERO_FREE, &fctx->ramfc);
62	NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8 \|	103	if (ret)
		104	goto error;
		105
		106	nv_wo32(fctx->ramfc, 0x00, chan->pushbuf_base);
		107	nv_wo32(fctx->ramfc, 0x04, chan->pushbuf_base);
		108	nv_wo32(fctx->ramfc, 0x0c, chan->pushbuf->pinst >> 4);
		109	nv_wo32(fctx->ramfc, 0x18, 0x30000000 \|
		110	NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES \|
		111	NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES \|
63	#ifdef __BIG_ENDIAN	112	#ifdef __BIG_ENDIAN
64	NV_PFIFO_CACHE1_BIG_ENDIAN \|	113	NV_PFIFO_CACHE1_BIG_ENDIAN \|
65	#endif	114	#endif
66	0x30000000 /* no idea.. */);	115	NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8);
67	nv_wi32(dev, fc + 60, 0x0001FFFF);	116	nv_wo32(fctx->ramfc, 0x3c, 0x0001ffff);
68
69	/* enable the fifo dma operation */
70	nv_wr32(dev, NV04_PFIFO_MODE,
71	nv_rd32(dev, NV04_PFIFO_MODE) \| (1 << chan->id));
72		117
		118	/* enable dma mode on the channel */
		119	spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
		120	nv_mask(dev, NV04_PFIFO_MODE, (1 << chan->id), (1 << chan->id));
73	spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);	121	spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
74	return 0;
75	}
76
77	static void
78	nv40_fifo_do_load_context(struct drm_device *dev, int chid)
79	{
80	struct drm_nouveau_private *dev_priv = dev->dev_private;
81	uint32_t fc = NV40_RAMFC(chid), tmp, tmp2;
82
83	nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_PUT, nv_ri32(dev, fc + 0));
84	nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_GET, nv_ri32(dev, fc + 4));
85	nv_wr32(dev, NV10_PFIFO_CACHE1_REF_CNT, nv_ri32(dev, fc + 8));
86	nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_INSTANCE, nv_ri32(dev, fc + 12));
87	nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_DCOUNT, nv_ri32(dev, fc + 16));
88	nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_STATE, nv_ri32(dev, fc + 20));
89
90	/* No idea what 0x2058 is.. */
91	tmp = nv_ri32(dev, fc + 24);
92	tmp2 = nv_rd32(dev, 0x2058) & 0xFFF;
93	tmp2 \|= (tmp & 0x30000000);
94	nv_wr32(dev, 0x2058, tmp2);
95	tmp &= ~0x30000000;
96	nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_FETCH, tmp);
97
98	nv_wr32(dev, NV04_PFIFO_CACHE1_ENGINE, nv_ri32(dev, fc + 28));
99	nv_wr32(dev, NV04_PFIFO_CACHE1_PULL1, nv_ri32(dev, fc + 32));
100	nv_wr32(dev, NV10_PFIFO_CACHE1_ACQUIRE_VALUE, nv_ri32(dev, fc + 36));
101	tmp = nv_ri32(dev, fc + 40);
102	nv_wr32(dev, NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP, tmp);
103	nv_wr32(dev, NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT, nv_ri32(dev, fc + 44));
104	nv_wr32(dev, NV10_PFIFO_CACHE1_SEMAPHORE, nv_ri32(dev, fc + 48));
105	nv_wr32(dev, NV10_PFIFO_CACHE1_DMA_SUBROUTINE, nv_ri32(dev, fc + 52));
106	nv_wr32(dev, NV40_PFIFO_GRCTX_INSTANCE, nv_ri32(dev, fc + 56));
107
108	/* Don't clobber the TIMEOUT_ENABLED flag when restoring from RAMFC */
109	tmp = nv_rd32(dev, NV04_PFIFO_DMA_TIMESLICE) & ~0x1FFFF;
110	tmp \|= nv_ri32(dev, fc + 60) & 0x1FFFF;
111	nv_wr32(dev, NV04_PFIFO_DMA_TIMESLICE, tmp);
112		122
113	nv_wr32(dev, 0x32e4, nv_ri32(dev, fc + 64));	123	/XXX: remove this later, need fifo engine context commit hook /
114	/* NVIDIA does this next line twice... */	124	nouveau_gpuobj_ref(fctx->ramfc, &chan->ramfc);
115	nv_wr32(dev, 0x32e8, nv_ri32(dev, fc + 68));
116	nv_wr32(dev, 0x2088, nv_ri32(dev, fc + 76));
117	nv_wr32(dev, 0x3300, nv_ri32(dev, fc + 80));
118	nv_wr32(dev, 0x330c, nv_ri32(dev, fc + 84));
119		125
120	nv_wr32(dev, NV03_PFIFO_CACHE1_GET, 0);	126	error:
121	nv_wr32(dev, NV03_PFIFO_CACHE1_PUT, 0);	127	if (ret)
122	}	128	priv->base.base.context_del(chan, engine);
123		129	return ret;
124	int
125	nv40_fifo_load_context(struct nouveau_channel *chan)
126	{
127	struct drm_device *dev = chan->dev;
128	uint32_t tmp;
129
130	nv40_fifo_do_load_context(dev, chan->id);
131
132	/* Set channel active, and in DMA mode */
133	nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1,
134	NV40_PFIFO_CACHE1_PUSH1_DMA \| chan->id);
135	nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_PUSH, 1);
136
137	/* Reset DMA_CTL_AT_INFO to INVALID */
138	tmp = nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_CTL) & ~(1 << 31);
139	nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_CTL, tmp);
140
141	return 0;
142	}	130	}
143		131
144	int	132	static int
145	nv40_fifo_unload_context(struct drm_device *dev)	133	nv40_fifo_init(struct drm_device *dev, int engine)
146	{	134	{
147	struct drm_nouveau_private *dev_priv = dev->dev_private;	135	struct drm_nouveau_private *dev_priv = dev->dev_private;
148	struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;	136	struct nv40_fifo_priv *priv = nv_engine(dev, engine);
149	uint32_t fc, tmp;
150	int chid;
151
152	chid = nv_rd32(dev, NV03_PFIFO_CACHE1_PUSH1) & 0x1f;
153	if (chid < 0 \|\| chid >= dev_priv->engine.fifo.channels)
154	return 0;
155	fc = NV40_RAMFC(chid);
156
157	nv_wi32(dev, fc + 0, nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_PUT));
158	nv_wi32(dev, fc + 4, nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_GET));
159	nv_wi32(dev, fc + 8, nv_rd32(dev, NV10_PFIFO_CACHE1_REF_CNT));
160	nv_wi32(dev, fc + 12, nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_INSTANCE));
161	nv_wi32(dev, fc + 16, nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_DCOUNT));
162	nv_wi32(dev, fc + 20, nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_STATE));
163	tmp = nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_FETCH);
164	tmp \|= nv_rd32(dev, 0x2058) & 0x30000000;
165	nv_wi32(dev, fc + 24, tmp);
166	nv_wi32(dev, fc + 28, nv_rd32(dev, NV04_PFIFO_CACHE1_ENGINE));
167	nv_wi32(dev, fc + 32, nv_rd32(dev, NV04_PFIFO_CACHE1_PULL1));
168	nv_wi32(dev, fc + 36, nv_rd32(dev, NV10_PFIFO_CACHE1_ACQUIRE_VALUE));
169	tmp = nv_rd32(dev, NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP);
170	nv_wi32(dev, fc + 40, tmp);
171	nv_wi32(dev, fc + 44, nv_rd32(dev, NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT));
172	nv_wi32(dev, fc + 48, nv_rd32(dev, NV10_PFIFO_CACHE1_SEMAPHORE));
173	/* NVIDIA read 0x3228 first, then write DMA_GET here.. maybe something
174	* more involved depending on the value of 0x3228?
175	*/
176	nv_wi32(dev, fc + 52, nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_GET));
177	nv_wi32(dev, fc + 56, nv_rd32(dev, NV40_PFIFO_GRCTX_INSTANCE));
178	nv_wi32(dev, fc + 60, nv_rd32(dev, NV04_PFIFO_DMA_TIMESLICE) & 0x1ffff);
179	/* No idea what the below is for exactly, ripped from a mmio-trace */
180	nv_wi32(dev, fc + 64, nv_rd32(dev, NV40_PFIFO_UNK32E4));
181	/* NVIDIA do this next line twice.. bug? */
182	nv_wi32(dev, fc + 68, nv_rd32(dev, 0x32e8));
183	nv_wi32(dev, fc + 76, nv_rd32(dev, 0x2088));
184	nv_wi32(dev, fc + 80, nv_rd32(dev, 0x3300));
185	#if 0 /* no real idea which is PUT/GET in UNK_48.. */
186	tmp = nv_rd32(dev, NV04_PFIFO_CACHE1_GET);
187	tmp \|= (nv_rd32(dev, NV04_PFIFO_CACHE1_PUT) << 16);
188	nv_wi32(dev, fc + 72, tmp);
189	#endif
190	nv_wi32(dev, fc + 84, nv_rd32(dev, 0x330c));
191
192	nv40_fifo_do_load_context(dev, pfifo->channels - 1);
193	nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1,
194	NV40_PFIFO_CACHE1_PUSH1_DMA \| (pfifo->channels - 1));
195	return 0;
196	}
197
198	static void
199	nv40_fifo_init_reset(struct drm_device *dev)
200	{
201	int i;	137	int i;
202		138
203	nv_wr32(dev, NV03_PMC_ENABLE,	139	nv_mask(dev, NV03_PMC_ENABLE, NV_PMC_ENABLE_PFIFO, 0);
204	nv_rd32(dev, NV03_PMC_ENABLE) & ~NV_PMC_ENABLE_PFIFO);	140	nv_mask(dev, NV03_PMC_ENABLE, NV_PMC_ENABLE_PFIFO, NV_PMC_ENABLE_PFIFO);
205	nv_wr32(dev, NV03_PMC_ENABLE,
206	nv_rd32(dev, NV03_PMC_ENABLE) \| NV_PMC_ENABLE_PFIFO);
207		141
208	nv_wr32(dev, 0x003224, 0x000f0078);
209	nv_wr32(dev, 0x003210, 0x00000000);
210	nv_wr32(dev, 0x003270, 0x00000000);
211	nv_wr32(dev, 0x003240, 0x00000000);
212	nv_wr32(dev, 0x003244, 0x00000000);
213	nv_wr32(dev, 0x003258, 0x00000000);
214	nv_wr32(dev, 0x002504, 0x00000000);
215	for (i = 0; i < 16; i++)
216	nv_wr32(dev, 0x002510 + (i * 4), 0x00000000);
217	nv_wr32(dev, 0x00250c, 0x0000ffff);
218	nv_wr32(dev, 0x002048, 0x00000000);
219	nv_wr32(dev, 0x003228, 0x00000000);
220	nv_wr32(dev, 0x0032e8, 0x00000000);
221	nv_wr32(dev, 0x002410, 0x00000000);
222	nv_wr32(dev, 0x002420, 0x00000000);
223	nv_wr32(dev, 0x002058, 0x00000001);
224	nv_wr32(dev, 0x00221c, 0x00000000);
225	/* something with 0x2084, read/modify/write, no change */
226	nv_wr32(dev, 0x002040, 0x000000ff);	142	nv_wr32(dev, 0x002040, 0x000000ff);
227	nv_wr32(dev, 0x002500, 0x00000000);	143	nv_wr32(dev, 0x002044, 0x2101ffff);
228	nv_wr32(dev, 0x003200, 0x00000000);	144	nv_wr32(dev, 0x002058, 0x00000001);
229
230	nv_wr32(dev, NV04_PFIFO_DMA_TIMESLICE, 0x2101ffff);
231	}
232
233	static void
234	nv40_fifo_init_ramxx(struct drm_device *dev)
235	{
236	struct drm_nouveau_private *dev_priv = dev->dev_private;
237		145
238	nv_wr32(dev, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ \|	146	nv_wr32(dev, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ \|
239	((dev_priv->ramht->bits - 9) << 16) \|	147	((dev_priv->ramht->bits - 9) << 16) \|
@@ -244,65 +152,59 @@ nv40_fifo_init_ramxx(struct drm_device *dev)
244	case 0x47:	152	case 0x47:
245	case 0x49:	153	case 0x49:
246	case 0x4b:	154	case 0x4b:
247	nv_wr32(dev, 0x2230, 1);	155	nv_wr32(dev, 0x002230, 0x00000001);
248	break;
249	default:
250	break;
251	}
252
253	switch (dev_priv->chipset) {
254	case 0x40:	156	case 0x40:
255	case 0x41:	157	case 0x41:
256	case 0x42:	158	case 0x42:
257	case 0x43:	159	case 0x43:
258	case 0x45:	160	case 0x45:
259	case 0x47:
260	case 0x48:	161	case 0x48:
261	case 0x49:	162	nv_wr32(dev, 0x002220, 0x00030002);
262	case 0x4b:
263	nv_wr32(dev, NV40_PFIFO_RAMFC, 0x30002);
264	break;	163	break;
265	default:	164	default:
266	nv_wr32(dev, 0x2230, 0);	165	nv_wr32(dev, 0x002230, 0x00000000);
267	nv_wr32(dev, NV40_PFIFO_RAMFC,	166	nv_wr32(dev, 0x002220, ((dev_priv->vram_size - 512 * 1024 +
268	((dev_priv->vram_size - 512 * 1024 +	167	dev_priv->ramfc->pinst) >> 16) \|
269	dev_priv->ramfc->pinst) >> 16) \| (3 << 16));	168	0x00030000);
270	break;	169	break;
271	}	170	}
272	}
273
274	static void
275	nv40_fifo_init_intr(struct drm_device *dev)
276	{
277	nouveau_irq_register(dev, 8, nv04_fifo_isr);
278	nv_wr32(dev, 0x002100, 0xffffffff);
279	nv_wr32(dev, 0x002140, 0xffffffff);
280	}
281
282	int
283	nv40_fifo_init(struct drm_device *dev)
284	{
285	struct drm_nouveau_private *dev_priv = dev->dev_private;
286	struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
287	int i;
288		171
289	nv40_fifo_init_reset(dev);	172	nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1, priv->base.channels);
290	nv40_fifo_init_ramxx(dev);
291		173
292	nv40_fifo_do_load_context(dev, pfifo->channels - 1);	174	nv_wr32(dev, NV03_PFIFO_INTR_0, 0xffffffff);
293	nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1, pfifo->channels - 1);	175	nv_wr32(dev, NV03_PFIFO_INTR_EN_0, 0xffffffff);
294		176
295	nv40_fifo_init_intr(dev);
296	nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH0, 1);	177	nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH0, 1);
297	nv_wr32(dev, NV04_PFIFO_CACHE1_PULL0, 1);	178	nv_wr32(dev, NV04_PFIFO_CACHE1_PULL0, 1);
298	nv_wr32(dev, NV03_PFIFO_CACHES, 1);	179	nv_wr32(dev, NV03_PFIFO_CACHES, 1);
299		180
300	for (i = 0; i < dev_priv->engine.fifo.channels; i++) {	181	for (i = 0; i < priv->base.channels; i++) {
301	if (dev_priv->channels.ptr[i]) {	182	if (dev_priv->channels.ptr[i])
302	uint32_t mode = nv_rd32(dev, NV04_PFIFO_MODE);	183	nv_mask(dev, NV04_PFIFO_MODE, (1 << i), (1 << i));
303	nv_wr32(dev, NV04_PFIFO_MODE, mode \| (1 << i));
304	}
305	}	184	}
306		185
307	return 0;	186	return 0;
308	}	187	}
		188
		189	int
		190	nv40_fifo_create(struct drm_device *dev)
		191	{
		192	struct drm_nouveau_private *dev_priv = dev->dev_private;
		193	struct nv40_fifo_priv *priv;
		194
		195	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
		196	if (!priv)
		197	return -ENOMEM;
		198
		199	priv->base.base.destroy = nv04_fifo_destroy;
		200	priv->base.base.init = nv40_fifo_init;
		201	priv->base.base.fini = nv04_fifo_fini;
		202	priv->base.base.context_new = nv40_fifo_context_new;
		203	priv->base.base.context_del = nv04_fifo_context_del;
		204	priv->base.channels = 31;
		205	priv->ramfc_desc = nv40_ramfc;
		206	dev_priv->eng[NVOBJ_ENGINE_FIFO] = &priv->base.base;
		207
		208	nouveau_irq_register(dev, 8, nv04_fifo_isr);
		209	return 0;
		210	}