drm/nv04-nv10: Don't re-enable FIFO access multiple times after IRQ dispatch.

nvxx_graph_isr is already taking care of it. In some cases this
could've made you miss PGRAPH interrupts (e.g. when you were supposed
to get several IRQs of the same kind in a row).

Signed-off-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

1 files changed, 0 insertions, 3 deletions

diff --git a/drivers/gpu/drm/nouveau/nv04_graph.c b/drivers/gpu/drm/nouveau/nv04_graph.c
index 0bc616d35eb6..af75015068d6 100644
--- a/drivers/gpu/drm/nouveau/nv04_graph.c
+++ b/drivers/gpu/drm/nouveau/nv04_graph.c
@@ -373,7 +373,6 @@ nv04_graph_context_switch(struct drm_device *dev)
         struct nouveau_channel *chan = NULL;
         int chid;
 
-        pgraph->fifo_access(dev, false);
         nouveau_wait_for_idle(dev);
 
         /* If previous context is valid, we need to save it */
@@ -384,8 +383,6 @@ nv04_graph_context_switch(struct drm_device *dev)
         chan = dev_priv->channels.ptr[chid];
         if (chan)
                 nv04_graph_load_context(chan);
-
-        pgraph->fifo_access(dev, true);
 }
 
 static uint32_t *ctx_reg(struct graph_state *ctx, uint32_t reg)