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authorBen Skeggs <bskeggs@redhat.com>2010-09-01 01:24:35 -0400
committerBen Skeggs <bskeggs@redhat.com>2010-09-24 02:23:22 -0400
commite05c5a317efb03854950a3fcc5c9501bfefc7d68 (patch)
tree188a3d497848cd383e69734a17e4d76f7939056f /drivers/gpu/drm/nouveau/nouveau_ramht.c
parentfbd2895e45aebdb3d3ea73a3a796cf3bb9c912da (diff)
drm/nouveau: tidy ram{ht,fc,ro} a bit
Reviewed-by: Francisco Jerez <currojerez@riseup.net> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau/nouveau_ramht.c')
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_ramht.c23
1 files changed, 13 insertions, 10 deletions
diff --git a/drivers/gpu/drm/nouveau/nouveau_ramht.c b/drivers/gpu/drm/nouveau/nouveau_ramht.c
index 5f9d52f06305..ccbc8d69ea68 100644
--- a/drivers/gpu/drm/nouveau/nouveau_ramht.c
+++ b/drivers/gpu/drm/nouveau/nouveau_ramht.c
@@ -28,21 +28,23 @@
28#include "nouveau_ramht.h" 28#include "nouveau_ramht.h"
29 29
30static uint32_t 30static uint32_t
31nouveau_ramht_hash_handle(struct drm_device *dev, int channel, uint32_t handle) 31nouveau_ramht_hash_handle(struct nouveau_channel *chan, uint32_t handle)
32{ 32{
33 struct drm_device *dev = chan->dev;
33 struct drm_nouveau_private *dev_priv = dev->dev_private; 34 struct drm_nouveau_private *dev_priv = dev->dev_private;
35 struct nouveau_ramht *ramht = chan->ramht;
34 uint32_t hash = 0; 36 uint32_t hash = 0;
35 int i; 37 int i;
36 38
37 NV_DEBUG(dev, "ch%d handle=0x%08x\n", channel, handle); 39 NV_DEBUG(dev, "ch%d handle=0x%08x\n", chan->id, handle);
38 40
39 for (i = 32; i > 0; i -= dev_priv->ramht_bits) { 41 for (i = 32; i > 0; i -= ramht->bits) {
40 hash ^= (handle & ((1 << dev_priv->ramht_bits) - 1)); 42 hash ^= (handle & ((1 << ramht->bits) - 1));
41 handle >>= dev_priv->ramht_bits; 43 handle >>= ramht->bits;
42 } 44 }
43 45
44 if (dev_priv->card_type < NV_50) 46 if (dev_priv->card_type < NV_50)
45 hash ^= channel << (dev_priv->ramht_bits - 4); 47 hash ^= chan->id << (ramht->bits - 4);
46 hash <<= 3; 48 hash <<= 3;
47 49
48 NV_DEBUG(dev, "hash=0x%08x\n", hash); 50 NV_DEBUG(dev, "hash=0x%08x\n", hash);
@@ -103,7 +105,7 @@ nouveau_ramht_insert(struct nouveau_channel *chan, u32 handle,
103 } 105 }
104 } 106 }
105 107
106 co = ho = nouveau_ramht_hash_handle(dev, chan->id, handle); 108 co = ho = nouveau_ramht_hash_handle(chan, handle);
107 do { 109 do {
108 if (!nouveau_ramht_entry_valid(dev, ramht, co)) { 110 if (!nouveau_ramht_entry_valid(dev, ramht, co)) {
109 NV_DEBUG(dev, 111 NV_DEBUG(dev,
@@ -119,7 +121,7 @@ nouveau_ramht_insert(struct nouveau_channel *chan, u32 handle,
119 chan->id, co, nv_ro32(ramht, co)); 121 chan->id, co, nv_ro32(ramht, co));
120 122
121 co += 8; 123 co += 8;
122 if (co >= dev_priv->ramht_size) 124 if (co >= ramht->size)
123 co = 0; 125 co = 0;
124 } while (co != ho); 126 } while (co != ho);
125 127
@@ -149,7 +151,7 @@ nouveau_ramht_remove(struct nouveau_channel *chan, u32 handle)
149 break; 151 break;
150 } 152 }
151 153
152 co = ho = nouveau_ramht_hash_handle(dev, chan->id, handle); 154 co = ho = nouveau_ramht_hash_handle(chan, handle);
153 do { 155 do {
154 if (nouveau_ramht_entry_valid(dev, ramht, co) && 156 if (nouveau_ramht_entry_valid(dev, ramht, co) &&
155 (handle == nv_ro32(ramht, co))) { 157 (handle == nv_ro32(ramht, co))) {
@@ -163,7 +165,7 @@ nouveau_ramht_remove(struct nouveau_channel *chan, u32 handle)
163 } 165 }
164 166
165 co += 8; 167 co += 8;
166 if (co >= dev_priv->ramht_size) 168 if (co >= ramht->size)
167 co = 0; 169 co = 0;
168 } while (co != ho); 170 } while (co != ho);
169 171
@@ -196,6 +198,7 @@ nouveau_ramht_new(struct drm_device *dev, struct nouveau_gpuobj *gpuobj,
196 198
197 ramht->dev = dev; 199 ramht->dev = dev;
198 ramht->refcount = 1; 200 ramht->refcount = 1;
201 ramht->bits = drm_order(gpuobj->size / 8);
199 INIT_LIST_HEAD(&ramht->entries); 202 INIT_LIST_HEAD(&ramht->entries);
200 nouveau_gpuobj_ref(gpuobj, &ramht->gpuobj); 203 nouveau_gpuobj_ref(gpuobj, &ramht->gpuobj);
201 204