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authorDaniel Vetter <daniel.vetter@ffwll.ch>2012-02-10 10:52:55 -0500
committerDaniel Vetter <daniel.vetter@ffwll.ch>2012-02-10 11:14:49 -0500
commit9edd576d89a5b6d3e136d7dcab654d887c0d25b7 (patch)
treed19670de2256f8187321de3a41fa4a10d3c8e402 /drivers/gpu/drm/i915
parente21af88d39796c907c38648c824be3d646ffbe35 (diff)
parent28a4d5675857f6386930a324317281cb8ed1e5d0 (diff)
Merge remote-tracking branch 'airlied/drm-fixes' into drm-intel-next-queued
Back-merge from drm-fixes into drm-intel-next to sort out two things: - interlaced support: -fixes contains a bugfix to correctly clear interlaced configuration bits in case the bios sets up an interlaced mode and we want to set up the progressive mode (current kernels don't support interlaced). The actual feature work to support interlaced depends upon (and conflicts with) this bugfix. - forcewake voodoo to workaround missed IRQ issues: -fixes only enabled this for ivybridge, but some recent bug reports indicate that we need this on Sandybridge, too. But in a slightly different flavour and with other fixes and reworks on top. Additionally there are some forcewake cleanup patches heading to -next that would conflict with currrent -fixes. Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915')
-rw-r--r--drivers/gpu/drm/i915/i915_debugfs.c31
-rw-r--r--drivers/gpu/drm/i915/i915_dma.c1
-rw-r--r--drivers/gpu/drm/i915/i915_drv.c56
-rw-r--r--drivers/gpu/drm/i915/i915_drv.h10
-rw-r--r--drivers/gpu/drm/i915/i915_gem_execbuffer.c4
-rw-r--r--drivers/gpu/drm/i915/i915_irq.c3
-rw-r--r--drivers/gpu/drm/i915/i915_suspend.c11
-rw-r--r--drivers/gpu/drm/i915/intel_bios.h6
-rw-r--r--drivers/gpu/drm/i915/intel_crt.c23
-rw-r--r--drivers/gpu/drm/i915/intel_display.c38
-rw-r--r--drivers/gpu/drm/i915/intel_dp.c20
-rw-r--r--drivers/gpu/drm/i915/intel_lvds.c16
-rw-r--r--drivers/gpu/drm/i915/intel_ringbuffer.c41
-rw-r--r--drivers/gpu/drm/i915/intel_sdvo.c8
-rw-r--r--drivers/gpu/drm/i915/intel_sdvo_regs.h2
-rw-r--r--drivers/gpu/drm/i915/intel_sprite.c8
-rw-r--r--drivers/gpu/drm/i915/intel_tv.c138
17 files changed, 191 insertions, 225 deletions
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 5d24581452eb..ae73288a9699 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -122,11 +122,11 @@ static const char *cache_level_str(int type)
122static void 122static void
123describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) 123describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
124{ 124{
125 seq_printf(m, "%p: %s%s %8zd %04x %04x %d %d%s%s%s", 125 seq_printf(m, "%p: %s%s %8zdKiB %04x %04x %d %d%s%s%s",
126 &obj->base, 126 &obj->base,
127 get_pin_flag(obj), 127 get_pin_flag(obj),
128 get_tiling_flag(obj), 128 get_tiling_flag(obj),
129 obj->base.size, 129 obj->base.size / 1024,
130 obj->base.read_domains, 130 obj->base.read_domains,
131 obj->base.write_domain, 131 obj->base.write_domain,
132 obj->last_rendering_seqno, 132 obj->last_rendering_seqno,
@@ -615,7 +615,7 @@ static int i915_ringbuffer_info(struct seq_file *m, void *data)
615 seq_printf(m, " Size : %08x\n", ring->size); 615 seq_printf(m, " Size : %08x\n", ring->size);
616 seq_printf(m, " Active : %08x\n", intel_ring_get_active_head(ring)); 616 seq_printf(m, " Active : %08x\n", intel_ring_get_active_head(ring));
617 seq_printf(m, " NOPID : %08x\n", I915_READ_NOPID(ring)); 617 seq_printf(m, " NOPID : %08x\n", I915_READ_NOPID(ring));
618 if (IS_GEN6(dev)) { 618 if (IS_GEN6(dev) || IS_GEN7(dev)) {
619 seq_printf(m, " Sync 0 : %08x\n", I915_READ_SYNC_0(ring)); 619 seq_printf(m, " Sync 0 : %08x\n", I915_READ_SYNC_0(ring));
620 seq_printf(m, " Sync 1 : %08x\n", I915_READ_SYNC_1(ring)); 620 seq_printf(m, " Sync 1 : %08x\n", I915_READ_SYNC_1(ring));
621 } 621 }
@@ -1055,6 +1055,7 @@ static int gen6_drpc_info(struct seq_file *m)
1055 struct drm_device *dev = node->minor->dev; 1055 struct drm_device *dev = node->minor->dev;
1056 struct drm_i915_private *dev_priv = dev->dev_private; 1056 struct drm_i915_private *dev_priv = dev->dev_private;
1057 u32 rpmodectl1, gt_core_status, rcctl1; 1057 u32 rpmodectl1, gt_core_status, rcctl1;
1058 unsigned forcewake_count;
1058 int count=0, ret; 1059 int count=0, ret;
1059 1060
1060 1061
@@ -1062,9 +1063,13 @@ static int gen6_drpc_info(struct seq_file *m)
1062 if (ret) 1063 if (ret)
1063 return ret; 1064 return ret;
1064 1065
1065 if (atomic_read(&dev_priv->forcewake_count)) { 1066 spin_lock_irq(&dev_priv->gt_lock);
1066 seq_printf(m, "RC information inaccurate because userspace " 1067 forcewake_count = dev_priv->forcewake_count;
1067 "holds a reference \n"); 1068 spin_unlock_irq(&dev_priv->gt_lock);
1069
1070 if (forcewake_count) {
1071 seq_printf(m, "RC information inaccurate because somebody "
1072 "holds a forcewake reference \n");
1068 } else { 1073 } else {
1069 /* NB: we cannot use forcewake, else we read the wrong values */ 1074 /* NB: we cannot use forcewake, else we read the wrong values */
1070 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1)) 1075 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
@@ -1086,7 +1091,7 @@ static int gen6_drpc_info(struct seq_file *m)
1086 seq_printf(m, "SW control enabled: %s\n", 1091 seq_printf(m, "SW control enabled: %s\n",
1087 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == 1092 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1088 GEN6_RP_MEDIA_SW_MODE)); 1093 GEN6_RP_MEDIA_SW_MODE));
1089 seq_printf(m, "RC6 Enabled: %s\n", 1094 seq_printf(m, "RC1e Enabled: %s\n",
1090 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE)); 1095 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1091 seq_printf(m, "RC6 Enabled: %s\n", 1096 seq_printf(m, "RC6 Enabled: %s\n",
1092 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE)); 1097 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
@@ -1378,9 +1383,13 @@ static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data)
1378 struct drm_info_node *node = (struct drm_info_node *) m->private; 1383 struct drm_info_node *node = (struct drm_info_node *) m->private;
1379 struct drm_device *dev = node->minor->dev; 1384 struct drm_device *dev = node->minor->dev;
1380 struct drm_i915_private *dev_priv = dev->dev_private; 1385 struct drm_i915_private *dev_priv = dev->dev_private;
1386 unsigned forcewake_count;
1387
1388 spin_lock_irq(&dev_priv->gt_lock);
1389 forcewake_count = dev_priv->forcewake_count;
1390 spin_unlock_irq(&dev_priv->gt_lock);
1381 1391
1382 seq_printf(m, "forcewake count = %d\n", 1392 seq_printf(m, "forcewake count = %u\n", forcewake_count);
1383 atomic_read(&dev_priv->forcewake_count));
1384 1393
1385 return 0; 1394 return 0;
1386} 1395}
@@ -1713,7 +1722,7 @@ static int i915_forcewake_open(struct inode *inode, struct file *file)
1713 struct drm_i915_private *dev_priv = dev->dev_private; 1722 struct drm_i915_private *dev_priv = dev->dev_private;
1714 int ret; 1723 int ret;
1715 1724
1716 if (!IS_GEN6(dev)) 1725 if (INTEL_INFO(dev)->gen < 6)
1717 return 0; 1726 return 0;
1718 1727
1719 ret = mutex_lock_interruptible(&dev->struct_mutex); 1728 ret = mutex_lock_interruptible(&dev->struct_mutex);
@@ -1730,7 +1739,7 @@ int i915_forcewake_release(struct inode *inode, struct file *file)
1730 struct drm_device *dev = inode->i_private; 1739 struct drm_device *dev = inode->i_private;
1731 struct drm_i915_private *dev_priv = dev->dev_private; 1740 struct drm_i915_private *dev_priv = dev->dev_private;
1732 1741
1733 if (!IS_GEN6(dev)) 1742 if (INTEL_INFO(dev)->gen < 6)
1734 return 0; 1743 return 0;
1735 1744
1736 /* 1745 /*
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 40bfafa13b72..38dfcf91f400 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -2066,6 +2066,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
2066 if (!IS_I945G(dev) && !IS_I945GM(dev)) 2066 if (!IS_I945G(dev) && !IS_I945GM(dev))
2067 pci_enable_msi(dev->pdev); 2067 pci_enable_msi(dev->pdev);
2068 2068
2069 spin_lock_init(&dev_priv->gt_lock);
2069 spin_lock_init(&dev_priv->irq_lock); 2070 spin_lock_init(&dev_priv->irq_lock);
2070 spin_lock_init(&dev_priv->error_lock); 2071 spin_lock_init(&dev_priv->error_lock);
2071 spin_lock_init(&dev_priv->rps_lock); 2072 spin_lock_init(&dev_priv->rps_lock);
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index d92c92dea4ec..189041984aba 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -377,11 +377,12 @@ void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv)
377 */ 377 */
378void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv) 378void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
379{ 379{
380 WARN_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex)); 380 unsigned long irqflags;
381 381
382 /* Forcewake is atomic in case we get in here without the lock */ 382 spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
383 if (atomic_add_return(1, &dev_priv->forcewake_count) == 1) 383 if (dev_priv->forcewake_count++ == 0)
384 dev_priv->display.force_wake_get(dev_priv); 384 dev_priv->display.force_wake_get(dev_priv);
385 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
385} 386}
386 387
387void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv) 388void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
@@ -401,10 +402,12 @@ void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv)
401 */ 402 */
402void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv) 403void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
403{ 404{
404 WARN_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex)); 405 unsigned long irqflags;
405 406
406 if (atomic_dec_and_test(&dev_priv->forcewake_count)) 407 spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
408 if (--dev_priv->forcewake_count == 0)
407 dev_priv->display.force_wake_put(dev_priv); 409 dev_priv->display.force_wake_put(dev_priv);
410 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
408} 411}
409 412
410void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv) 413void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
@@ -606,9 +609,36 @@ static int ironlake_do_reset(struct drm_device *dev, u8 flags)
606static int gen6_do_reset(struct drm_device *dev, u8 flags) 609static int gen6_do_reset(struct drm_device *dev, u8 flags)
607{ 610{
608 struct drm_i915_private *dev_priv = dev->dev_private; 611 struct drm_i915_private *dev_priv = dev->dev_private;
612 int ret;
613 unsigned long irqflags;
609 614
610 I915_WRITE(GEN6_GDRST, GEN6_GRDOM_FULL); 615 /* Hold gt_lock across reset to prevent any register access
611 return wait_for((I915_READ(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500); 616 * with forcewake not set correctly
617 */
618 spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
619
620 /* Reset the chip */
621
622 /* GEN6_GDRST is not in the gt power well, no need to check
623 * for fifo space for the write or forcewake the chip for
624 * the read
625 */
626 I915_WRITE_NOTRACE(GEN6_GDRST, GEN6_GRDOM_FULL);
627
628 /* Spin waiting for the device to ack the reset request */
629 ret = wait_for((I915_READ_NOTRACE(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
630
631 /* If reset with a user forcewake, try to restore, otherwise turn it off */
632 if (dev_priv->forcewake_count)
633 dev_priv->display.force_wake_get(dev_priv);
634 else
635 dev_priv->display.force_wake_put(dev_priv);
636
637 /* Restore fifo count */
638 dev_priv->gt_fifo_count = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
639
640 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
641 return ret;
612} 642}
613 643
614/** 644/**
@@ -652,9 +682,6 @@ int i915_reset(struct drm_device *dev, u8 flags)
652 case 7: 682 case 7:
653 case 6: 683 case 6:
654 ret = gen6_do_reset(dev, flags); 684 ret = gen6_do_reset(dev, flags);
655 /* If reset with a user forcewake, try to restore */
656 if (atomic_read(&dev_priv->forcewake_count))
657 __gen6_gt_force_wake_get(dev_priv);
658 break; 685 break;
659 case 5: 686 case 5:
660 ret = ironlake_do_reset(dev, flags); 687 ret = ironlake_do_reset(dev, flags);
@@ -940,9 +967,14 @@ MODULE_LICENSE("GPL and additional rights");
940u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \ 967u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
941 u##x val = 0; \ 968 u##x val = 0; \
942 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ 969 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
943 gen6_gt_force_wake_get(dev_priv); \ 970 unsigned long irqflags; \
971 spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \
972 if (dev_priv->forcewake_count == 0) \
973 dev_priv->display.force_wake_get(dev_priv); \
944 val = read##y(dev_priv->regs + reg); \ 974 val = read##y(dev_priv->regs + reg); \
945 gen6_gt_force_wake_put(dev_priv); \ 975 if (dev_priv->forcewake_count == 0) \
976 dev_priv->display.force_wake_put(dev_priv); \
977 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \
946 } else { \ 978 } else { \
947 val = read##y(dev_priv->regs + reg); \ 979 val = read##y(dev_priv->regs + reg); \
948 } \ 980 } \
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 45b609e6b131..922aed33035d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -299,7 +299,13 @@ typedef struct drm_i915_private {
299 int relative_constants_mode; 299 int relative_constants_mode;
300 300
301 void __iomem *regs; 301 void __iomem *regs;
302 u32 gt_fifo_count; 302 /** gt_fifo_count and the subsequent register write are synchronized
303 * with dev->struct_mutex. */
304 unsigned gt_fifo_count;
305 /** forcewake_count is protected by gt_lock */
306 unsigned forcewake_count;
307 /** gt_lock is also taken in irq contexts. */
308 struct spinlock gt_lock;
303 309
304 struct intel_gmbus { 310 struct intel_gmbus {
305 struct i2c_adapter adapter; 311 struct i2c_adapter adapter;
@@ -754,8 +760,6 @@ typedef struct drm_i915_private {
754 760
755 struct drm_property *broadcast_rgb_property; 761 struct drm_property *broadcast_rgb_property;
756 struct drm_property *force_audio_property; 762 struct drm_property *force_audio_property;
757
758 atomic_t forcewake_count;
759} drm_i915_private_t; 763} drm_i915_private_t;
760 764
761enum i915_cache_level { 765enum i915_cache_level {
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 9835b2efd93e..81687af00893 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -807,9 +807,9 @@ intel_enable_semaphores(struct drm_device *dev)
807 if (i915_semaphores >= 0) 807 if (i915_semaphores >= 0)
808 return i915_semaphores; 808 return i915_semaphores;
809 809
810 /* Enable semaphores on SNB when IO remapping is off */ 810 /* Disable semaphores on SNB */
811 if (INTEL_INFO(dev)->gen == 6) 811 if (INTEL_INFO(dev)->gen == 6)
812 return !intel_iommu_enabled; 812 return 0;
813 813
814 return 1; 814 return 1;
815} 815}
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index cde1ce94563c..063b4577d4c6 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1784,7 +1784,8 @@ static void ironlake_irq_preinstall(struct drm_device *dev)
1784 INIT_WORK(&dev_priv->rps_work, gen6_pm_rps_work); 1784 INIT_WORK(&dev_priv->rps_work, gen6_pm_rps_work);
1785 1785
1786 I915_WRITE(HWSTAM, 0xeffe); 1786 I915_WRITE(HWSTAM, 0xeffe);
1787 if (IS_GEN6(dev) || IS_GEN7(dev)) { 1787
1788 if (IS_GEN6(dev)) {
1788 /* Workaround stalls observed on Sandy Bridge GPUs by 1789 /* Workaround stalls observed on Sandy Bridge GPUs by
1789 * making the blitter command streamer generate a 1790 * making the blitter command streamer generate a
1790 * write to the Hardware Status Page for 1791 * write to the Hardware Status Page for
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index 7886e4fb60e3..2b5eb229ff2c 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -28,14 +28,19 @@
28#include "drm.h" 28#include "drm.h"
29#include "i915_drm.h" 29#include "i915_drm.h"
30#include "intel_drv.h" 30#include "intel_drv.h"
31#include "i915_reg.h"
31 32
32static bool i915_pipe_enabled(struct drm_device *dev, enum pipe pipe) 33static bool i915_pipe_enabled(struct drm_device *dev, enum pipe pipe)
33{ 34{
34 struct drm_i915_private *dev_priv = dev->dev_private; 35 struct drm_i915_private *dev_priv = dev->dev_private;
35 u32 dpll_reg; 36 u32 dpll_reg;
36 37
38 /* On IVB, 3rd pipe shares PLL with another one */
39 if (pipe > 1)
40 return false;
41
37 if (HAS_PCH_SPLIT(dev)) 42 if (HAS_PCH_SPLIT(dev))
38 dpll_reg = (pipe == PIPE_A) ? _PCH_DPLL_A : _PCH_DPLL_B; 43 dpll_reg = PCH_DPLL(pipe);
39 else 44 else
40 dpll_reg = (pipe == PIPE_A) ? _DPLL_A : _DPLL_B; 45 dpll_reg = (pipe == PIPE_A) ? _DPLL_A : _DPLL_B;
41 46
@@ -822,7 +827,7 @@ int i915_save_state(struct drm_device *dev)
822 827
823 if (IS_IRONLAKE_M(dev)) 828 if (IS_IRONLAKE_M(dev))
824 ironlake_disable_drps(dev); 829 ironlake_disable_drps(dev);
825 if (IS_GEN6(dev)) 830 if (INTEL_INFO(dev)->gen >= 6)
826 gen6_disable_rps(dev); 831 gen6_disable_rps(dev);
827 832
828 /* Cache mode state */ 833 /* Cache mode state */
@@ -881,7 +886,7 @@ int i915_restore_state(struct drm_device *dev)
881 intel_init_emon(dev); 886 intel_init_emon(dev);
882 } 887 }
883 888
884 if (IS_GEN6(dev)) { 889 if (INTEL_INFO(dev)->gen >= 6) {
885 gen6_enable_rps(dev_priv); 890 gen6_enable_rps(dev_priv);
886 gen6_update_ring_freq(dev_priv); 891 gen6_update_ring_freq(dev_priv);
887 } 892 }
diff --git a/drivers/gpu/drm/i915/intel_bios.h b/drivers/gpu/drm/i915/intel_bios.h
index 8af3735e27c6..dbda6e3bdf07 100644
--- a/drivers/gpu/drm/i915/intel_bios.h
+++ b/drivers/gpu/drm/i915/intel_bios.h
@@ -467,8 +467,12 @@ struct edp_link_params {
467struct bdb_edp { 467struct bdb_edp {
468 struct edp_power_seq power_seqs[16]; 468 struct edp_power_seq power_seqs[16];
469 u32 color_depth; 469 u32 color_depth;
470 u32 sdrrs_msa_timing_delay;
471 struct edp_link_params link_params[16]; 470 struct edp_link_params link_params[16];
471 u32 sdrrs_msa_timing_delay;
472
473 /* ith bit indicates enabled/disabled for (i+1)th panel */
474 u16 edp_s3d_feature;
475 u16 edp_t3_optimization;
472} __attribute__ ((packed)); 476} __attribute__ ((packed));
473 477
474void intel_setup_bios(struct drm_device *dev); 478void intel_setup_bios(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index fee0ad02c6d0..dd729d46a61f 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -24,6 +24,7 @@
24 * Eric Anholt <eric@anholt.net> 24 * Eric Anholt <eric@anholt.net>
25 */ 25 */
26 26
27#include <linux/dmi.h>
27#include <linux/i2c.h> 28#include <linux/i2c.h>
28#include <linux/slab.h> 29#include <linux/slab.h>
29#include "drmP.h" 30#include "drmP.h"
@@ -540,6 +541,24 @@ static const struct drm_encoder_funcs intel_crt_enc_funcs = {
540 .destroy = intel_encoder_destroy, 541 .destroy = intel_encoder_destroy,
541}; 542};
542 543
544static int __init intel_no_crt_dmi_callback(const struct dmi_system_id *id)
545{
546 DRM_DEBUG_KMS("Skipping CRT initialization for %s\n", id->ident);
547 return 1;
548}
549
550static const struct dmi_system_id intel_no_crt[] = {
551 {
552 .callback = intel_no_crt_dmi_callback,
553 .ident = "ACER ZGB",
554 .matches = {
555 DMI_MATCH(DMI_SYS_VENDOR, "ACER"),
556 DMI_MATCH(DMI_PRODUCT_NAME, "ZGB"),
557 },
558 },
559 { }
560};
561
543void intel_crt_init(struct drm_device *dev) 562void intel_crt_init(struct drm_device *dev)
544{ 563{
545 struct drm_connector *connector; 564 struct drm_connector *connector;
@@ -547,6 +566,10 @@ void intel_crt_init(struct drm_device *dev)
547 struct intel_connector *intel_connector; 566 struct intel_connector *intel_connector;
548 struct drm_i915_private *dev_priv = dev->dev_private; 567 struct drm_i915_private *dev_priv = dev->dev_private;
549 568
569 /* Skip machines without VGA that falsely report hotplug events */
570 if (dmi_check_system(intel_no_crt))
571 return;
572
550 crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL); 573 crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL);
551 if (!crt) 574 if (!crt)
552 return; 575 return;
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 5ab967ce86cc..efe56a2c4f4b 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1901,7 +1901,7 @@ static void intel_update_fbc(struct drm_device *dev)
1901 if (enable_fbc < 0) { 1901 if (enable_fbc < 0) {
1902 DRM_DEBUG_KMS("fbc set to per-chip default\n"); 1902 DRM_DEBUG_KMS("fbc set to per-chip default\n");
1903 enable_fbc = 1; 1903 enable_fbc = 1;
1904 if (INTEL_INFO(dev)->gen <= 5) 1904 if (INTEL_INFO(dev)->gen <= 6)
1905 enable_fbc = 0; 1905 enable_fbc = 0;
1906 } 1906 }
1907 if (!enable_fbc) { 1907 if (!enable_fbc) {
@@ -5387,6 +5387,7 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
5387 } 5387 }
5388 } 5388 }
5389 5389
5390 pipeconf &= ~PIPECONF_INTERLACE_MASK;
5390 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { 5391 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5391 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; 5392 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5392 /* the chip adds 2 halflines automatically */ 5393 /* the chip adds 2 halflines automatically */
@@ -5397,7 +5398,7 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
5397 adjusted_mode->crtc_vsync_end -= 1; 5398 adjusted_mode->crtc_vsync_end -= 1;
5398 adjusted_mode->crtc_vsync_start -= 1; 5399 adjusted_mode->crtc_vsync_start -= 1;
5399 } else 5400 } else
5400 pipeconf &= ~PIPECONF_INTERLACE_MASK; /* progressive */ 5401 pipeconf |= PIPECONF_PROGRESSIVE;
5401 5402
5402 I915_WRITE(HTOTAL(pipe), 5403 I915_WRITE(HTOTAL(pipe),
5403 (adjusted_mode->crtc_hdisplay - 1) | 5404 (adjusted_mode->crtc_hdisplay - 1) |
@@ -5885,12 +5886,15 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5885 if (is_lvds) { 5886 if (is_lvds) {
5886 temp = I915_READ(PCH_LVDS); 5887 temp = I915_READ(PCH_LVDS);
5887 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP; 5888 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5888 if (HAS_PCH_CPT(dev)) 5889 if (HAS_PCH_CPT(dev)) {
5890 temp &= ~PORT_TRANS_SEL_MASK;
5889 temp |= PORT_TRANS_SEL_CPT(pipe); 5891 temp |= PORT_TRANS_SEL_CPT(pipe);
5890 else if (pipe == 1) 5892 } else {
5891 temp |= LVDS_PIPEB_SELECT; 5893 if (pipe == 1)
5892 else 5894 temp |= LVDS_PIPEB_SELECT;
5893 temp &= ~LVDS_PIPEB_SELECT; 5895 else
5896 temp &= ~LVDS_PIPEB_SELECT;
5897 }
5894 5898
5895 /* set the corresponsding LVDS_BORDER bit */ 5899 /* set the corresponsding LVDS_BORDER bit */
5896 temp |= dev_priv->lvds_border_bits; 5900 temp |= dev_priv->lvds_border_bits;
@@ -5976,6 +5980,7 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5976 } 5980 }
5977 } 5981 }
5978 5982
5983 pipeconf &= ~PIPECONF_INTERLACE_MASK;
5979 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { 5984 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5980 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; 5985 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5981 /* the chip adds 2 halflines automatically */ 5986 /* the chip adds 2 halflines automatically */
@@ -5986,7 +5991,7 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5986 adjusted_mode->crtc_vsync_end -= 1; 5991 adjusted_mode->crtc_vsync_end -= 1;
5987 adjusted_mode->crtc_vsync_start -= 1; 5992 adjusted_mode->crtc_vsync_start -= 1;
5988 } else 5993 } else
5989 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */ 5994 pipeconf |= PIPECONF_PROGRESSIVE;
5990 5995
5991 I915_WRITE(HTOTAL(pipe), 5996 I915_WRITE(HTOTAL(pipe),
5992 (adjusted_mode->crtc_hdisplay - 1) | 5997 (adjusted_mode->crtc_hdisplay - 1) |
@@ -8210,13 +8215,11 @@ static bool intel_enable_rc6(struct drm_device *dev)
8210 return 0; 8215 return 0;
8211 8216
8212 /* 8217 /*
8213 * Enable rc6 on Sandybridge if DMA remapping is disabled 8218 * Disable rc6 on Sandybridge
8214 */ 8219 */
8215 if (INTEL_INFO(dev)->gen == 6) { 8220 if (INTEL_INFO(dev)->gen == 6) {
8216 DRM_DEBUG_DRIVER("Sandybridge: intel_iommu_enabled %s -- RC6 %sabled\n", 8221 DRM_DEBUG_DRIVER("Sandybridge: RC6 disabled\n");
8217 intel_iommu_enabled ? "true" : "false", 8222 return 0;
8218 !intel_iommu_enabled ? "en" : "dis");
8219 return !intel_iommu_enabled;
8220 } 8223 }
8221 DRM_DEBUG_DRIVER("RC6 enabled\n"); 8224 DRM_DEBUG_DRIVER("RC6 enabled\n");
8222 return 1; 8225 return 1;
@@ -9105,12 +9108,9 @@ void intel_modeset_init(struct drm_device *dev)
9105 9108
9106 for (i = 0; i < dev_priv->num_pipe; i++) { 9109 for (i = 0; i < dev_priv->num_pipe; i++) {
9107 intel_crtc_init(dev, i); 9110 intel_crtc_init(dev, i);
9108 if (HAS_PCH_SPLIT(dev)) { 9111 ret = intel_plane_init(dev, i);
9109 ret = intel_plane_init(dev, i); 9112 if (ret)
9110 if (ret) 9113 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
9111 DRM_ERROR("plane %d init failed: %d\n",
9112 i, ret);
9113 }
9114 } 9114 }
9115 9115
9116 /* Just disable it once at startup */ 9116 /* Just disable it once at startup */
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 8f1148c04108..39eccf908a69 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -208,17 +208,8 @@ intel_dp_link_clock(uint8_t link_bw)
208 */ 208 */
209 209
210static int 210static int
211intel_dp_link_required(struct intel_dp *intel_dp, int pixel_clock, int check_bpp) 211intel_dp_link_required(int pixel_clock, int bpp)
212{ 212{
213 struct drm_crtc *crtc = intel_dp->base.base.crtc;
214 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
215 int bpp = 24;
216
217 if (check_bpp)
218 bpp = check_bpp;
219 else if (intel_crtc)
220 bpp = intel_crtc->bpp;
221
222 return (pixel_clock * bpp + 9) / 10; 213 return (pixel_clock * bpp + 9) / 10;
223} 214}
224 215
@@ -245,12 +236,11 @@ intel_dp_mode_valid(struct drm_connector *connector,
245 return MODE_PANEL; 236 return MODE_PANEL;
246 } 237 }
247 238
248 mode_rate = intel_dp_link_required(intel_dp, mode->clock, 0); 239 mode_rate = intel_dp_link_required(mode->clock, 24);
249 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes); 240 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
250 241
251 if (mode_rate > max_rate) { 242 if (mode_rate > max_rate) {
252 mode_rate = intel_dp_link_required(intel_dp, 243 mode_rate = intel_dp_link_required(mode->clock, 18);
253 mode->clock, 18);
254 if (mode_rate > max_rate) 244 if (mode_rate > max_rate)
255 return MODE_CLOCK_HIGH; 245 return MODE_CLOCK_HIGH;
256 else 246 else
@@ -682,7 +672,7 @@ intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
682 int lane_count, clock; 672 int lane_count, clock;
683 int max_lane_count = intel_dp_max_lane_count(intel_dp); 673 int max_lane_count = intel_dp_max_lane_count(intel_dp);
684 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0; 674 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
685 int bpp = mode->private_flags & INTEL_MODE_DP_FORCE_6BPC ? 18 : 0; 675 int bpp = mode->private_flags & INTEL_MODE_DP_FORCE_6BPC ? 18 : 24;
686 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 }; 676 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
687 677
688 if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) { 678 if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
@@ -700,7 +690,7 @@ intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
700 for (clock = 0; clock <= max_clock; clock++) { 690 for (clock = 0; clock <= max_clock; clock++) {
701 int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count); 691 int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
702 692
703 if (intel_dp_link_required(intel_dp, mode->clock, bpp) 693 if (intel_dp_link_required(mode->clock, bpp)
704 <= link_avail) { 694 <= link_avail) {
705 intel_dp->link_bw = bws[clock]; 695 intel_dp->link_bw = bws[clock];
706 intel_dp->lane_count = lane_count; 696 intel_dp->lane_count = lane_count;
diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index e44191132ac4..aa84832b0e1a 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -694,6 +694,14 @@ static const struct dmi_system_id intel_no_lvds[] = {
694 }, 694 },
695 { 695 {
696 .callback = intel_no_lvds_dmi_callback, 696 .callback = intel_no_lvds_dmi_callback,
697 .ident = "AOpen i45GMx-I",
698 .matches = {
699 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
700 DMI_MATCH(DMI_BOARD_NAME, "i45GMx-I"),
701 },
702 },
703 {
704 .callback = intel_no_lvds_dmi_callback,
697 .ident = "Aopen i945GTt-VFA", 705 .ident = "Aopen i945GTt-VFA",
698 .matches = { 706 .matches = {
699 DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"), 707 DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"),
@@ -708,6 +716,14 @@ static const struct dmi_system_id intel_no_lvds[] = {
708 }, 716 },
709 }, 717 },
710 { 718 {
719 .callback = intel_no_lvds_dmi_callback,
720 .ident = "Clientron E830",
721 .matches = {
722 DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
723 DMI_MATCH(DMI_PRODUCT_NAME, "E830"),
724 },
725 },
726 {
711 .callback = intel_no_lvds_dmi_callback, 727 .callback = intel_no_lvds_dmi_callback,
712 .ident = "Asus EeeBox PC EB1007", 728 .ident = "Asus EeeBox PC EB1007",
713 .matches = { 729 .matches = {
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 6e80f8368355..4956f1bff522 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -634,6 +634,19 @@ render_ring_add_request(struct intel_ring_buffer *ring,
634} 634}
635 635
636static u32 636static u32
637gen6_ring_get_seqno(struct intel_ring_buffer *ring)
638{
639 struct drm_device *dev = ring->dev;
640
641 /* Workaround to force correct ordering between irq and seqno writes on
642 * ivb (and maybe also on snb) by reading from a CS register (like
643 * ACTHD) before reading the status page. */
644 if (IS_GEN7(dev))
645 intel_ring_get_active_head(ring);
646 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
647}
648
649static u32
637ring_get_seqno(struct intel_ring_buffer *ring) 650ring_get_seqno(struct intel_ring_buffer *ring)
638{ 651{
639 return intel_read_status_page(ring, I915_GEM_HWS_INDEX); 652 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
@@ -790,17 +803,6 @@ ring_add_request(struct intel_ring_buffer *ring,
790} 803}
791 804
792static bool 805static bool
793gen7_blt_ring_get_irq(struct intel_ring_buffer *ring)
794{
795 /* The BLT ring on IVB appears to have broken synchronization
796 * between the seqno write and the interrupt, so that the
797 * interrupt appears first. Returning false here makes
798 * i915_wait_request() do a polling loop, instead.
799 */
800 return false;
801}
802
803static bool
804gen6_ring_get_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag) 806gen6_ring_get_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag)
805{ 807{
806 struct drm_device *dev = ring->dev; 808 struct drm_device *dev = ring->dev;
@@ -809,6 +811,12 @@ gen6_ring_get_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag)
809 if (!dev->irq_enabled) 811 if (!dev->irq_enabled)
810 return false; 812 return false;
811 813
814 /* It looks like we need to prevent the gt from suspending while waiting
815 * for an notifiy irq, otherwise irqs seem to get lost on at least the
816 * blt/bsd rings on ivb. */
817 if (IS_GEN7(dev))
818 gen6_gt_force_wake_get(dev_priv);
819
812 spin_lock(&ring->irq_lock); 820 spin_lock(&ring->irq_lock);
813 if (ring->irq_refcount++ == 0) { 821 if (ring->irq_refcount++ == 0) {
814 ring->irq_mask &= ~rflag; 822 ring->irq_mask &= ~rflag;
@@ -833,6 +841,9 @@ gen6_ring_put_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag)
833 ironlake_disable_irq(dev_priv, gflag); 841 ironlake_disable_irq(dev_priv, gflag);
834 } 842 }
835 spin_unlock(&ring->irq_lock); 843 spin_unlock(&ring->irq_lock);
844
845 if (IS_GEN7(dev))
846 gen6_gt_force_wake_put(dev_priv);
836} 847}
837 848
838static bool 849static bool
@@ -1339,7 +1350,7 @@ static const struct intel_ring_buffer gen6_bsd_ring = {
1339 .write_tail = gen6_bsd_ring_write_tail, 1350 .write_tail = gen6_bsd_ring_write_tail,
1340 .flush = gen6_ring_flush, 1351 .flush = gen6_ring_flush,
1341 .add_request = gen6_add_request, 1352 .add_request = gen6_add_request,
1342 .get_seqno = ring_get_seqno, 1353 .get_seqno = gen6_ring_get_seqno,
1343 .irq_get = gen6_bsd_ring_get_irq, 1354 .irq_get = gen6_bsd_ring_get_irq,
1344 .irq_put = gen6_bsd_ring_put_irq, 1355 .irq_put = gen6_bsd_ring_put_irq,
1345 .dispatch_execbuffer = gen6_ring_dispatch_execbuffer, 1356 .dispatch_execbuffer = gen6_ring_dispatch_execbuffer,
@@ -1398,7 +1409,7 @@ static const struct intel_ring_buffer gen6_blt_ring = {
1398 .write_tail = ring_write_tail, 1409 .write_tail = ring_write_tail,
1399 .flush = blt_ring_flush, 1410 .flush = blt_ring_flush,
1400 .add_request = gen6_add_request, 1411 .add_request = gen6_add_request,
1401 .get_seqno = ring_get_seqno, 1412 .get_seqno = gen6_ring_get_seqno,
1402 .irq_get = blt_ring_get_irq, 1413 .irq_get = blt_ring_get_irq,
1403 .irq_put = blt_ring_put_irq, 1414 .irq_put = blt_ring_put_irq,
1404 .dispatch_execbuffer = gen6_ring_dispatch_execbuffer, 1415 .dispatch_execbuffer = gen6_ring_dispatch_execbuffer,
@@ -1420,6 +1431,7 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
1420 ring->flush = gen6_render_ring_flush; 1431 ring->flush = gen6_render_ring_flush;
1421 ring->irq_get = gen6_render_ring_get_irq; 1432 ring->irq_get = gen6_render_ring_get_irq;
1422 ring->irq_put = gen6_render_ring_put_irq; 1433 ring->irq_put = gen6_render_ring_put_irq;
1434 ring->get_seqno = gen6_ring_get_seqno;
1423 } else if (IS_GEN5(dev)) { 1435 } else if (IS_GEN5(dev)) {
1424 ring->add_request = pc_render_add_request; 1436 ring->add_request = pc_render_add_request;
1425 ring->get_seqno = pc_render_get_seqno; 1437 ring->get_seqno = pc_render_get_seqno;
@@ -1498,8 +1510,5 @@ int intel_init_blt_ring_buffer(struct drm_device *dev)
1498 1510
1499 *ring = gen6_blt_ring; 1511 *ring = gen6_blt_ring;
1500 1512
1501 if (IS_GEN7(dev))
1502 ring->irq_get = gen7_blt_ring_get_irq;
1503
1504 return intel_init_ring_buffer(dev, ring); 1513 return intel_init_ring_buffer(dev, ring);
1505} 1514}
diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index f7b9268df266..e334ec33a47d 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -1066,15 +1066,13 @@ static void intel_sdvo_mode_set(struct drm_encoder *encoder,
1066 1066
1067 /* Set the SDVO control regs. */ 1067 /* Set the SDVO control regs. */
1068 if (INTEL_INFO(dev)->gen >= 4) { 1068 if (INTEL_INFO(dev)->gen >= 4) {
1069 sdvox = 0; 1069 /* The real mode polarity is set by the SDVO commands, using
1070 * struct intel_sdvo_dtd. */
1071 sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH;
1070 if (intel_sdvo->is_hdmi) 1072 if (intel_sdvo->is_hdmi)
1071 sdvox |= intel_sdvo->color_range; 1073 sdvox |= intel_sdvo->color_range;
1072 if (INTEL_INFO(dev)->gen < 5) 1074 if (INTEL_INFO(dev)->gen < 5)
1073 sdvox |= SDVO_BORDER_ENABLE; 1075 sdvox |= SDVO_BORDER_ENABLE;
1074 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1075 sdvox |= SDVO_VSYNC_ACTIVE_HIGH;
1076 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1077 sdvox |= SDVO_HSYNC_ACTIVE_HIGH;
1078 } else { 1076 } else {
1079 sdvox = I915_READ(intel_sdvo->sdvo_reg); 1077 sdvox = I915_READ(intel_sdvo->sdvo_reg);
1080 switch (intel_sdvo->sdvo_reg) { 1078 switch (intel_sdvo->sdvo_reg) {
diff --git a/drivers/gpu/drm/i915/intel_sdvo_regs.h b/drivers/gpu/drm/i915/intel_sdvo_regs.h
index 4aa6f343e49a..6b7b22f4d63e 100644
--- a/drivers/gpu/drm/i915/intel_sdvo_regs.h
+++ b/drivers/gpu/drm/i915/intel_sdvo_regs.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright © 2006-2007 Intel Corporation 2 * Copyright © 2006-2007 Intel Corporation
3 * 3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a 4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"), 5 * copy of this software and associated documentation files (the "Software"),
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index ad3bd929aec7..98444ab68bc3 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -466,10 +466,8 @@ intel_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
466 mutex_lock(&dev->struct_mutex); 466 mutex_lock(&dev->struct_mutex);
467 467
468 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL); 468 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
469 if (ret) { 469 if (ret)
470 DRM_ERROR("failed to pin object\n");
471 goto out_unlock; 470 goto out_unlock;
472 }
473 471
474 intel_plane->obj = obj; 472 intel_plane->obj = obj;
475 473
@@ -632,10 +630,8 @@ intel_plane_init(struct drm_device *dev, enum pipe pipe)
632 unsigned long possible_crtcs; 630 unsigned long possible_crtcs;
633 int ret; 631 int ret;
634 632
635 if (!(IS_GEN6(dev) || IS_GEN7(dev))) { 633 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
636 DRM_ERROR("new plane code only for SNB+\n");
637 return -ENODEV; 634 return -ENODEV;
638 }
639 635
640 intel_plane = kzalloc(sizeof(struct intel_plane), GFP_KERNEL); 636 intel_plane = kzalloc(sizeof(struct intel_plane), GFP_KERNEL);
641 if (!intel_plane) 637 if (!intel_plane)
diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c
index f3c6a9a8b081..1571be37ce3e 100644
--- a/drivers/gpu/drm/i915/intel_tv.c
+++ b/drivers/gpu/drm/i915/intel_tv.c
@@ -417,7 +417,7 @@ static const struct tv_mode tv_modes[] = {
417 { 417 {
418 .name = "NTSC-M", 418 .name = "NTSC-M",
419 .clock = 108000, 419 .clock = 108000,
420 .refresh = 29970, 420 .refresh = 59940,
421 .oversample = TV_OVERSAMPLE_8X, 421 .oversample = TV_OVERSAMPLE_8X,
422 .component_only = 0, 422 .component_only = 0,
423 /* 525 Lines, 60 Fields, 15.734KHz line, Sub-Carrier 3.580MHz */ 423 /* 525 Lines, 60 Fields, 15.734KHz line, Sub-Carrier 3.580MHz */
@@ -460,7 +460,7 @@ static const struct tv_mode tv_modes[] = {
460 { 460 {
461 .name = "NTSC-443", 461 .name = "NTSC-443",
462 .clock = 108000, 462 .clock = 108000,
463 .refresh = 29970, 463 .refresh = 59940,
464 .oversample = TV_OVERSAMPLE_8X, 464 .oversample = TV_OVERSAMPLE_8X,
465 .component_only = 0, 465 .component_only = 0,
466 /* 525 Lines, 60 Fields, 15.734KHz line, Sub-Carrier 4.43MHz */ 466 /* 525 Lines, 60 Fields, 15.734KHz line, Sub-Carrier 4.43MHz */
@@ -502,7 +502,7 @@ static const struct tv_mode tv_modes[] = {
502 { 502 {
503 .name = "NTSC-J", 503 .name = "NTSC-J",
504 .clock = 108000, 504 .clock = 108000,
505 .refresh = 29970, 505 .refresh = 59940,
506 .oversample = TV_OVERSAMPLE_8X, 506 .oversample = TV_OVERSAMPLE_8X,
507 .component_only = 0, 507 .component_only = 0,
508 508
@@ -545,7 +545,7 @@ static const struct tv_mode tv_modes[] = {
545 { 545 {
546 .name = "PAL-M", 546 .name = "PAL-M",
547 .clock = 108000, 547 .clock = 108000,
548 .refresh = 29970, 548 .refresh = 59940,
549 .oversample = TV_OVERSAMPLE_8X, 549 .oversample = TV_OVERSAMPLE_8X,
550 .component_only = 0, 550 .component_only = 0,
551 551
@@ -589,7 +589,7 @@ static const struct tv_mode tv_modes[] = {
589 /* 625 Lines, 50 Fields, 15.625KHz line, Sub-Carrier 4.434MHz */ 589 /* 625 Lines, 50 Fields, 15.625KHz line, Sub-Carrier 4.434MHz */
590 .name = "PAL-N", 590 .name = "PAL-N",
591 .clock = 108000, 591 .clock = 108000,
592 .refresh = 25000, 592 .refresh = 50000,
593 .oversample = TV_OVERSAMPLE_8X, 593 .oversample = TV_OVERSAMPLE_8X,
594 .component_only = 0, 594 .component_only = 0,
595 595
@@ -634,7 +634,7 @@ static const struct tv_mode tv_modes[] = {
634 /* 625 Lines, 50 Fields, 15.625KHz line, Sub-Carrier 4.434MHz */ 634 /* 625 Lines, 50 Fields, 15.625KHz line, Sub-Carrier 4.434MHz */
635 .name = "PAL", 635 .name = "PAL",
636 .clock = 108000, 636 .clock = 108000,
637 .refresh = 25000, 637 .refresh = 50000,
638 .oversample = TV_OVERSAMPLE_8X, 638 .oversample = TV_OVERSAMPLE_8X,
639 .component_only = 0, 639 .component_only = 0,
640 640
@@ -674,78 +674,6 @@ static const struct tv_mode tv_modes[] = {
674 .filter_table = filter_table, 674 .filter_table = filter_table,
675 }, 675 },
676 { 676 {
677 .name = "480p@59.94Hz",
678 .clock = 107520,
679 .refresh = 59940,
680 .oversample = TV_OVERSAMPLE_4X,
681 .component_only = 1,
682
683 .hsync_end = 64, .hblank_end = 122,
684 .hblank_start = 842, .htotal = 857,
685
686 .progressive = true, .trilevel_sync = false,
687
688 .vsync_start_f1 = 12, .vsync_start_f2 = 12,
689 .vsync_len = 12,
690
691 .veq_ena = false,
692
693 .vi_end_f1 = 44, .vi_end_f2 = 44,
694 .nbr_end = 479,
695
696 .burst_ena = false,
697
698 .filter_table = filter_table,
699 },
700 {
701 .name = "480p@60Hz",
702 .clock = 107520,
703 .refresh = 60000,
704 .oversample = TV_OVERSAMPLE_4X,
705 .component_only = 1,
706
707 .hsync_end = 64, .hblank_end = 122,
708 .hblank_start = 842, .htotal = 856,
709
710 .progressive = true, .trilevel_sync = false,
711
712 .vsync_start_f1 = 12, .vsync_start_f2 = 12,
713 .vsync_len = 12,
714
715 .veq_ena = false,
716
717 .vi_end_f1 = 44, .vi_end_f2 = 44,
718 .nbr_end = 479,
719
720 .burst_ena = false,
721
722 .filter_table = filter_table,
723 },
724 {
725 .name = "576p",
726 .clock = 107520,
727 .refresh = 50000,
728 .oversample = TV_OVERSAMPLE_4X,
729 .component_only = 1,
730
731 .hsync_end = 64, .hblank_end = 139,
732 .hblank_start = 859, .htotal = 863,
733
734 .progressive = true, .trilevel_sync = false,
735
736 .vsync_start_f1 = 10, .vsync_start_f2 = 10,
737 .vsync_len = 10,
738
739 .veq_ena = false,
740
741 .vi_end_f1 = 48, .vi_end_f2 = 48,
742 .nbr_end = 575,
743
744 .burst_ena = false,
745
746 .filter_table = filter_table,
747 },
748 {
749 .name = "720p@60Hz", 677 .name = "720p@60Hz",
750 .clock = 148800, 678 .clock = 148800,
751 .refresh = 60000, 679 .refresh = 60000,
@@ -770,30 +698,6 @@ static const struct tv_mode tv_modes[] = {
770 .filter_table = filter_table, 698 .filter_table = filter_table,
771 }, 699 },
772 { 700 {
773 .name = "720p@59.94Hz",
774 .clock = 148800,
775 .refresh = 59940,
776 .oversample = TV_OVERSAMPLE_2X,
777 .component_only = 1,
778
779 .hsync_end = 80, .hblank_end = 300,
780 .hblank_start = 1580, .htotal = 1651,
781
782 .progressive = true, .trilevel_sync = true,
783
784 .vsync_start_f1 = 10, .vsync_start_f2 = 10,
785 .vsync_len = 10,
786
787 .veq_ena = false,
788
789 .vi_end_f1 = 29, .vi_end_f2 = 29,
790 .nbr_end = 719,
791
792 .burst_ena = false,
793
794 .filter_table = filter_table,
795 },
796 {
797 .name = "720p@50Hz", 701 .name = "720p@50Hz",
798 .clock = 148800, 702 .clock = 148800,
799 .refresh = 50000, 703 .refresh = 50000,
@@ -821,7 +725,7 @@ static const struct tv_mode tv_modes[] = {
821 { 725 {
822 .name = "1080i@50Hz", 726 .name = "1080i@50Hz",
823 .clock = 148800, 727 .clock = 148800,
824 .refresh = 25000, 728 .refresh = 50000,
825 .oversample = TV_OVERSAMPLE_2X, 729 .oversample = TV_OVERSAMPLE_2X,
826 .component_only = 1, 730 .component_only = 1,
827 731
@@ -847,7 +751,7 @@ static const struct tv_mode tv_modes[] = {
847 { 751 {
848 .name = "1080i@60Hz", 752 .name = "1080i@60Hz",
849 .clock = 148800, 753 .clock = 148800,
850 .refresh = 30000, 754 .refresh = 60000,
851 .oversample = TV_OVERSAMPLE_2X, 755 .oversample = TV_OVERSAMPLE_2X,
852 .component_only = 1, 756 .component_only = 1,
853 757
@@ -870,32 +774,6 @@ static const struct tv_mode tv_modes[] = {
870 774
871 .filter_table = filter_table, 775 .filter_table = filter_table,
872 }, 776 },
873 {
874 .name = "1080i@59.94Hz",
875 .clock = 148800,
876 .refresh = 29970,
877 .oversample = TV_OVERSAMPLE_2X,
878 .component_only = 1,
879
880 .hsync_end = 88, .hblank_end = 235,
881 .hblank_start = 2155, .htotal = 2201,
882
883 .progressive = false, .trilevel_sync = true,
884
885 .vsync_start_f1 = 4, .vsync_start_f2 = 5,
886 .vsync_len = 10,
887
888 .veq_ena = true, .veq_start_f1 = 4,
889 .veq_start_f2 = 4, .veq_len = 10,
890
891
892 .vi_end_f1 = 21, .vi_end_f2 = 22,
893 .nbr_end = 539,
894
895 .burst_ena = false,
896
897 .filter_table = filter_table,
898 },
899}; 777};
900 778
901static struct intel_tv *enc_to_intel_tv(struct drm_encoder *encoder) 779static struct intel_tv *enc_to_intel_tv(struct drm_encoder *encoder)
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-09 23:57:00 -0500