drm/i915: i8xx interrupt handler

gen2 hardware has some significant differences from the other interrupt
routines that were glossed over and then forgotten about in the
transition to KMS. Such as

- 16bit IIR
- PendingFlip status bit

This patch reintroduces a handler specifically for gen2 for the purpose
of handling pageflips correctly, simplifying code in the process.

v2: Also fixup ring get/put irq to only access 16bit registers (Daniel)

Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=24202
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=41793
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
[danvet: use posting_read16 in intel_ringbuffer.c and kill _driver
from the function names.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

1 files changed, 49 insertions, 4 deletions

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 12d9bc789dfb..6249a7fa9acc 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -678,6 +678,41 @@ i9xx_ring_put_irq(struct intel_ring_buffer *ring)
         spin_unlock(&ring->irq_lock);
 }
 
+static bool
+i8xx_ring_get_irq(struct intel_ring_buffer *ring)
+{
+        struct drm_device *dev = ring->dev;
+        drm_i915_private_t *dev_priv = dev->dev_private;
+
+        if (!dev->irq_enabled)
+                return false;
+
+        spin_lock(&ring->irq_lock);
+        if (ring->irq_refcount++ == 0) {
+                dev_priv->irq_mask &= ~ring->irq_enable_mask;
+                I915_WRITE16(IMR, dev_priv->irq_mask);
+                POSTING_READ16(IMR);
+        }
+        spin_unlock(&ring->irq_lock);
+
+        return true;
+}
+
+static void
+i8xx_ring_put_irq(struct intel_ring_buffer *ring)
+{
+        struct drm_device *dev = ring->dev;
+        drm_i915_private_t *dev_priv = dev->dev_private;
+
+        spin_lock(&ring->irq_lock);
+        if (--ring->irq_refcount == 0) {
+                dev_priv->irq_mask |= ring->irq_enable_mask;
+                I915_WRITE16(IMR, dev_priv->irq_mask);
+                POSTING_READ16(IMR);
+        }
+        spin_unlock(&ring->irq_lock);
+}
+
 void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
 {
         struct drm_device *dev = ring->dev;
@@ -1310,8 +1345,13 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
                 else
                         ring->flush = gen4_render_ring_flush;
                 ring->get_seqno = ring_get_seqno;
-                ring->irq_get = i9xx_ring_get_irq;
-                ring->irq_put = i9xx_ring_put_irq;
+                if (IS_GEN2(dev)) {
+                        ring->irq_get = i8xx_ring_get_irq;
+                        ring->irq_put = i8xx_ring_put_irq;
+                } else {
+                        ring->irq_get = i9xx_ring_get_irq;
+                        ring->irq_put = i9xx_ring_put_irq;
+                }
                 ring->irq_enable_mask = I915_USER_INTERRUPT;
         }
         ring->write_tail = ring_write_tail;
@@ -1358,8 +1398,13 @@ int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
         else
                 ring->flush = gen4_render_ring_flush;
         ring->get_seqno = ring_get_seqno;
-        ring->irq_get = i9xx_ring_get_irq;
-        ring->irq_put = i9xx_ring_put_irq;
+        if (IS_GEN2(dev)) {
+                ring->irq_get = i8xx_ring_get_irq;
+                ring->irq_put = i8xx_ring_put_irq;
+        } else {
+                ring->irq_get = i9xx_ring_get_irq;
+                ring->irq_put = i9xx_ring_put_irq;
+        }
         ring->irq_enable_mask = I915_USER_INTERRUPT;
         ring->write_tail = ring_write_tail;
         if (INTEL_INFO(dev)->gen >= 4)