diff options
author | Chris Wilson <chris@chris-wilson.co.uk> | 2011-02-16 04:36:05 -0500 |
---|---|---|
committer | Chris Wilson <chris@chris-wilson.co.uk> | 2011-02-16 04:44:30 -0500 |
commit | 9035a97a32836d0e456ddafaaf249a844e6e4b5e (patch) | |
tree | 41ec3db083bdb46cd831f0d39db1fe294ae7d55f /drivers/gpu/drm/i915/intel_ringbuffer.c | |
parent | fe16d949b45036d9f80e20e07bde1ddacc930b10 (diff) | |
parent | 452858338aec31c1f4414bf07f31663690479869 (diff) |
Merge branch 'drm-intel-fixes' into drm-intel-next
Grab the latest stabilisation bits from -fixes and some suspend and
resume fixes from linus.
Conflicts:
drivers/gpu/drm/i915/i915_drv.h
drivers/gpu/drm/i915/i915_irq.c
Diffstat (limited to 'drivers/gpu/drm/i915/intel_ringbuffer.c')
-rw-r--r-- | drivers/gpu/drm/i915/intel_ringbuffer.c | 26 |
1 files changed, 16 insertions, 10 deletions
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index ec7175e0dcd8..789c47801ba8 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c | |||
@@ -1051,22 +1051,25 @@ static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring, | |||
1051 | } | 1051 | } |
1052 | 1052 | ||
1053 | static int gen6_ring_flush(struct intel_ring_buffer *ring, | 1053 | static int gen6_ring_flush(struct intel_ring_buffer *ring, |
1054 | u32 invalidate_domains, | 1054 | u32 invalidate, u32 flush) |
1055 | u32 flush_domains) | ||
1056 | { | 1055 | { |
1056 | uint32_t cmd; | ||
1057 | int ret; | 1057 | int ret; |
1058 | 1058 | ||
1059 | if ((flush_domains & I915_GEM_DOMAIN_RENDER) == 0) | 1059 | if (((invalidate | flush) & I915_GEM_GPU_DOMAINS) == 0) |
1060 | return 0; | 1060 | return 0; |
1061 | 1061 | ||
1062 | ret = intel_ring_begin(ring, 4); | 1062 | ret = intel_ring_begin(ring, 4); |
1063 | if (ret) | 1063 | if (ret) |
1064 | return ret; | 1064 | return ret; |
1065 | 1065 | ||
1066 | intel_ring_emit(ring, MI_FLUSH_DW); | 1066 | cmd = MI_FLUSH_DW; |
1067 | intel_ring_emit(ring, 0); | 1067 | if (invalidate & I915_GEM_GPU_DOMAINS) |
1068 | cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD; | ||
1069 | intel_ring_emit(ring, cmd); | ||
1068 | intel_ring_emit(ring, 0); | 1070 | intel_ring_emit(ring, 0); |
1069 | intel_ring_emit(ring, 0); | 1071 | intel_ring_emit(ring, 0); |
1072 | intel_ring_emit(ring, MI_NOOP); | ||
1070 | intel_ring_advance(ring); | 1073 | intel_ring_advance(ring); |
1071 | return 0; | 1074 | return 0; |
1072 | } | 1075 | } |
@@ -1222,22 +1225,25 @@ static int blt_ring_begin(struct intel_ring_buffer *ring, | |||
1222 | } | 1225 | } |
1223 | 1226 | ||
1224 | static int blt_ring_flush(struct intel_ring_buffer *ring, | 1227 | static int blt_ring_flush(struct intel_ring_buffer *ring, |
1225 | u32 invalidate_domains, | 1228 | u32 invalidate, u32 flush) |
1226 | u32 flush_domains) | ||
1227 | { | 1229 | { |
1230 | uint32_t cmd; | ||
1228 | int ret; | 1231 | int ret; |
1229 | 1232 | ||
1230 | if ((flush_domains & I915_GEM_DOMAIN_RENDER) == 0) | 1233 | if (((invalidate | flush) & I915_GEM_DOMAIN_RENDER) == 0) |
1231 | return 0; | 1234 | return 0; |
1232 | 1235 | ||
1233 | ret = blt_ring_begin(ring, 4); | 1236 | ret = blt_ring_begin(ring, 4); |
1234 | if (ret) | 1237 | if (ret) |
1235 | return ret; | 1238 | return ret; |
1236 | 1239 | ||
1237 | intel_ring_emit(ring, MI_FLUSH_DW); | 1240 | cmd = MI_FLUSH_DW; |
1238 | intel_ring_emit(ring, 0); | 1241 | if (invalidate & I915_GEM_DOMAIN_RENDER) |
1242 | cmd |= MI_INVALIDATE_TLB; | ||
1243 | intel_ring_emit(ring, cmd); | ||
1239 | intel_ring_emit(ring, 0); | 1244 | intel_ring_emit(ring, 0); |
1240 | intel_ring_emit(ring, 0); | 1245 | intel_ring_emit(ring, 0); |
1246 | intel_ring_emit(ring, MI_NOOP); | ||
1241 | intel_ring_advance(ring); | 1247 | intel_ring_advance(ring); |
1242 | return 0; | 1248 | return 0; |
1243 | } | 1249 | } |