drm/i915: Check VBIOS value for determining LVDS dual channel mode, too

Currently i915 driver checks [PCH_]LVDS register bits to decide
whether to set up the dual-link or the single-link mode.  This relies
implicitly on that BIOS initializes the register properly at boot.
However, BIOS doesn't initialize it always.  When the machine is
booted with the closed lid, BIOS skips the LVDS reg initialization.
This ends up in blank output on a machine with a dual-link LVDS when
you open the lid after the boot.

This patch adds a workaround for that problem by checking the initial
LVDS register value in VBT.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=37742
Tested-By: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Signed-off-by: Takashi Iwai <tiwai@suse.de>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

1 files changed, 24 insertions, 6 deletions

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 683002fb63d1..a76ac2eb9938 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -360,6 +360,27 @@ static const intel_limit_t intel_limits_ironlake_display_port = {
         .find_pll = intel_find_pll_ironlake_dp,
 };
 
+static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
+                              unsigned int reg)
+{
+        unsigned int val;
+
+        if (dev_priv->lvds_val)
+                val = dev_priv->lvds_val;
+        else {
+                /* BIOS should set the proper LVDS register value at boot, but
+                 * in reality, it doesn't set the value when the lid is closed;
+                 * we need to check "the value to be set" in VBT when LVDS
+                 * register is uninitialized.
+                 */
+                val = I915_READ(reg);
+                if (!(val & ~LVDS_DETECTED))
+                        val = dev_priv->bios_lvds_val;
+                dev_priv->lvds_val = val;
+        }
+        return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
+}
+
 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
                                                 int refclk)
 {
@@ -368,8 +389,7 @@ static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
         const intel_limit_t *limit;
 
         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
-                if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
-                    LVDS_CLKB_POWER_UP) {
+                if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
                         /* LVDS dual channel */
                         if (refclk == 100000)
                                 limit = &intel_limits_ironlake_dual_lvds_100m;
@@ -397,8 +417,7 @@ static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
         const intel_limit_t *limit;
 
         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
-                if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
-                    LVDS_CLKB_POWER_UP)
+                if (is_dual_link_lvds(dev_priv, LVDS))
                         /* LVDS with dual channel */
                         limit = &intel_limits_g4x_dual_channel_lvds;
                 else
@@ -536,8 +555,7 @@ intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
                  * reliably set up different single/dual channel state, if we
                  * even can.
                  */
-                if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
-                    LVDS_CLKB_POWER_UP)
+                if (is_dual_link_lvds(dev_priv, LVDS))
                         clock.p2 = limit->p2.p2_fast;
                 else
                         clock.p2 = limit->p2.p2_slow;