diff options
author | Chris Wilson <chris@chris-wilson.co.uk> | 2010-10-03 05:56:11 -0400 |
---|---|---|
committer | Chris Wilson <chris@chris-wilson.co.uk> | 2010-10-03 05:56:11 -0400 |
commit | 58e10eb92d36a62568349d985c9140d9be16a99c (patch) | |
tree | 6ffaf65e64db390f6a28c1dca8c43d4eb1493f94 /drivers/gpu/drm/i915/i915_reg.h | |
parent | 1cdf7fef793c715d8c4998575aba3741fa4a0b01 (diff) | |
parent | ab7ad7f6451580aa7eccc0ba62807c872088a8f9 (diff) |
Merge branch 'drm-intel-fixes' into drm-intel-next
Conflicts:
drivers/gpu/drm/i915/i915_gem_evict.c
drivers/gpu/drm/i915/intel_display.c
drivers/gpu/drm/i915/intel_dp.c
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
-rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 58cfea25a645..d02de212e6ad 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h | |||
@@ -2105,7 +2105,7 @@ | |||
2105 | 2105 | ||
2106 | /* Pipe A */ | 2106 | /* Pipe A */ |
2107 | #define PIPEADSL 0x70000 | 2107 | #define PIPEADSL 0x70000 |
2108 | #define DSL_LINEMASK 0x00000fff | 2108 | #define DSL_LINEMASK 0x00000fff |
2109 | #define PIPEACONF 0x70008 | 2109 | #define PIPEACONF 0x70008 |
2110 | #define PIPECONF_ENABLE (1<<31) | 2110 | #define PIPECONF_ENABLE (1<<31) |
2111 | #define PIPECONF_DISABLE 0 | 2111 | #define PIPECONF_DISABLE 0 |
@@ -2162,13 +2162,14 @@ | |||
2162 | #define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */ | 2162 | #define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */ |
2163 | #define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1) | 2163 | #define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1) |
2164 | #define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0) | 2164 | #define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0) |
2165 | #define PIPE_BPC_MASK (7 << 5) /* Ironlake */ | 2165 | #define PIPE_BPC_MASK (7 << 5) /* Ironlake */ |
2166 | #define PIPE_8BPC (0 << 5) | 2166 | #define PIPE_8BPC (0 << 5) |
2167 | #define PIPE_10BPC (1 << 5) | 2167 | #define PIPE_10BPC (1 << 5) |
2168 | #define PIPE_6BPC (2 << 5) | 2168 | #define PIPE_6BPC (2 << 5) |
2169 | #define PIPE_12BPC (3 << 5) | 2169 | #define PIPE_12BPC (3 << 5) |
2170 | 2170 | ||
2171 | #define PIPECONF(pipe) _PIPE(pipe, PIPEACONF, PIPEBCONF) | 2171 | #define PIPECONF(pipe) _PIPE(pipe, PIPEACONF, PIPEBCONF) |
2172 | #define PIPEDSL(pipe) _PIPE(pipe, PIPEADSL, PIPEBDSL) | ||
2172 | 2173 | ||
2173 | #define DSPARB 0x70030 | 2174 | #define DSPARB 0x70030 |
2174 | #define DSPARB_CSTART_MASK (0x7f << 7) | 2175 | #define DSPARB_CSTART_MASK (0x7f << 7) |