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authorZhenyu Wang <zhenyuw@linux.intel.com>2009-07-23 13:00:32 -0400
committerEric Anholt <eric@anholt.net>2009-07-29 18:16:19 -0400
commit32f9d658aee5be09ebdd28fc730630e61d0b46db (patch)
tree66f1417c8631659c17874876ab7036eb4fdf2ec9 /drivers/gpu/drm/i915/i915_reg.h
parent5eb08b69f510fadaba77eb9a1bda0f7299c4ebcc (diff)
drm/i915: Add eDP support on IGDNG mobile chip
This adds embedded DisplayPort support on next mobile chip which aims to replace origin LVDS port. VBT's driver feature block has been used to determine the type of current internal panel for eDP or LVDS. Currently no panel fitting support for eDP and backlight control would be added in future. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h16
1 files changed, 16 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4518a9489ed1..2955083aa471 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1395,6 +1395,7 @@
1395#define TV_V_CHROMA_42 0x684a8 1395#define TV_V_CHROMA_42 0x684a8
1396 1396
1397/* Display Port */ 1397/* Display Port */
1398#define DP_A 0x64000 /* eDP */
1398#define DP_B 0x64100 1399#define DP_B 0x64100
1399#define DP_C 0x64200 1400#define DP_C 0x64200
1400#define DP_D 0x64300 1401#define DP_D 0x64300
@@ -1437,9 +1438,17 @@
1437/* Mystic DPCD version 1.1 special mode */ 1438/* Mystic DPCD version 1.1 special mode */
1438#define DP_ENHANCED_FRAMING (1 << 18) 1439#define DP_ENHANCED_FRAMING (1 << 18)
1439 1440
1441/* eDP */
1442#define DP_PLL_FREQ_270MHZ (0 << 16)
1443#define DP_PLL_FREQ_160MHZ (1 << 16)
1444#define DP_PLL_FREQ_MASK (3 << 16)
1445
1440/** locked once port is enabled */ 1446/** locked once port is enabled */
1441#define DP_PORT_REVERSAL (1 << 15) 1447#define DP_PORT_REVERSAL (1 << 15)
1442 1448
1449/* eDP */
1450#define DP_PLL_ENABLE (1 << 14)
1451
1443/** sends the clock on lane 15 of the PEG for debug */ 1452/** sends the clock on lane 15 of the PEG for debug */
1444#define DP_CLOCK_OUTPUT_ENABLE (1 << 13) 1453#define DP_CLOCK_OUTPUT_ENABLE (1 << 13)
1445 1454
@@ -1464,6 +1473,13 @@
1464 * is 20 bytes in each direction, hence the 5 fixed 1473 * is 20 bytes in each direction, hence the 5 fixed
1465 * data registers 1474 * data registers
1466 */ 1475 */
1476#define DPA_AUX_CH_CTL 0x64010
1477#define DPA_AUX_CH_DATA1 0x64014
1478#define DPA_AUX_CH_DATA2 0x64018
1479#define DPA_AUX_CH_DATA3 0x6401c
1480#define DPA_AUX_CH_DATA4 0x64020
1481#define DPA_AUX_CH_DATA5 0x64024
1482
1467#define DPB_AUX_CH_CTL 0x64110 1483#define DPB_AUX_CH_CTL 0x64110
1468#define DPB_AUX_CH_DATA1 0x64114 1484#define DPB_AUX_CH_DATA1 0x64114
1469#define DPB_AUX_CH_DATA2 0x64118 1485#define DPB_AUX_CH_DATA2 0x64118