diff options
author | Xiang, Haihao <haihao.xiang@intel.com> | 2010-09-19 09:40:43 -0400 |
---|---|---|
committer | Chris Wilson <chris@chris-wilson.co.uk> | 2010-09-21 06:19:57 -0400 |
commit | 881f47b64723f4d697084533491a489e3e74b10f (patch) | |
tree | 8659b98e6dc7706af79e2d8c6894bc9dd2cb6217 /drivers/gpu/drm/i915/i915_irq.c | |
parent | a3f07cd53e31c1c27364e56266a541b9467c1895 (diff) |
drm/i915: add a new BSD ring buffer for Sandybridge
This ring buffer is used for video decoding/encoding on Sandybridge.
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_irq.c')
-rw-r--r-- | drivers/gpu/drm/i915/i915_irq.c | 15 |
1 files changed, 10 insertions, 5 deletions
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index b1e7655288d8..d4c053e1c376 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c | |||
@@ -300,6 +300,10 @@ static irqreturn_t ironlake_irq_handler(struct drm_device *dev) | |||
300 | u32 de_iir, gt_iir, de_ier, pch_iir; | 300 | u32 de_iir, gt_iir, de_ier, pch_iir; |
301 | struct drm_i915_master_private *master_priv; | 301 | struct drm_i915_master_private *master_priv; |
302 | struct intel_ring_buffer *render_ring = &dev_priv->render_ring; | 302 | struct intel_ring_buffer *render_ring = &dev_priv->render_ring; |
303 | u32 bsd_usr_interrupt = GT_BSD_USER_INTERRUPT; | ||
304 | |||
305 | if (IS_GEN6(dev)) | ||
306 | bsd_usr_interrupt = GT_GEN6_BSD_USER_INTERRUPT; | ||
303 | 307 | ||
304 | /* disable master interrupt before clearing iir */ | 308 | /* disable master interrupt before clearing iir */ |
305 | de_ier = I915_READ(DEIER); | 309 | de_ier = I915_READ(DEIER); |
@@ -331,10 +335,9 @@ static irqreturn_t ironlake_irq_handler(struct drm_device *dev) | |||
331 | mod_timer(&dev_priv->hangcheck_timer, | 335 | mod_timer(&dev_priv->hangcheck_timer, |
332 | jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)); | 336 | jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)); |
333 | } | 337 | } |
334 | if (gt_iir & GT_BSD_USER_INTERRUPT) | 338 | if (gt_iir & bsd_usr_interrupt) |
335 | DRM_WAKEUP(&dev_priv->bsd_ring.irq_queue); | 339 | DRM_WAKEUP(&dev_priv->bsd_ring.irq_queue); |
336 | 340 | ||
337 | |||
338 | if (de_iir & DE_GSE) | 341 | if (de_iir & DE_GSE) |
339 | intel_opregion_gse_intr(dev); | 342 | intel_opregion_gse_intr(dev); |
340 | 343 | ||
@@ -1436,17 +1439,19 @@ static int ironlake_irq_postinstall(struct drm_device *dev) | |||
1436 | I915_WRITE(DEIER, dev_priv->de_irq_enable_reg); | 1439 | I915_WRITE(DEIER, dev_priv->de_irq_enable_reg); |
1437 | (void) I915_READ(DEIER); | 1440 | (void) I915_READ(DEIER); |
1438 | 1441 | ||
1439 | /* Gen6 only needs render pipe_control now */ | ||
1440 | if (IS_GEN6(dev)) | 1442 | if (IS_GEN6(dev)) |
1441 | render_mask = GT_PIPE_NOTIFY; | 1443 | render_mask = GT_PIPE_NOTIFY | GT_GEN6_BSD_USER_INTERRUPT; |
1442 | 1444 | ||
1443 | dev_priv->gt_irq_mask_reg = ~render_mask; | 1445 | dev_priv->gt_irq_mask_reg = ~render_mask; |
1444 | dev_priv->gt_irq_enable_reg = render_mask; | 1446 | dev_priv->gt_irq_enable_reg = render_mask; |
1445 | 1447 | ||
1446 | I915_WRITE(GTIIR, I915_READ(GTIIR)); | 1448 | I915_WRITE(GTIIR, I915_READ(GTIIR)); |
1447 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg); | 1449 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg); |
1448 | if (IS_GEN6(dev)) | 1450 | if (IS_GEN6(dev)) { |
1449 | I915_WRITE(GEN6_RENDER_IMR, ~GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT); | 1451 | I915_WRITE(GEN6_RENDER_IMR, ~GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT); |
1452 | I915_WRITE(GEN6_BSD_IMR, ~GEN6_BSD_IMR_USER_INTERRUPT); | ||
1453 | } | ||
1454 | |||
1450 | I915_WRITE(GTIER, dev_priv->gt_irq_enable_reg); | 1455 | I915_WRITE(GTIER, dev_priv->gt_irq_enable_reg); |
1451 | (void) I915_READ(GTIER); | 1456 | (void) I915_READ(GTIER); |
1452 | 1457 | ||