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authorChris Wilson <chris@chris-wilson.co.uk>2012-03-21 06:48:18 -0400
committerDaniel Vetter <daniel.vetter@ffwll.ch>2012-04-01 06:26:05 -0400
commit7dd4906586274f3945f2aeaaa5a33b451c3b4bba (patch)
treefa0258dcd2325e7ffef04adedf471a0a5afa8f10 /drivers/gpu/drm/i915/i915_gem.c
parent55a254ac63a3ac1867d1501030e7fba69c7d4aeb (diff)
drm/i915: Mark untiled BLT commands as fenced on gen2/3
The BLT commands on gen2/3 utilize the fence registers and so we cannot modify any fences for the object whilst those commands are in flight. Currently we marked tiled commands as occupying a fence, but forgot to restrict the untiled commands from preventing a fence being assigned before they were completed. One side-effect is that we ten have to double check that a fence was allocated for a fenced buffer during move-to-active. Reported-by: Jiri Slaby <jirislaby@gmail.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=43427 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=47990 Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Testcase: i-g-t/tests/gem_tiled_after_untiled_blt Tested-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: stable@kernel.org Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_gem.c')
-rw-r--r--drivers/gpu/drm/i915/i915_gem.c15
1 files changed, 9 insertions, 6 deletions
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 97e659985223..4c65c639f772 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1472,16 +1472,19 @@ i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1472 list_move_tail(&obj->ring_list, &ring->active_list); 1472 list_move_tail(&obj->ring_list, &ring->active_list);
1473 1473
1474 obj->last_rendering_seqno = seqno; 1474 obj->last_rendering_seqno = seqno;
1475 if (obj->fenced_gpu_access) {
1476 struct drm_i915_fence_reg *reg;
1477
1478 BUG_ON(obj->fence_reg == I915_FENCE_REG_NONE);
1479 1475
1476 if (obj->fenced_gpu_access) {
1480 obj->last_fenced_seqno = seqno; 1477 obj->last_fenced_seqno = seqno;
1481 obj->last_fenced_ring = ring; 1478 obj->last_fenced_ring = ring;
1482 1479
1483 reg = &dev_priv->fence_regs[obj->fence_reg]; 1480 /* Bump MRU to take account of the delayed flush */
1484 list_move_tail(&reg->lru_list, &dev_priv->mm.fence_list); 1481 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1482 struct drm_i915_fence_reg *reg;
1483
1484 reg = &dev_priv->fence_regs[obj->fence_reg];
1485 list_move_tail(&reg->lru_list,
1486 &dev_priv->mm.fence_list);
1487 }
1485 } 1488 }
1486} 1489}
1487 1490