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authorChris Wilson <chris@chris-wilson.co.uk>2010-09-30 11:53:18 -0400
committerChris Wilson <chris@chris-wilson.co.uk>2010-10-01 09:45:22 -0400
commit069efc1dac477a4a51e42c0fe50bdcf85ada626a (patch)
treeb24caf4bc67882566a1bb458532173eb19c016eb /drivers/gpu/drm/i915/i915_gem.c
parent812ed4924328adf94f45c664b6a4c710a69167e2 (diff)
drm/i915: Clear fence registers on GPU reset
When the GPU is reset, the fence registers are invalidated, so release the objects and clear them out. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_gem.c')
-rw-r--r--drivers/gpu/drm/i915/i915_gem.c14
1 files changed, 13 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index c033c5a2e9fc..db9d36fb5883 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1826,10 +1826,11 @@ static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
1826 } 1826 }
1827} 1827}
1828 1828
1829void i915_gem_reset_lists(struct drm_device *dev) 1829void i915_gem_reset(struct drm_device *dev)
1830{ 1830{
1831 struct drm_i915_private *dev_priv = dev->dev_private; 1831 struct drm_i915_private *dev_priv = dev->dev_private;
1832 struct drm_i915_gem_object *obj_priv; 1832 struct drm_i915_gem_object *obj_priv;
1833 int i;
1833 1834
1834 i915_gem_reset_ring_lists(dev_priv, &dev_priv->render_ring); 1835 i915_gem_reset_ring_lists(dev_priv, &dev_priv->render_ring);
1835 if (HAS_BSD(dev)) 1836 if (HAS_BSD(dev))
@@ -1858,6 +1859,17 @@ void i915_gem_reset_lists(struct drm_device *dev)
1858 { 1859 {
1859 obj_priv->base.read_domains &= ~I915_GEM_GPU_DOMAINS; 1860 obj_priv->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
1860 } 1861 }
1862
1863 /* The fence registers are invalidated so clear them out */
1864 for (i = 0; i < 16; i++) {
1865 struct drm_i915_fence_reg *reg;
1866
1867 reg = &dev_priv->fence_regs[i];
1868 if (!reg->obj)
1869 continue;
1870
1871 i915_gem_clear_fence_reg(reg->obj);
1872 }
1861} 1873}
1862 1874
1863/** 1875/**