drm/i915: Add CxSR support on Pineview DDR3

Pineview with DDR3 memory has different latencies to enable CxSR.
This patch updates CxSR latency table to add Pineview DDR3 latency
configuration. It also adds one flag "is_ddr3" for checking DDR3
setting in MCHBAR.

Cc: Shaohua Li <shaohua.li@intel.com>
Cc: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Li Peng <peng.li@intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>

1 files changed, 4 insertions, 0 deletions

diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 12e92f2cc3a7..a5f401664845 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1491,6 +1491,10 @@ static void i915_pineview_get_mem_freq(struct drm_device *dev)
                 dev_priv->mem_freq = 800;
                 break;
         }
+
+        /* detect pineview DDR3 setting */
+        tmp = I915_READ(CSHRDDR3CTL);
+        dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
 }
 
 static void i915_ironlake_get_mem_freq(struct drm_device *dev)