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authorBorislav Petkov <borislav.petkov@amd.com>2010-08-27 11:03:34 -0400
committerBorislav Petkov <bp@amd64.org>2010-10-21 08:48:02 -0400
commitded506232865e8e932bc21c87f48170d50db4d97 (patch)
treec773d4644925eade05a9f0876e98c70750f6e97a /drivers/edac/mce_amd.c
parentdd53bce4e8987f6848840d42bbeead5221eff308 (diff)
EDAC, MCE: Warn about LS MCEs on F14h
F14h CPUs do not generate LS MCEs so exit early and warn the user in case this path is ever hit that something else might be going haywire. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
Diffstat (limited to 'drivers/edac/mce_amd.c')
-rw-r--r--drivers/edac/mce_amd.c18
1 files changed, 13 insertions, 5 deletions
diff --git a/drivers/edac/mce_amd.c b/drivers/edac/mce_amd.c
index 60d5d9f4dfee..3c161672a84b 100644
--- a/drivers/edac/mce_amd.c
+++ b/drivers/edac/mce_amd.c
@@ -339,19 +339,27 @@ wrong_bu_mce:
339 339
340static void amd_decode_ls_mce(struct mce *m) 340static void amd_decode_ls_mce(struct mce *m)
341{ 341{
342 u32 ec = m->status & 0xffff; 342 u16 ec = m->status & 0xffff;
343 u32 xec = (m->status >> 16) & 0xf; 343 u8 xec = (m->status >> 16) & 0xf;
344
345 if (boot_cpu_data.x86 == 0x14) {
346 pr_emerg("You shouldn't be seeing an LS MCE on this cpu family,"
347 " please report on LKML.\n");
348 return;
349 }
344 350
345 pr_emerg(HW_ERR "Load Store Error"); 351 pr_emerg(HW_ERR "Load Store Error");
346 352
347 if (xec == 0x0) { 353 if (xec == 0x0) {
348 u8 rrrr = (ec >> 4) & 0xf; 354 u8 r4 = (ec >> 4) & 0xf;
349 355
350 if (!BUS_ERROR(ec) || (rrrr != 0x3 && rrrr != 0x4)) 356 if (!BUS_ERROR(ec) || (r4 != R4_DRD && r4 != R4_DWR))
351 goto wrong_ls_mce; 357 goto wrong_ls_mce;
352 358
353 pr_cont(" during %s.\n", RRRR_MSG(ec)); 359 pr_cont(" during %s.\n", RRRR_MSG(ec));
354 } 360 } else
361 goto wrong_ls_mce;
362
355 return; 363 return;
356 364
357wrong_ls_mce: 365wrong_ls_mce: