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authorBorislav Petkov <borislav.petkov@amd.com>2010-11-24 13:52:09 -0500
committerBorislav Petkov <borislav.petkov@amd.com>2011-01-07 05:38:31 -0500
commit390944439f746824faec51b576f50cb5ef18745b (patch)
tree5fd15e75e8e5e5d3dc1e176c655829f9d0f83aa9 /drivers/edac/amd64_edac.c
parent360b7f3c602ed80ce8c6b2585dcb76883a440c17 (diff)
EDAC: Fixup scrubrate manipulation
Make the ->{get|set}_sdram_scrub_rate return the actual scrub rate bandwidth it succeeded setting and remove superfluous arg pointer used for that. A negative value returned still means that an error occurred while setting the scrubrate. Document this for future reference. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
Diffstat (limited to 'drivers/edac/amd64_edac.c')
-rw-r--r--drivers/edac/amd64_edac.c24
1 files changed, 12 insertions, 12 deletions
diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index f621aa8becee..8c176fb8a8fb 100644
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -77,7 +77,11 @@ static int ddr3_dbam[] = { [0] = -1,
77 *FIXME: Produce a better mapping/linearisation. 77 *FIXME: Produce a better mapping/linearisation.
78 */ 78 */
79 79
80struct scrubrate scrubrates[] = { 80
81struct scrubrate {
82 u32 scrubval; /* bit pattern for scrub rate */
83 u32 bandwidth; /* bandwidth consumed (bytes/sec) */
84} scrubrates[] = {
81 { 0x01, 1600000000UL}, 85 { 0x01, 1600000000UL},
82 { 0x02, 800000000UL}, 86 { 0x02, 800000000UL},
83 { 0x03, 400000000UL}, 87 { 0x03, 400000000UL},
@@ -151,14 +155,12 @@ static int __amd64_set_scrub_rate(struct pci_dev *ctl, u32 new_bw, u32 min_rate)
151 } 155 }
152 156
153 scrubval = scrubrates[i].scrubval; 157 scrubval = scrubrates[i].scrubval;
154 if (scrubval)
155 amd64_info("Setting scrub rate bandwidth: %u\n",
156 scrubrates[i].bandwidth);
157 else
158 amd64_info("Turning scrubbing off.\n");
159 158
160 pci_write_bits32(ctl, K8_SCRCTRL, scrubval, 0x001F); 159 pci_write_bits32(ctl, K8_SCRCTRL, scrubval, 0x001F);
161 160
161 if (scrubval)
162 return scrubrates[i].bandwidth;
163
162 return 0; 164 return 0;
163} 165}
164 166
@@ -169,11 +171,11 @@ static int amd64_set_scrub_rate(struct mem_ctl_info *mci, u32 bw)
169 return __amd64_set_scrub_rate(pvt->F3, bw, pvt->min_scrubrate); 171 return __amd64_set_scrub_rate(pvt->F3, bw, pvt->min_scrubrate);
170} 172}
171 173
172static int amd64_get_scrub_rate(struct mem_ctl_info *mci, u32 *bw) 174static int amd64_get_scrub_rate(struct mem_ctl_info *mci)
173{ 175{
174 struct amd64_pvt *pvt = mci->pvt_info; 176 struct amd64_pvt *pvt = mci->pvt_info;
175 u32 scrubval = 0; 177 u32 scrubval = 0;
176 int status = -1, i; 178 int i, retval = -EINVAL;
177 179
178 amd64_read_pci_cfg(pvt->F3, K8_SCRCTRL, &scrubval); 180 amd64_read_pci_cfg(pvt->F3, K8_SCRCTRL, &scrubval);
179 181
@@ -183,13 +185,11 @@ static int amd64_get_scrub_rate(struct mem_ctl_info *mci, u32 *bw)
183 185
184 for (i = 0; i < ARRAY_SIZE(scrubrates); i++) { 186 for (i = 0; i < ARRAY_SIZE(scrubrates); i++) {
185 if (scrubrates[i].scrubval == scrubval) { 187 if (scrubrates[i].scrubval == scrubval) {
186 *bw = scrubrates[i].bandwidth; 188 retval = scrubrates[i].bandwidth;
187 status = 0;
188 break; 189 break;
189 } 190 }
190 } 191 }
191 192 return retval;
192 return status;
193} 193}
194 194
195/* Map from a CSROW entry to the mask entry that operates on it */ 195/* Map from a CSROW entry to the mask entry that operates on it */