MIPS: Cavium: Add EDAC support.

Drivers for EDAC on Cavium.  Supported subsystems are:

 o CPU primary caches.  These are parity protected only, so only error
   reporting.
 o Second level cache - ECC protected, provides SECDED.
 o Memory: ECC / SECDEC if used with suitable DRAM modules.  The driver will
   will only initialize if ECC is enabled on a system so is safe to run on
   non-ECC memory.
 o PCI: Parity error reporting

Since it is very hard to test this sort of code the implementation is very
conservative and uses polling where possible for now.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Reviewed-by: Borislav Petkov <borislav.petkov@amd.com>

1 files changed, 32 insertions, 1 deletions

diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
index 409b92b8d346..a9db20815a39 100644
--- a/drivers/edac/Kconfig
+++ b/drivers/edac/Kconfig
@@ -7,7 +7,7 @@
 menuconfig EDAC
         bool "EDAC (Error Detection And Correction) reporting"
         depends on HAS_IOMEM
-        depends on X86 || PPC || TILE || ARM
+        depends on X86 || PPC || TILE || ARM || EDAC_SUPPORT
         help
           EDAC is designed to report errors in the core system.
           These are low-level errors that are reported in the CPU or
@@ -27,6 +27,9 @@ menuconfig EDAC
           There is also a mailing list for the EDAC project, which can
           be found via the sourceforge page.
 
+config EDAC_SUPPORT
+        bool
+
 if EDAC
 
 comment "Reporting subsystems"
@@ -316,4 +319,32 @@ config EDAC_HIGHBANK_L2
           Support for error detection and correction on the
           Calxeda Highbank memory controller.
 
+config EDAC_OCTEON_PC
+        tristate "Cavium Octeon Primary Caches"
+        depends on EDAC_MM_EDAC && CPU_CAVIUM_OCTEON
+        help
+          Support for error detection and correction on the primary caches of
+          the cnMIPS cores of Cavium Octeon family SOCs.
+
+config EDAC_OCTEON_L2C
+        tristate "Cavium Octeon Secondary Caches (L2C)"
+        depends on EDAC_MM_EDAC && CPU_CAVIUM_OCTEON
+        help
+          Support for error detection and correction on the
+          Cavium Octeon family of SOCs.
+
+config EDAC_OCTEON_LMC
+        tristate "Cavium Octeon DRAM Memory Controller (LMC)"
+        depends on EDAC_MM_EDAC && CPU_CAVIUM_OCTEON
+        help
+          Support for error detection and correction on the
+          Cavium Octeon family of SOCs.
+
+config EDAC_OCTEON_PCI
+        tristate "Cavium Octeon PCI Controller"
+        depends on EDAC_MM_EDAC && PCI && CPU_CAVIUM_OCTEON
+        help
+          Support for error detection and correction on the
+          Cavium Octeon family of SOCs.
+
 endif # EDAC